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Date: Thu, 4 Apr 2024 19:36:00 -0400
From: Eric Biggers <ebiggers@kernel.org>
To: Dave Hansen <dave.hansen@intel.com>
Cc: linux-crypto@vger.kernel.org, x86@kernel.org,
	linux-kernel@vger.kernel.org, Ard Biesheuvel <ardb@kernel.org>,
	Andy Lutomirski <luto@kernel.org>,
	"Chang S . Bae" <chang.seok.bae@intel.com>
Subject: Re: [PATCH v2 6/6] crypto: x86/aes-xts - wire up VAES + AVX10/512
 implementation
Message-ID: <20240404233600.GA746@quark.localdomain>
References: <20240329080355.2871-1-ebiggers@kernel.org>
 <20240329080355.2871-7-ebiggers@kernel.org>
 <f5461df0-6609-42db-850c-de6a32728fe2@intel.com>
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In-Reply-To: <f5461df0-6609-42db-850c-de6a32728fe2@intel.com>

On Thu, Apr 04, 2024 at 01:34:04PM -0700, Dave Hansen wrote:
> On 3/29/24 01:03, Eric Biggers wrote:
> > +static const struct x86_cpu_id zmm_exclusion_list[] = {
> > +	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_SKYLAKE_X },
> > +	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_X },
> > +	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_D },
> > +	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE },
> > +	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_L },
> > +	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_NNPI },
> > +	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_TIGERLAKE_L },
> > +	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_TIGERLAKE },
> > +	/* Allow Rocket Lake and later, and Sapphire Rapids and later. */
> > +	/* Also allow AMD CPUs (starting with Zen 4, the first with AVX-512). */
> > +	{},
> > +};
> 
> A hard-coded model/family exclusion list is not great.
> 
> It'll break when running in guests on newer CPUs that fake any of these
> models.  Some folks will also surely disagree with the kernel policy
> implemented here.
> 
> Is there no way to implement this other than a hard-coded kernel policy?

Besides the hardcoded CPU exclusion list, the options are:

1. Never use zmm registers.

2. Ignore the issue and use zmm registers even on these CPU models.  Systemwide
   performance may suffer due to downclocking.

3. Do a runtime test to detect whether using zmm registers causes downclocking.
   This seems impractical.

4. Keep the proposed policy as the default behavior, but allow it to be
   overridden on the kernel command line.  This would be a bit more flexible;
   however, most people don't change defaults anyway.

When you write "Some folks will also surely disagree with the kernel policy
implemented here", are there any specific concerns that you anticipate?  Note
that Intel has acknowledged the zmm downclocking issues on Ice Lake and
suggested that using ymm registers instead would be reasonable:
https://lore.kernel.org/linux-crypto/e8ce1146-3952-6977-1d0e-a22758e58914@intel.com/

If there is really a controversy, my vote is that for now we just go with option
(1), i.e. drop this patch from the series.  We can reconsider the issue when a
CPU is released with better 512-bit support.

- Eric