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Date: Fri, 10 May 2024 08:59:09 -0700
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Subject: Re: [PATCH v15 21/23] KVM: MMU: Disable fast path for private memslots
From: Sean Christopherson <seanjc@google.com>
To: Michael Roth <michael.roth@amd.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>, kvm@vger.kernel.org, linux-coco@lists.linux.dev, 
	linux-mm@kvack.org, linux-crypto@vger.kernel.org, x86@kernel.org, 
	linux-kernel@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com, 
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	pankaj.gupta@amd.com, liam.merwick@oracle.com, papaluri@amd.com, 
	Isaku Yamahata <isaku.yamahata@intel.com>
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On Fri, May 10, 2024, Michael Roth wrote:
> On Fri, May 10, 2024 at 03:50:26PM +0200, Paolo Bonzini wrote:
> > On Fri, May 10, 2024 at 3:47=E2=80=AFPM Sean Christopherson <seanjc@goo=
gle.com> wrote:
> > >
> > > > +      * Since software-protected VMs don't have a notion of a shar=
ed vs.
> > > > +      * private that's separate from what KVM is tracking, the abo=
ve
> > > > +      * KVM_EXIT_MEMORY_FAULT condition wouldn't occur, so avoid t=
he
> > > > +      * special handling for that case for now.
> > >
> > > Very technically, it can occur if userspace _just_ modified the attri=
butes.  And
> > > as I've said multiple times, at least for now, I want to avoid specia=
l casing
> > > SW-protected VMs unless it is *absolutely* necessary, because their s=
ole purpose
> > > is to allow testing flows that are impossible to excercise without SN=
P/TDX hardware.
> >=20
> > Yep, it is not like they have to be optimized.
>=20
> Ok, I thought there were maybe some future plans to use sw-protected VMs
> to get some added protections from userspace. But even then there'd
> probably still be extra considerations for how to handle access tracking
> so white-listing them probably isn't right anyway.
>=20
> I was also partly tempted to take this route because it would cover this
> TDX patch as well:
>=20
>   https://lore.kernel.org/lkml/91c797997b57056224571e22362321a23947172f.1=
705965635.git.isaku.yamahata@intel.com/

Hmm, I'm pretty sure that patch is trying to fix the exact same issue you a=
re
fixing, just in a less precise way.  S-EPT entries only support RWX=3D0 and=
 RWX=3D111b,
i.e. it should be impossible to have a write-fault to a present S-EPT entry=
.

And if TDX is running afoul of this code:

	if (!fault->present)
		return !kvm_ad_enabled();

then KVM should do the sane thing and require A/D support be enabled for TD=
X.

And if it's something else entirely, that changelog has some explaining to =
do.

> and avoid any weirdness about checking kvm_mem_is_private() without
> checking mmu_invalidate_seq, but I think those cases all end up
> resolving themselves eventually and added some comments around that.

Yep, checking state that is protected by mmu_invalidate_seq outside of mmu_=
lock
is definitely allowed, e.g. the entire fast page fault path operates outsid=
e of
mmu_lock and thus outside of mmu_invalidate_seq's purview.

It's a-ok because the SPTE are done with an atomic CMPXCHG, and so KVM only=
 needs
to ensure its page tables aren't outright _freed_.  If the zap triggered by=
 the
attributes change "wins", then the fast #PF path will fail the CMPXCHG and =
be an
expensive NOP.  If the fast #PF wins, the zap will pave over the fast #PF f=
ix,
and the IPI+flush that is needed for all zaps, to ensure vCPUs don't have s=
tale
references, does the rest.

And if there's an attributes race that causes the fast #PF to bail early, t=
he vCPU
will see the correct state on the next page fault.