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Thu, 6 Jun 2024 16:49:27 +0000 Received: from DS0PR10MB7224.namprd10.prod.outlook.com ([fe80::c57:383f:cfb2:47f8]) by DS0PR10MB7224.namprd10.prod.outlook.com ([fe80::c57:383f:cfb2:47f8%3]) with mapi id 15.20.7633.033; Thu, 6 Jun 2024 16:49:27 +0000 Message-ID: <23961b5b-a52a-483c-876e-e5e39d9e6c01@oracle.com> Date: Thu, 6 Jun 2024 09:49:19 -0700 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 04/19] x86: Secure Launch Resource Table header file To: Jarkko Sakkinen , linux-kernel@vger.kernel.org, x86@kernel.org, linux-integrity@vger.kernel.org, linux-doc@vger.kernel.org, linux-crypto@vger.kernel.org, kexec@lists.infradead.org, linux-efi@vger.kernel.org, iommu@lists.linux-foundation.org Cc: dpsmith@apertussolutions.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, dave.hansen@linux.intel.com, ardb@kernel.org, mjg59@srcf.ucam.org, James.Bottomley@hansenpartnership.com, peterhuewe@gmx.de, jgg@ziepe.ca, luto@amacapital.net, nivedita@alum.mit.edu, herbert@gondor.apana.org.au, davem@davemloft.net, corbet@lwn.net, ebiederm@xmission.com, dwmw2@infradead.org, baolu.lu@linux.intel.com, kanth.ghatraju@oracle.com, andrew.cooper3@citrix.com, trenchboot-devel@googlegroups.com, ross.philipson@oracle.com References: <20240531010331.134441-1-ross.philipson@oracle.com> <20240531010331.134441-5-ross.philipson@oracle.com> <1eca8cb1-4b3b-402b-993b-53de7c810016@oracle.com> <249a9b27-c18d-4377-8b51-9bc610b53a8b@oracle.com> Content-Language: en-US From: ross.philipson@oracle.com In-Reply-To: Content-Type: text/plain; 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In fact we are >> actively working on DRTM support through the TrenchBoot project on >> several platforms/architectures. Just a quick rundown here: >> >> Intel: Plenty of Intel platforms are vPro with TXT. It is really just >> the lower end systems that don't have it available (like Core i3). And >> my guess was wrong about x86s. You can find the spec on the page in the >> following link. There is an entire subsection on SMX support on x86s and >> the changes to the various GETSEC instruction leaves that were made to >> make it work there (see 3.15). >> >> https://urldefense.com/v3/__https://www.intel.com/content/www/us/en/developer/articles/technical/envisioning-future-simplified-architecture.html__;!!ACWV5N9M2RV99hQ!Lt-srkRLHstA9PPCB-NWogvHP-9mfh2bHjkml-lARY79BhYlWJjhrHb6RyCN_WdGstcABq1FdqPUKn5dCdw$ > > Happend to bump into same PDF specification and exactly the seeked > information is "3.15 SMX Changes". So just write this down to some > patch that starts adding SMX things. > > Link: https://urldefense.com/v3/__https://cdrdv2.intel.com/v1/dl/getContent/776648__;!!ACWV5N9M2RV99hQ!Lt-srkRLHstA9PPCB-NWogvHP-9mfh2bHjkml-lARY79BhYlWJjhrHb6RyCN_WdGstcABq1FdqPUuZy8Sfk$ > > So link and document, and other stuff above is not relevant from > upstream context, only potential maintenance burden :-) I am not 100% sure what you mean exactly here... > > For any architectures dig a similar fact: > > 1. Is not dead. > 2. Will be there also in future. > > Make any architecture existentially relevant for and not too much > coloring in the text that is easy to check. > > It is nearing 5k lines so you should be really good with measured > facts too (not just launch) :-) ... but overall I get your meaning. We will spend time on this sort of documentation for the v10 release. Thanks for the feedback, Ross > > BR, Jarkko >