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From: JiaJie Ho <jiajie.ho@starfivetech.com>
To: Vinod Koul <vkoul@kernel.org>
CC: Herbert Xu <herbert@gondor.apana.org.au>, "David S . Miller"
	<davem@davemloft.net>, Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-crypto@vger.kernel.org" <linux-crypto@vger.kernel.org>,
	"dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>
Subject: RE: [PATCH v5 1/3] dmaengine: dw-axi-dmac: Support hardware quirks
Thread-Topic: [PATCH v5 1/3] dmaengine: dw-axi-dmac: Support hardware quirks
Thread-Index: AQHasj8OTzZ9CEf8H0CgWgm1ave3tbHC60wAgAD2s5A=
Date: Wed, 12 Jun 2024 10:13:30 +0000
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> On 30-05-24, 11:11, Jia Jie Ho wrote:
>=20
> > +
> > +struct dw_axi_peripheral_config {
> > +#define DWAXIDMAC_STARFIVE_SM_ALGO	BIT(0)
>=20
> what does this quirk mean?
>=20
> > +	u32 quirks;
>=20
> Can you explain why you need this to be exposed. I would prefer we use
> existing interfaces and not define a new one...
>=20

Hi Vinod,
Thanks for reviewing this.
This is a dedicated dma controller for the crypto engine.
I am adding this quirk to:
1. Select the src and dest AXI master for transfers between mem and dev.=20
    Driver currently only uses AXI0 for both.
2. Workaround a hardware limitation on the crypto engine to
     transfer data > 256B by incrementing the peripheral FIFO offset.

What is the recommended way to handle such cases besides using=20
peripheral_config in dma_slave_config?

Best regards,
Jia Jie