2021-07-26 07:17:34

by Sam Shih

[permalink] [raw]
Subject: [PATCH 00/12] Add basic SoC support for mediatek mt7986

This patch adds basic SoC support for Mediatek's new 4-core SoC,
MT7986, which is mainly for wifi-router application.

Sam Shih (12):
dt-bindings: clock: mediatek: document clk bindings for mediatek
mt7986 SoC
clk: mediatek: add mt7986 clock IDs
clk: mediatek: add mt7986 clock support
pinctrl: mediatek: moore: use pin number in mtk_pin_desc instead of
array index
dt-bindings: pinctrl: update bindings for MT7986 SoC
pinctrl: mediatek: add support for MT7986 SoC
dt-bindings: arm64: dts: mediatek: Add mt7986 series
dt-bindings: rng: mediatek: add mt7986 to mtk rng binding
dt-bindings: serial: Add compatible for Mediatek MT7986
dt-bindings: watchdog: Add compatible for Mediatek MT7986
arm64: dts: mediatek: add mt7986a support
arm64: dts: mediatek: add mt7986b support

.../devicetree/bindings/arm/mediatek.yaml | 8 +
.../arm/mediatek/mediatek,apmixedsys.txt | 1 +
.../bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
.../arm/mediatek/mediatek,infracfg.txt | 2 +
.../arm/mediatek/mediatek,sgmiisys.txt | 2 +
.../arm/mediatek/mediatek,topckgen.txt | 1 +
.../bindings/pinctrl/pinctrl-mt7622.txt | 284 +++
.../devicetree/bindings/rng/mtk-rng.yaml | 1 +
.../devicetree/bindings/serial/mtk-uart.txt | 1 +
.../devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
arch/arm64/boot/dts/mediatek/Makefile | 2 +
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 49 +
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 235 +++
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 21 +
arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 235 +++
drivers/clk/mediatek/Kconfig | 17 +
drivers/clk/mediatek/Makefile | 2 +
drivers/clk/mediatek/clk-mt7986-eth.c | 132 ++
drivers/clk/mediatek/clk-mt7986.c | 610 ++++++
drivers/pinctrl/mediatek/Kconfig | 7 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-moore.c | 61 +
drivers/pinctrl/mediatek/pinctrl-mt7986.c | 1640 +++++++++++++++++
include/dt-bindings/clock/mt7986-clk.h | 244 +++
24 files changed, 3558 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a.dtsi
create mode 100644 arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt7986b.dtsi
create mode 100644 drivers/clk/mediatek/clk-mt7986-eth.c
create mode 100644 drivers/clk/mediatek/clk-mt7986.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7986.c
create mode 100644 include/dt-bindings/clock/mt7986-clk.h

--
2.29.2


2021-07-26 07:17:40

by Sam Shih

[permalink] [raw]
Subject: [PATCH 01/12] dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC

This patch adds the binding documentation for topckgen, apmixedsys,
infracfg, infracfg_ao, and ethernet subsystem clocks.

Signed-off-by: Sam Shih <[email protected]>
---
.../devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 +
.../devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
.../devicetree/bindings/arm/mediatek/mediatek,infracfg.txt | 2 ++
.../devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt | 2 ++
.../devicetree/bindings/arm/mediatek/mediatek,topckgen.txt | 1 +
5 files changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
index ea827e8763de..3fa755866528 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -14,6 +14,7 @@ Required Properties:
- "mediatek,mt7622-apmixedsys"
- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
- "mediatek,mt7629-apmixedsys"
+ - "mediatek,mt7986-apmixedsys"
- "mediatek,mt8135-apmixedsys"
- "mediatek,mt8167-apmixedsys", "syscon"
- "mediatek,mt8173-apmixedsys"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
index 6b7e8067e7aa..0502db73686b 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
@@ -10,6 +10,7 @@ Required Properties:
- "mediatek,mt7622-ethsys", "syscon"
- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7629-ethsys", "syscon"
+ - "mediatek,mt7986-ethsys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
index eb3523c7a7be..5f68c30162bf 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
@@ -15,6 +15,8 @@ Required Properties:
- "mediatek,mt7622-infracfg", "syscon"
- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
- "mediatek,mt7629-infracfg", "syscon"
+ - "mediatek,mt7986-infracfg", "syscon"
+ - "mediatek,mt7986-infracfg_ao", "syscon"
- "mediatek,mt8135-infracfg", "syscon"
- "mediatek,mt8167-infracfg", "syscon"
- "mediatek,mt8173-infracfg", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
index 30cb645c0e54..0e1184392941 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
@@ -8,6 +8,8 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt7622-sgmiisys", "syscon"
- "mediatek,mt7629-sgmiisys", "syscon"
+ - "mediatek,mt7986-sgmiisys", "mediatek,mt7986-sgmiisys_0", "syscon"
+ - "mediatek,mt7986-sgmiisys", "mediatek,mt7986-sgmiisys_1", "syscon"
- #clock-cells: Must be 1

The SGMIISYS controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
index 5ce7578cf274..b82422bb717f 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
@@ -14,6 +14,7 @@ Required Properties:
- "mediatek,mt7622-topckgen"
- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
- "mediatek,mt7629-topckgen"
+ - "mediatek,mt7986-topckgen", "syscon"
- "mediatek,mt8135-topckgen"
- "mediatek,mt8167-topckgen", "syscon"
- "mediatek,mt8173-topckgen"
--
2.29.2

2021-07-26 07:17:41

by Sam Shih

[permalink] [raw]
Subject: [PATCH 02/12] clk: mediatek: add mt7986 clock IDs

Add MT7986 clock dt-bindings, include topckgen, apmixedsys,
infracfg, infracfg_ao, and ethernet subsystem clocks.

Signed-off-by: Sam Shih <[email protected]>
---
include/dt-bindings/clock/mt7986-clk.h | 244 +++++++++++++++++++++++++
1 file changed, 244 insertions(+)
create mode 100644 include/dt-bindings/clock/mt7986-clk.h

diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
new file mode 100644
index 000000000000..dd11d0a717bc
--- /dev/null
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -0,0 +1,244 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Sam Shih <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7986_H
+#define _DT_BINDINGS_CLK_MT7986_H
+
+/* INFRACFG */
+
+#define CK_INFRA_CK_F26M 0
+#define CK_INFRA_UART 1
+#define CK_INFRA_ISPI0 2
+#define CK_INFRA_I2C 3
+#define CK_INFRA_ISPI1 4
+#define CK_INFRA_PWM 5
+#define CK_INFRA_66M_MCK 6
+#define CK_INFRA_CK_F32K 7
+#define CK_INFRA_PCIE_CK 8
+#define CK_INFRA_PWM_BCK 9
+#define CK_INFRA_PWM_CK1 10
+#define CK_INFRA_PWM_CK2 11
+#define CK_INFRA_133M_HCK 12
+#define CK_INFRA_EIP_CK 13
+#define CK_INFRA_66M_PHCK 14
+#define CK_INFRA_FAUD_L_CK 15
+#define CK_INFRA_FAUD_AUD_CK 16
+#define CK_INFRA_FAUD_EG2_CK 17
+#define CK_INFRA_I2CS_CK 18
+#define CK_INFRA_MUX_UART0 19
+#define CK_INFRA_MUX_UART1 20
+#define CK_INFRA_MUX_UART2 21
+#define CK_INFRA_NFI_CK 22
+#define CK_INFRA_SPINFI_CK 23
+#define CK_INFRA_MUX_SPI0 24
+#define CK_INFRA_MUX_SPI1 25
+#define CK_INFRA_RTC_32K 26
+#define CK_INFRA_FMSDC_CK 27
+#define CK_INFRA_FMSDC_HCK_CK 28
+#define CK_INFRA_PERI_133M 29
+#define CK_INFRA_133M_PHCK 30
+#define CK_INFRA_USB_SYS_CK 31
+#define CK_INFRA_USB_CK 32
+#define CK_INFRA_USB_XHCI_CK 33
+#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34
+#define CK_INFRA_F26M_CK0 35
+#define CK_INFRA_HD_133M 36
+#define CLK_INFRA_NR_CLK 37
+
+/* TOPCKGEN */
+
+#define CK_TOP_CB_CKSQ_40M 0
+#define CK_TOP_CB_M_416M 1
+#define CK_TOP_CB_M_D2 2
+#define CK_TOP_CB_M_D4 3
+#define CK_TOP_CB_M_D8 4
+#define CK_TOP_M_D8_D2 5
+#define CK_TOP_M_D3_D2 6
+#define CK_TOP_CB_MM_D2 7
+#define CK_TOP_CB_MM_D4 8
+#define CK_TOP_CB_MM_D8 9
+#define CK_TOP_MM_D8_D2 10
+#define CK_TOP_MM_D3_D8 11
+#define CK_TOP_CB_U2_PHYD_CK 12
+#define CK_TOP_CB_APLL2_196M 13
+#define CK_TOP_APLL2_D4 14
+#define CK_TOP_CB_NET1_D4 15
+#define CK_TOP_CB_NET1_D5 16
+#define CK_TOP_NET1_D5_D2 17
+#define CK_TOP_NET1_D5_D4 18
+#define CK_TOP_NET1_D8_D2 19
+#define CK_TOP_NET1_D8_D4 20
+#define CK_TOP_CB_NET2_800M 21
+#define CK_TOP_CB_NET2_D4 22
+#define CK_TOP_NET2_D4_D2 23
+#define CK_TOP_NET2_D3_D2 24
+#define CK_TOP_CB_WEDMCU_760M 25
+#define CK_TOP_WEDMCU_D5_D2 26
+#define CK_TOP_CB_SGM_325M 27
+#define CK_TOP_CB_CKSQ_40M_D2 28
+#define CK_TOP_CB_RTC_32K 29
+#define CK_TOP_CB_RTC_32P7K 30
+#define CK_TOP_NFI1X 31
+#define CK_TOP_USB_EQ_RX250M 32
+#define CK_TOP_USB_TX250M 33
+#define CK_TOP_USB_LN0_CK 34
+#define CK_TOP_USB_CDR_CK 35
+#define CK_TOP_SPINFI_BCK 36
+#define CK_TOP_I2C_BCK 37
+#define CK_TOP_PEXTP_TL 38
+#define CK_TOP_EMMC_250M 39
+#define CK_TOP_EMMC_416M 40
+#define CK_TOP_F_26M_ADC_CK 41
+#define CK_TOP_SYSAXI 42
+#define CK_TOP_NETSYS_WED_MCU 43
+#define CK_TOP_NETSYS_2X 44
+#define CK_TOP_SGM_325M 45
+#define CK_TOP_A1SYS 46
+#define CK_TOP_EIP_B 47
+#define CK_TOP_F26M 48
+#define CK_TOP_AUD_L 49
+#define CK_TOP_A_TUNER 50
+#define CK_TOP_U2U3_REF 51
+#define CK_TOP_U2U3_SYS 52
+#define CK_TOP_U2U3_XHCI 53
+#define CK_TOP_AP2CNN_HOST 54
+#define CK_TOP_NFI1X_SEL 55
+#define CK_TOP_SPINFI_SEL 56
+#define CK_TOP_SPI_SEL 57
+#define CK_TOP_SPIM_MST_SEL 58
+#define CK_TOP_UART_SEL 59
+#define CK_TOP_PWM_SEL 60
+#define CK_TOP_I2C_SEL 61
+#define CK_TOP_PEXTP_TL_SEL 62
+#define CK_TOP_EMMC_250M_SEL 63
+#define CK_TOP_EMMC_416M_SEL 64
+#define CK_TOP_F_26M_ADC_SEL 65
+#define CK_TOP_DRAMC_SEL 66
+#define CK_TOP_DRAMC_MD32_SEL 67
+#define CK_TOP_SYSAXI_SEL 68
+#define CK_TOP_SYSAPB_SEL 69
+#define CK_TOP_ARM_DB_MAIN_SEL 70
+#define CK_TOP_ARM_DB_JTSEL 71
+#define CK_TOP_NETSYS_SEL 72
+#define CK_TOP_NETSYS_500M_SEL 73
+#define CK_TOP_NETSYS_MCU_SEL 74
+#define CK_TOP_NETSYS_2X_SEL 75
+#define CK_TOP_SGM_325M_SEL 76
+#define CK_TOP_SGM_REG_SEL 77
+#define CK_TOP_A1SYS_SEL 78
+#define CK_TOP_CONN_MCUSYS_SEL 79
+#define CK_TOP_EIP_B_SEL 80
+#define CK_TOP_PCIE_PHY_SEL 81
+#define CK_TOP_USB3_PHY_SEL 82
+#define CK_TOP_F26M_SEL 83
+#define CK_TOP_AUD_L_SEL 84
+#define CK_TOP_A_TUNER_SEL 85
+#define CK_TOP_U2U3_SEL 86
+#define CK_TOP_U2U3_SYS_SEL 87
+#define CK_TOP_U2U3_XHCI_SEL 88
+#define CK_TOP_DA_U2_REFSEL 89
+#define CK_TOP_DA_U2_CK_1P_SEL 90
+#define CK_TOP_AP2CNN_HOST_SEL 91
+#define CLK_TOP_NR_CLK 92
+
+/* INFRACFG_AO */
+
+#define CK_INFRA_UART0_SEL 0
+#define CK_INFRA_UART1_SEL 1
+#define CK_INFRA_UART2_SEL 2
+#define CK_INFRA_SPI0_SEL 3
+#define CK_INFRA_SPI1_SEL 4
+#define CK_INFRA_PWM1_SEL 5
+#define CK_INFRA_PWM2_SEL 6
+#define CK_INFRA_PWM_BSEL 7
+#define CK_INFRA_PCIE_SEL 8
+#define CK_INFRA_GPT_STA 9
+#define CK_INFRA_PWM_HCK 10
+#define CK_INFRA_PWM_STA 11
+#define CK_INFRA_PWM1_CK 12
+#define CK_INFRA_PWM2_CK 13
+#define CK_INFRA_CQ_DMA_CK 14
+#define CK_INFRA_EIP97_CK 15
+#define CK_INFRA_AUD_BUS_CK 16
+#define CK_INFRA_AUD_26M_CK 17
+#define CK_INFRA_AUD_L_CK 18
+#define CK_INFRA_AUD_AUD_CK 19
+#define CK_INFRA_AUD_EG2_CK 20
+#define CK_INFRA_DRAMC_26M_CK 21
+#define CK_INFRA_DBG_CK 22
+#define CK_INFRA_AP_DMA_CK 23
+#define CK_INFRA_SEJ_CK 24
+#define CK_INFRA_SEJ_13M_CK 25
+#define CK_INFRA_THERM_CK 26
+#define CK_INFRA_I2CO_CK 27
+#define CK_INFRA_UART0_CK 28
+#define CK_INFRA_UART1_CK 29
+#define CK_INFRA_UART2_CK 30
+#define CK_INFRA_NFI1_CK 31
+#define CK_INFRA_SPINFI1_CK 32
+#define CK_INFRA_NFI_HCK_CK 33
+#define CK_INFRA_SPI0_CK 34
+#define CK_INFRA_SPI1_CK 35
+#define CK_INFRA_SPI0_HCK_CK 36
+#define CK_INFRA_SPI1_HCK_CK 37
+#define CK_INFRA_FRTC_CK 38
+#define CK_INFRA_MSDC_CK 39
+#define CK_INFRA_MSDC_HCK_CK 40
+#define CK_INFRA_MSDC_133M_CK 41
+#define CK_INFRA_MSDC_66M_CK 42
+#define CK_INFRA_ADC_26M_CK 43
+#define CK_INFRA_ADC_FRC_CK 44
+#define CK_INFRA_FBIST2FPC_CK 45
+#define CK_INFRA_IUSB_133_CK 46
+#define CK_INFRA_IUSB_66M_CK 47
+#define CK_INFRA_IUSB_SYS_CK 48
+#define CK_INFRA_IUSB_CK 49
+#define CK_INFRA_IPCIE_CK 50
+#define CK_INFRA_IPCIE_PIPE_CK 51
+#define CK_INFRA_IPCIER_CK 52
+#define CK_INFRA_IPCIEB_CK 53
+#define CK_INFRA_TRNG_CK 54
+#define CLK_INFRA_AO_NR_CLK 55
+
+/* APMIXEDSYS */
+
+#define CK_APMIXED_ARMPLL 0
+#define CK_APMIXED_NET2PLL 1
+#define CK_APMIXED_MMPLL 2
+#define CK_APMIXED_SGMPLL 3
+#define CK_APMIXED_WEDMCUPLL 4
+#define CK_APMIXED_NET1PLL 5
+#define CK_APMIXED_MPLL 6
+#define CK_APMIXED_APLL2 7
+#define CLK_APMIXED_NR_CLK 8
+
+/* SGMIISYS_0 */
+
+#define CK_SGM0_TX_EN 0
+#define CK_SGM0_RX_EN 1
+#define CK_SGM0_CK0_EN 2
+#define CK_SGM0_CDR_CK0_EN 3
+#define CLK_SGMII0_NR_CLK 4
+
+/* SGMIISYS_1 */
+
+#define CK_SGM1_TX_EN 0
+#define CK_SGM1_RX_EN 1
+#define CK_SGM1_CK1_EN 2
+#define CK_SGM1_CDR_CK1_EN 3
+#define CLK_SGMII1_NR_CLK 4
+
+/* ETHSYS */
+
+#define CK_ETH_FE_EN 0
+#define CK_ETH_GP2_EN 1
+#define CK_ETH_GP1_EN 2
+#define CK_ETH_WOCPU1_EN 3
+#define CK_ETH_WOCPU0_EN 4
+#define CLK_ETH_NR_CLK 5
+
+#endif /* _DT_BINDINGS_CLK_MT7986_H */
+
--
2.29.2

2021-07-26 07:17:54

by Sam Shih

[permalink] [raw]
Subject: [PATCH 03/12] clk: mediatek: add mt7986 clock support

Add MT7986 clock support, include topckgen, apmixedsys,
infracfg, infracfg_ao, and ethernet subsystem clocks.

Signed-off-by: Sam Shih <[email protected]>
---
drivers/clk/mediatek/Kconfig | 17 +
drivers/clk/mediatek/Makefile | 2 +
drivers/clk/mediatek/clk-mt7986-eth.c | 132 ++++++
drivers/clk/mediatek/clk-mt7986.c | 610 ++++++++++++++++++++++++++
4 files changed, 761 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt7986-eth.c
create mode 100644 drivers/clk/mediatek/clk-mt7986.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 886e2d9fced5..28d8a07d5139 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -344,6 +344,23 @@ config COMMON_CLK_MT7629_HIFSYS
This driver supports MediaTek MT7629 HIFSYS clocks providing
to PCI-E and USB.

+config COMMON_CLK_MT7986
+ bool "Clock driver for MediaTek MT7986"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ default ARCH_MEDIATEK
+ help
+ This driver supports MediaTek MT7986 basic clocks and clocks
+ required for various periperals found on MediaTek.
+
+config COMMON_CLK_MT7986_ETHSYS
+ bool "Clock driver for MediaTek MT7986 ETHSYS"
+ depends on COMMON_CLK_MT7986
+ default COMMON_CLK_MT7986
+ help
+ This driver add support for clocks for Ethernet and SGMII
+ required on MediaTek MT7986 SoC.
+
config COMMON_CLK_MT8135
bool "Clock driver for MediaTek MT8135"
depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 3b0c2be73824..c513548a2518 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -46,6 +46,8 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o
obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
+obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986.o
+obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
diff --git a/drivers/clk/mediatek/clk-mt7986-eth.c b/drivers/clk/mediatek/clk-mt7986-eth.c
new file mode 100644
index 000000000000..b8f16fb7eea5
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7986-eth.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Wenzhen Yu <[email protected]>
+ * Sam Shih <[email protected]>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt7986-clk.h>
+
+static const struct mtk_gate_regs sgmii0_cg_regs = {
+ .set_ofs = 0xe4,
+ .clr_ofs = 0xe4,
+ .sta_ofs = 0xe4,
+};
+
+#define GATE_SGMII0(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .name = _name, .parent_name = _parent, \
+ .regs = &sgmii0_cg_regs, .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate sgmii0_clks[] __initconst = {
+ GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
+ GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
+ GATE_SGMII0(CK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
+ GATE_SGMII0(CK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),
+};
+
+static const struct mtk_gate_regs sgmii1_cg_regs = {
+ .set_ofs = 0xe4,
+ .clr_ofs = 0xe4,
+ .sta_ofs = 0xe4,
+};
+
+#define GATE_SGMII1(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .name = _name, .parent_name = _parent, \
+ .regs = &sgmii1_cg_regs, .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate sgmii1_clks[] __initconst = {
+ GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
+ GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
+ GATE_SGMII1(CK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
+ GATE_SGMII1(CK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),
+};
+
+static const struct mtk_gate_regs eth_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+#define GATE_ETH(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .name = _name, .parent_name = _parent, \
+ .regs = &eth_cg_regs, .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
+static const struct mtk_gate eth_clks[] __initconst = {
+ GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
+ GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
+ GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),
+ GATE_ETH(CK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_wed_mcu", 14),
+ GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),
+};
+
+static void __init mtk_sgmiisys_0_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_SGMII0_NR_CLK);
+
+ mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0",
+ mtk_sgmiisys_0_init);
+
+static void __init mtk_sgmiisys_1_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_SGMII1_NR_CLK);
+
+ mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1",
+ mtk_sgmiisys_1_init);
+
+static void __init mtk_ethsys_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
+
+ mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys_ck", mtk_ethsys_init);
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
new file mode 100644
index 000000000000..c8f2a4d7ac1c
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -0,0 +1,610 @@
+// SPDX-License-Identifier: GPL-1.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Wenzhen Yu <[email protected]>
+ * Sam Shih <[email protected]>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "clk-mtk.h"
+#include "clk-gate.h"
+#include "clk-mux.h"
+
+#include <dt-bindings/clock/mt7986-clk.h>
+#include <linux/clk.h>
+
+#define MT7986_PLL_FMAX (2500UL * MHZ)
+#define CON0_MT7986_RST_BAR BIT(27)
+
+#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
+ _div_table, _parent_name) \
+ { \
+ .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, .flags = _flags, \
+ .rst_bar_mask = CON0_MT7986_RST_BAR, .fmax = MT7986_PLL_FMAX, \
+ .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, .div_table = _div_table, \
+ .parent_name = _parent_name, \
+ }
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \
+ PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
+ "clkxtal")
+
+static DEFINE_SPINLOCK(mt7986_clk_lock);
+
+static const struct mtk_fixed_factor infra_divs[] __initconst = {
+ FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", "csw_f26m_sel", 1, 1),
+ FACTOR(CK_INFRA_UART, "infra_uart", "uart_sel", 1, 1),
+ FACTOR(CK_INFRA_ISPI0, "infra_ispi0", "spi_sel", 1, 1),
+ FACTOR(CK_INFRA_I2C, "infra_i2c", "i2c_sel", 1, 1),
+ FACTOR(CK_INFRA_ISPI1, "infra_ispi1", "spim_mst_sel", 1, 1),
+ FACTOR(CK_INFRA_ISPI1, "infra_ispi1", "spinfi_sel", 1, 1),
+ FACTOR(CK_INFRA_PWM, "infra_pwm", "pwm_sel", 1, 1),
+ FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2),
+ FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", "cb_rtc_32p7k", 1, 1),
+ FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", "pextp_tl_ck_sel", 1, 1),
+ FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", "infra_pwm_bsel", 1, 1),
+ FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", "infra_pwm1_sel", 1, 1),
+ FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", "infra_pwm2_sel", 1, 1),
+ FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", "sysaxi", 1, 1),
+ FACTOR(CK_INFRA_EIP_CK, "infra_eip", "eip_b", 1, 1),
+ FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", "infra_133m_hck", 1, 1),
+ FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", "aud_l", 1, 1),
+ FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", "a1sys", 1, 1),
+ FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", "a_tuner", 1, 1),
+ FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", "i2c_bck", 1, 1),
+ FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", "infra_uart0_sel", 1, 1),
+ FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", "infra_uart1_sel", 1, 1),
+ FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", "infra_uart2_sel", 1, 1),
+ FACTOR(CK_INFRA_NFI_CK, "infra_nfi", "nfi1x", 1, 1),
+ FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", "spinfi_bck", 1, 1),
+ FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", "infra_spi0_sel", 1, 1),
+ FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", "infra_spi1_sel", 1, 1),
+ FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", "cb_rtc_32k", 1, 1),
+ FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", "emmc_416m", 1, 1),
+ FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", "emmc_250m", 1, 1),
+ FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", "sysaxi", 1, 1),
+ FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", "sysaxi", 1, 1),
+ FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", "u2u3_sys", 1, 1),
+ FACTOR(CK_INFRA_USB_CK, "infra_usb", "u2u3_ref", 1, 1),
+ FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", "u2u3_xhci", 1, 1),
+ FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux", "pextp_tl", 1,
+ 1),
+ FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", "csw_f26m", 1, 1),
+ FACTOR(CK_INFRA_HD_133M, "infra_hd_133m", "sysaxi", 1, 1),
+};
+
+static const struct mtk_fixed_factor top_divs[] __initconst = {
+ FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1),
+ FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
+ FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
+ FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
+ FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
+ FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
+ FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
+ FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2),
+ FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4),
+ FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8),
+ FACTOR(CK_TOP_MM_D8_D2, "mm_d8_d2", "mmpll", 1, 16),
+ FACTOR(CK_TOP_MM_D3_D8, "mm_d3_d8", "mmpll", 1, 8),
+ FACTOR(CK_TOP_CB_U2_PHYD_CK, "cb_u2_phyd", "mmpll", 1, 30),
+ FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1),
+ FACTOR(CK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
+ FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4),
+ FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5),
+ FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10),
+ FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20),
+ FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16),
+ FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32),
+ FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1),
+ FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4),
+ FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8),
+ FACTOR(CK_TOP_NET2_D3_D2, "net2_d3_d2", "net2pll", 1, 2),
+ FACTOR(CK_TOP_CB_WEDMCU_760M, "cb_wedmcu_760m", "wedmcupll", 1, 1),
+ FACTOR(CK_TOP_WEDMCU_D5_D2, "wedmcu_d5_d2", "wedmcupll", 1, 10),
+ FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1),
+ FACTOR(CK_TOP_CB_CKSQ_40M_D2, "cb_cksq_40m_d2", "cb_cksq_40m", 1, 2),
+ FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250),
+ FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220),
+ FACTOR(CK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1),
+ FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1),
+ FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1),
+ FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1),
+ FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1),
+ FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1),
+ FACTOR(CK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1),
+ FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1),
+ FACTOR(CK_TOP_EMMC_250M, "emmc_250m", "emmc_250m_sel", 1, 1),
+ FACTOR(CK_TOP_EMMC_416M, "emmc_416m", "emmc_416m_sel", 1, 1),
+ FACTOR(CK_TOP_F_26M_ADC_CK, "f_26m_adc", "f_26m_adc_sel", 1, 1),
+ FACTOR(CK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1),
+ FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1),
+ FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1),
+ FACTOR(CK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1),
+ FACTOR(CK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1),
+ FACTOR(CK_TOP_EIP_B, "eip_b", "eip_b_sel", 1, 1),
+ FACTOR(CK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1),
+ FACTOR(CK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1),
+ FACTOR(CK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1),
+ FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1),
+ FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1),
+ FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1),
+ FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1),
+};
+
+static const char *const nfi1x_parents[] __initconst = {
+ "cb_cksq_40m", "cb_mm_d8", "net1_d8_d2", "net2_d3_d2",
+ "cb_m_d4", "mm_d8_d2", "wedmcu_d5_d2", "cb_m_d8"
+};
+
+static const char *const spinfi_parents[] __initconst = {
+ "cb_cksq_40m_d2", "cb_cksq_40m", "net1_d5_d4", "cb_m_d4",
+ "mm_d8_d2", "wedmcu_d5_d2", "mm_d3_d8", "cb_m_d8"
+};
+
+static const char *const spi_parents[] __initconst = {
+ "cb_cksq_40m", "cb_m_d2", "cb_mm_d8", "net1_d8_d2",
+ "net2_d3_d2", "net1_d5_d4", "cb_m_d4", "wedmcu_d5_d2"
+};
+
+static const char *const uart_parents[] __initconst = { "cb_cksq_40m",
+ "cb_m_d8", "m_d8_d2" };
+
+static const char *const pwm_parents[] __initconst = {
+ "cb_cksq_40m", "net1_d8_d2", "net1_d5_d4", "cb_m_d4"
+};
+
+static const char *const i2c_parents[] __initconst = { "cb_cksq_40m",
+ "net1_d5_d4", "cb_m_d4",
+ "net1_d8_d4" };
+
+static const char *const pextp_tl_ck_parents[] __initconst = {
+ "cb_cksq_40m", "net1_d5_d4", "net2_d4_d2", "cb_rtc_32k"
+};
+
+static const char *const emmc_250m_parents[] __initconst = { "cb_cksq_40m",
+ "net1_d5_d2" };
+
+static const char *const emmc_416m_parents[] __initconst = { "cb_cksq_40m",
+ "cb_m_416m" };
+
+static const char *const f_26m_adc_parents[] __initconst = { "cb_cksq_40m",
+ "m_d8_d2" };
+
+static const char *const dramc_md32_parents[] __initconst = { "cb_cksq_40m",
+ "cb_m_d2" };
+
+static const char *const sysaxi_parents[] __initconst = { "cb_cksq_40m",
+ "net1_d8_d2",
+ "cb_net2_d4" };
+
+static const char *const sysapb_parents[] __initconst = { "cb_cksq_40m",
+ "m_d3_d2",
+ "net2_d4_d2" };
+
+static const char *const arm_db_main_parents[] __initconst = { "cb_cksq_40m",
+ "net2_d3_d2" };
+
+static const char *const arm_db_jtsel_parents[] __initconst = { "cb_jtck_50m",
+ "cb_cksq_40m" };
+
+static const char *const netsys_parents[] __initconst = { "cb_cksq_40m",
+ "cb_mm_d4" };
+
+static const char *const netsys_500m_parents[] __initconst = { "cb_cksq_40m",
+ "cb_net1_d5" };
+
+static const char *const netsys_mcu_parents[] __initconst = {
+ "cb_cksq_40m", "cb_wedmcu_760m", "cb_mm_d2", "cb_net1_d4", "cb_net1_d5"
+};
+
+static const char *const netsys_2x_parents[] __initconst = {
+ "cb_cksq_40m", "cb_net2_800m", "cb_wedmcu_760m", "cb_mm_d2"
+};
+
+static const char *const sgm_325m_parents[] __initconst = { "cb_cksq_40m",
+ "cb_sgm_325m" };
+
+static const char *const sgm_reg_parents[] __initconst = { "cb_cksq_40m",
+ "net1_d8_d4" };
+
+static const char *const a1sys_parents[] __initconst = { "cb_cksq_40m",
+ "apll2_d4" };
+
+static const char *const conn_mcusys_parents[] __initconst = { "cb_cksq_40m",
+ "cb_mm_d2" };
+
+static const char *const eip_b_parents[] __initconst = { "cb_cksq_40m",
+ "cb_net2_800m" };
+
+static const char *const aud_l_parents[] __initconst = { "cb_cksq_40m",
+ "cb_apll2_196m",
+ "m_d8_d2" };
+
+static const char *const a_tuner_parents[] __initconst = { "cb_cksq_40m",
+ "apll2_d4",
+ "m_d8_d2" };
+
+static const char *const u2u3_sys_parents[] __initconst = { "cb_cksq_40m",
+ "net1_d5_d4" };
+
+static const char *const da_u2_refsel_parents[] __initconst = { "cb_cksq_40m",
+ "cb_u2_phyd" };
+
+static const struct mtk_mux top_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX_GATE_CLR_SET_UPD(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
+ 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
+ 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
+ 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
+ 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
+ /* CLK_CFG_1 */
+ MUX_GATE_CLR_SET_UPD(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
+ 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
+ 0x014, 0x018, 8, 2, 15, 0x1C0, 5),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
+ 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
+ pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2,
+ 31, 0x1C0, 7),
+ /* CLK_CFG_2 */
+ MUX_GATE_CLR_SET_UPD(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
+ emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7,
+ 0x1C0, 8),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_EMMC_416M_SEL, "emmc_416m_sel",
+ emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15,
+ 0x1C0, 9),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
+ f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
+ 0x1C0, 10),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
+ 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
+ /* CLK_CFG_3 */
+ MUX_GATE_CLR_SET_UPD(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
+ dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
+ 0x1C0, 12),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
+ 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
+ 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
+ arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
+ 31, 0x1C0, 15),
+ /* CLK_CFG_4 */
+ MUX_GATE_CLR_SET_UPD(CK_TOP_ARM_DB_JTSEL, "arm_db_jtsel",
+ arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7,
+ 0x1C0, 16),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
+ 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
+ netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1,
+ 23, 0x1C0, 18),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
+ netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
+ 0x1C0, 19),
+ /* CLK_CFG_5 */
+ MUX_GATE_CLR_SET_UPD(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
+ netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
+ 0x1C0, 20),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_SGM_325M_SEL, "sgm_325m_sel",
+ sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
+ 0x1C0, 21),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents,
+ 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
+ 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
+ /* CLK_CFG_6 */
+ MUX_GATE_CLR_SET_UPD(CK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel",
+ conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7,
+ 0x1C0, 24),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents,
+ 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_PCIE_PHY_SEL, "pcie_phy_sel",
+ f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23,
+ 0x1C0, 26),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
+ f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
+ 0x1C0, 27),
+ /* CLK_CFG_7 */
+ MUX_GATE_CLR_SET_UPD(CK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents,
+ 0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
+ 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents,
+ 0x070, 0x074, 0x078, 16, 2, 23, 0x1C0, 30),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents,
+ 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0),
+ /* CLK_CFG_8 */
+ MUX_GATE_CLR_SET_UPD(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
+ u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7,
+ 0x1C4, 1),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
+ u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15,
+ 0x1C4, 2),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_DA_U2_REFSEL, "da_u2_refsel",
+ da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1,
+ 23, 0x1C4, 3),
+ MUX_GATE_CLR_SET_UPD(CK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel",
+ da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1,
+ 31, 0x1C4, 4),
+ /* CLK_CFG_9 */
+ MUX_GATE_CLR_SET_UPD(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
+ sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7,
+ 0x1C4, 5),
+};
+
+static const char *const infra_uart0_parents[] __initconst = { "infra_ck_f26m",
+ "infra_uart" };
+
+static const char *const infra_spi0_parents[] __initconst = { "infra_i2c",
+ "infra_ispi0" };
+
+static const char *const infra_spi1_parents[] __initconst = { "infra_i2c",
+ "infra_ispi1" };
+
+static const char *const infra_pwm_bsel_parents[] __initconst = {
+ "infra_ck_f32k", "infra_ck_f26m", "infra_66m_mck", "infra_pwm"
+};
+
+static const char *const infra_pcie_parents[] __initconst = {
+ "infra_ck_f32k", "infra_ck_f26m", "cb_cksq_40m", "infra_pcie"
+};
+
+static const struct mtk_mux infra_muxes[] = {
+ /* MODULE_CLK_SEL_0 */
+ MUX_GATE_CLR_SET_UPD(CK_INFRA_UART0_SEL, "infra_uart0_sel",
+ infra_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1,
+ -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CK_INFRA_UART1_SEL, "infra_uart1_sel",
+ infra_uart0_parents, 0x0018, 0x0010, 0x0014, 1, 1,
+ -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CK_INFRA_UART2_SEL, "infra_uart2_sel",
+ infra_uart0_parents, 0x0018, 0x0010, 0x0014, 2, 1,
+ -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CK_INFRA_SPI0_SEL, "infra_spi0_sel",
+ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,
+ -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CK_INFRA_SPI1_SEL, "infra_spi1_sel",
+ infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,
+ -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM1_SEL, "infra_pwm1_sel",
+ infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9,
+ 2, -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM2_SEL, "infra_pwm2_sel",
+ infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11,
+ 2, -1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CK_INFRA_PWM_BSEL, "infra_pwm_bsel",
+ infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
+ 2, -1, -1, -1),
+ /* MODULE_CLK_SEL_1 */
+ MUX_GATE_CLR_SET_UPD(CK_INFRA_PCIE_SEL, "infra_pcie_sel",
+ infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
+ -1, -1, -1),
+};
+
+static const struct mtk_gate_regs infra0_cg_regs = {
+ .set_ofs = 0x40,
+ .clr_ofs = 0x44,
+ .sta_ofs = 0x48,
+};
+
+static const struct mtk_gate_regs infra1_cg_regs = {
+ .set_ofs = 0x50,
+ .clr_ofs = 0x54,
+ .sta_ofs = 0x58,
+};
+
+static const struct mtk_gate_regs infra2_cg_regs = {
+ .set_ofs = 0x60,
+ .clr_ofs = 0x64,
+ .sta_ofs = 0x68,
+};
+
+#define GATE_INFRA0(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .name = _name, .parent_name = _parent, \
+ .regs = &infra0_cg_regs, .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_INFRA1(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .name = _name, .parent_name = _parent, \
+ .regs = &infra1_cg_regs, .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+#define GATE_INFRA2(_id, _name, _parent, _shift) \
+ { \
+ .id = _id, .name = _name, .parent_name = _parent, \
+ .regs = &infra2_cg_regs, .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate infra_clks[] __initconst = {
+ /* INFRA0 */
+ GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),
+ GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1),
+ GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bck", 2),
+ GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm_ck1", 3),
+ GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm_ck2", 4),
+ GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", "infra_133m_hck", 6),
+ GATE_INFRA0(CK_INFRA_EIP97_CK, "infra_eip97", "infra_eip", 7),
+ GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", "infra_66m_phck", 8),
+ GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", "infra_ck_f26m", 9),
+ GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", "infra_faud_l", 10),
+ GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", "infra_faud_aud", 11),
+ GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "infra_faud_eg2", 13),
+ GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "infra_ck_f26m",
+ 14),
+ GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15),
+ GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),
+ GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),
+ GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", "infra_ck_f26m", 25),
+ GATE_INFRA0(CK_INFRA_TRNG_CK, "infra_trng", "infra_hd_133m", 26),
+ /* INFRA1 */
+ GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", "infra_ck_f26m", 0),
+ GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", "infra_i2cs", 1),
+ GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", "infra_mux_uart0", 2),
+ GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", "infra_mux_uart1", 3),
+ GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", "infra_mux_uart2", 4),
+ GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", "infra_nfi", 8),
+ GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", "infra_spinfi", 9),
+ GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10),
+ GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", "infra_mux_spi0", 11),
+ GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", "infra_mux_spi1", 12),
+ GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck",
+ 13),
+ GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck",
+ 14),
+ GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", "infra_rtc_32k", 15),
+ GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", "infra_fmsdc", 16),
+ GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "infra_fmsdc_hck",
+ 17),
+ GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "infra_peri_133m",
+ 18),
+ GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_66m_phck",
+ 19),
+ GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", "csw_f26m", 20),
+ GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21),
+ GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "infra_nfi", 23),
+ /* INFRA2 */
+ GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", "infra_133m_phck",
+ 0),
+ GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_66m_phck",
+ 1),
+ GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "infra_usb_sys", 2),
+ GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", "infra_usb", 3),
+ GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", "infra_pcie_mux", 12),
+ GATE_INFRA2(CK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m",
+ 13),
+ GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", "infra_f26m_ck0", 14),
+ GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", "infra_133m_phck", 15),
+};
+
+static const struct mtk_pll_data plls[] = {
+ PLL(CK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32,
+ 0x0200, 4, 0, 0x0204, 0),
+ PLL(CK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
+ 0x0210, 4, 0, 0x0214, 0),
+ PLL(CK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
+ 0x0220, 4, 0, 0x0224, 0),
+ PLL(CK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x00000001, 0, 32,
+ 0x0230, 4, 0, 0x0234, 0),
+ PLL(CK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x00000001, 0,
+ 32, 0x0240, 4, 0, 0x0244, 0),
+ PLL(CK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x00000001, 0, 32,
+ 0x0250, 4, 0, 0x0254, 0),
+ PLL(CK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, 0x0260,
+ 4, 0, 0x0264, 0),
+ PLL(CK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
+ 0x0278, 4, 0, 0x027c, 0),
+};
+
+static void __init mtk_infracfg_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+
+ mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt7986-infracfg", mtk_infracfg_init);
+
+static void __init mtk_topckgen_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ void __iomem *base;
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return;
+ }
+
+ clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+
+ mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
+ mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
+ &mt7986_clk_lock, clk_data);
+
+ clk_prepare_enable(clk_data->clks[CK_TOP_SYSAXI_SEL]);
+ clk_prepare_enable(clk_data->clks[CK_TOP_SYSAPB_SEL]);
+ clk_prepare_enable(clk_data->clks[CK_TOP_DRAMC_SEL]);
+ clk_prepare_enable(clk_data->clks[CK_TOP_DRAMC_MD32_SEL]);
+ clk_prepare_enable(clk_data->clks[CK_TOP_F26M_SEL]);
+ clk_prepare_enable(clk_data->clks[CK_TOP_SGM_REG_SEL]);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt7986-topckgen", mtk_topckgen_init);
+
+static void __init mtk_infracfg_ao_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+ void __iomem *base;
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ pr_err("%s(): ioremap failed\n", __func__);
+ return;
+ }
+
+ clk_data = mtk_alloc_clk_data(CLK_INFRA_AO_NR_CLK);
+
+ mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
+ &mt7986_clk_lock, clk_data);
+ mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+CLK_OF_DECLARE(mtk_infracfg_ao, "mediatek,mt7986-infracfg_ao",
+ mtk_infracfg_ao_init);
+
+static void __init mtk_apmixedsys_init(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+
+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+
+ clk_prepare_enable(clk_data->clks[CK_APMIXED_ARMPLL]);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ pr_err("%s(): could not register clock provider: %d\n",
+ __func__, r);
+}
+CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt7986-apmixedsys",
+ mtk_apmixedsys_init);
--
2.29.2

2021-07-26 07:18:00

by Sam Shih

[permalink] [raw]
Subject: [PATCH 04/12] pinctrl: mediatek: moore: use pin number in mtk_pin_desc instead of array index

Certain SoC are missing the middle part gpios in consecutive pins,
it's better to use pin number in mtk_pin_desc instead of array index
for the extensibility

Signed-off-by: Sam Shih <[email protected]>
---
drivers/pinctrl/mediatek/pinctrl-moore.c | 61 ++++++++++++++++++++++++
1 file changed, 61 insertions(+)

diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c
index 3a4a23c40a71..16206254ec3d 100644
--- a/drivers/pinctrl/mediatek/pinctrl-moore.c
+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
@@ -35,6 +35,19 @@ static const struct pin_config_item mtk_conf_items[] = {
};
#endif

+static int mtk_pin_desc_lookup(struct mtk_pinctrl *hw, int pin)
+{
+ int idx;
+
+ for (idx = 0 ; idx < hw->soc->npins ; idx++)
+ if (hw->soc->pins[idx].number == pin)
+ break;
+ if (idx < hw->soc->npins)
+ return idx;
+
+ return -EINVAL;
+}
+
static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned int group)
{
@@ -74,6 +87,13 @@ static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
+ int err;
+
+ err = mtk_pin_desc_lookup(hw, pin);
+ if (err >= 0)
+ pin = err;
+ else
+ return err;

desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];

@@ -87,6 +107,13 @@ static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
{
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
const struct mtk_pin_desc *desc;
+ int err;
+
+ err = mtk_pin_desc_lookup(hw, pin);
+ if (err >= 0)
+ pin = err;
+ else
+ return err;

desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];

@@ -102,6 +129,12 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
int val, val2, err, reg, ret = 1;
const struct mtk_pin_desc *desc;

+ err = mtk_pin_desc_lookup(hw, pin);
+ if (err >= 0)
+ pin = err;
+ else
+ return err;
+
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];

switch (param) {
@@ -217,6 +250,12 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
u32 reg, param, arg;
int cfg, err = 0;

+ err = mtk_pin_desc_lookup(hw, pin);
+ if (err >= 0)
+ pin = err;
+ else
+ return err;
+
desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];

for (cfg = 0; cfg < num_configs; cfg++) {
@@ -434,6 +473,12 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
const struct mtk_pin_desc *desc;
int value, err;

+ err = mtk_pin_desc_lookup(hw, gpio);
+ if (err >= 0)
+ gpio = err;
+ else
+ return err;
+
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];

err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
@@ -447,6 +492,15 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
{
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
+ int err;
+
+ err = mtk_pin_desc_lookup(hw, gpio);
+ if (err >= 0) {
+ gpio = err;
+ } else {
+ dev_err(hw->dev, "Failed to set gpio %d\n", gpio);
+ return;
+ }

desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];

@@ -488,6 +542,13 @@ static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
const struct mtk_pin_desc *desc;
u32 debounce;
+ int err;
+
+ err = mtk_pin_desc_lookup(hw, offset);
+ if (err >= 0)
+ offset = err;
+ else
+ return err;

desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];

--
2.29.2

2021-07-26 07:18:14

by Sam Shih

[permalink] [raw]
Subject: [PATCH 07/12] dt-bindings: arm64: dts: mediatek: Add mt7986 series

MT7986 is Mediatek's new 4-core SoC, which is mainly for wifi-router
application. The difference between mt7986a and mt7986b is that some
pins do not exist on mt7986b.

Signed-off-by: Sam Shih <[email protected]>
---
Documentation/devicetree/bindings/arm/mediatek.yaml | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index 80a05f6fee85..a9a778269684 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -76,6 +76,14 @@ properties:
- enum:
- mediatek,mt7629-rfb
- const: mediatek,mt7629
+ - items:
+ - enum:
+ - mediatek,mt7986a-rfb
+ - const: mediatek,mt7986a
+ - items:
+ - enum:
+ - mediatek,mt7986b-rfb
+ - const: mediatek,mt7986b
- items:
- enum:
- mediatek,mt8127-moose
--
2.29.2

2021-07-26 07:18:15

by Sam Shih

[permalink] [raw]
Subject: [PATCH 06/12] pinctrl: mediatek: add support for MT7986 SoC

This commit includes pinctrl driver for Mediatek MT7986

The difference of pinctrl between mt7986a and mt7986b
is that pin-41 to pin-65 do not exist on mt7986b

Signed-off-by: Sam Shih <[email protected]>
---
drivers/pinctrl/mediatek/Kconfig | 7 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt7986.c | 1640 +++++++++++++++++++++
3 files changed, 1648 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7986.c

diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 7040a7a7bd5d..66db4ac5d169 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -119,6 +119,13 @@ config PINCTRL_MT7622
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_MOORE

+config PINCTRL_MT7986
+ bool "Mediatek MT7986 pin control"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ default ARM64 && ARCH_MEDIATEK
+ select PINCTRL_MTK_MOORE
+
config PINCTRL_MT8167
bool "Mediatek MT8167 pin control"
depends on OF
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index 1bb7f9c65bc2..1e3931d924e7 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
+obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
new file mode 100644
index 000000000000..1cccef2b5405
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
@@ -0,0 +1,1640 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * The MT7986 driver based on Linux generic pinctrl binding.
+ *
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Sam Shih <[email protected]>
+ */
+
+#include "pinctrl-moore.h"
+
+#define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
+
+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
+ _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, 0)
+
+/**
+ * enum - Locking variants of the iocfg bases
+ *
+ * MT7986 have multiple bases to program pin configuration listed as the below:
+ * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000,
+ * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000,
+ * _i_based could be used to indicate what base the pin should be mapped into.
+ *
+ * Each iocfg register base control different group of pads on the SoC
+ *
+ *
+ * chip carrier
+ *
+ * A B C D E F G H
+ * +------------------------+
+ * 8 | o o o o o o o o |
+ * 7 | o o o o o o o o |
+ * 6 | o o o o o o o o |
+ * 5 | o o o o o o o o |
+ * 4 | o o o o o o o o |
+ * 3 | o o o o o o o o |
+ * 2 | o o o o o o o o |
+ * 1 | o o o o o o o o |
+ * +------------------------+
+ *
+ * inside Chip carrier
+ *
+ * A B C D E F G H
+ * +------------------------+
+ * 8 | |
+ * 7 | TL TR |
+ * 6 | +---------+ |
+ * 5 | LT | | RT |
+ * 4 | | | |
+ * 3 | LB | | RB |
+ * 2 | +---------+ |
+ * 1 | |
+ * +------------------------+
+ *
+ */
+
+static const char *const mt7986_pinctrl_register_base_names[] = {
+ "gpio_base", "iocfg_rt_base", "iocfg_rb_base", "iocfg_lt_base",
+ "iocfg_lb_base", "iocfg_tr_base", "iocfg_tl_base",
+};
+
+enum {
+ GPIO_BASE,
+ IOCFG_RT_BASE,
+ IOCFG_RB_BASE,
+ IOCFG_LT_BASE,
+ IOCFG_LB_BASE,
+ IOCFG_TR_BASE,
+ IOCFG_TL_BASE,
+};
+
+static const struct mtk_pin_field_calc mt7986a_pin_mode_range[] = {
+ PIN_FIELD(0, 40, 0x300, 0x10, 0, 4),
+ PIN_FIELD(41, 65, 0x350, 0x10, 4, 4),
+ PIN_FIELD(66, 68, 0x380, 0x10, 8, 4),
+ PIN_FIELD(69, 100, 0x380, 0x10, 20, 4),
+};
+
+static const struct mtk_pin_field_calc mt7986a_pin_dir_range[] = {
+ PIN_FIELD(0, 40, 0x0, 0x10, 0, 1),
+ PIN_FIELD(41, 65, 0x10, 0x10, 9, 1),
+ PIN_FIELD(66, 68, 0x20, 0x10, 2, 1),
+ PIN_FIELD(69, 100, 0x20, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986a_pin_di_range[] = {
+ PIN_FIELD(0, 40, 0x200, 0x10, 0, 1),
+ PIN_FIELD(41, 65, 0x210, 0x10, 9, 1),
+ PIN_FIELD(66, 68, 0x220, 0x10, 2, 1),
+ PIN_FIELD(69, 100, 0x220, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986a_pin_do_range[] = {
+ PIN_FIELD(0, 40, 0x100, 0x10, 0, 1),
+ PIN_FIELD(41, 65, 0x110, 0x10, 9, 1),
+ PIN_FIELD(66, 68, 0x120, 0x10, 2, 1),
+ PIN_FIELD(69, 100, 0x120, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986b_pin_mode_range[] = {
+ PIN_FIELD(0, 40, 0x300, 0x10, 0, 4),
+ PIN_FIELD(66, 68, 0x380, 0x10, 8, 4),
+ PIN_FIELD(69, 100, 0x380, 0x10, 20, 4),
+};
+
+static const struct mtk_pin_field_calc mt7986b_pin_dir_range[] = {
+ PIN_FIELD(0, 40, 0x0, 0x10, 0, 1),
+ PIN_FIELD(66, 68, 0x20, 0x10, 2, 1),
+ PIN_FIELD(69, 100, 0x20, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986b_pin_di_range[] = {
+ PIN_FIELD(0, 40, 0x200, 0x10, 0, 1),
+ PIN_FIELD(66, 68, 0x220, 0x10, 2, 1),
+ PIN_FIELD(69, 100, 0x220, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986b_pin_do_range[] = {
+ PIN_FIELD(0, 40, 0x100, 0x10, 0, 1),
+ PIN_FIELD(66, 68, 0x120, 0x10, 2, 1),
+ PIN_FIELD(69, 100, 0x120, 0x10, 5, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986a_pin_ies_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1),
+ PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x20, 0x10, 10, 1),
+ PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x20, 0x10, 11, 1),
+ PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x20, 0x10, 0, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x20, 0x10, 1, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x40, 0x10, 0, 1),
+ PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x40, 0x10, 1, 1),
+ PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x20, 0x10, 0, 1),
+ PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x20, 0x10, 1, 1),
+ PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x20, 0x10, 2, 1),
+ PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x20, 0x10, 3, 1),
+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x40, 0x10, 8, 1),
+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x40, 0x10, 9, 1),
+ PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x40, 0x10, 10, 1),
+ PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x40, 0x10, 11, 1),
+ PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x40, 0x10, 2, 1),
+ PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x40, 0x10, 3, 1),
+ PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x40, 0x10, 4, 1),
+ PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x40, 0x10, 5, 1),
+ PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x40, 0x10, 6, 1),
+ PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x40, 0x10, 7, 1),
+ PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x30, 0x10, 12, 1),
+ PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x30, 0x10, 13, 1),
+ PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x30, 0x10, 14, 1),
+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1),
+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1),
+ PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x30, 0x10, 15, 1),
+ PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x30, 0x10, 16, 1),
+ PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x30, 0x10, 19, 1),
+ PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x30, 0x10, 20, 1),
+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1),
+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1),
+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1),
+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1),
+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1),
+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1),
+ PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x20, 0x10, 5, 1),
+ PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x20, 0x10, 6, 1),
+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x40, 0x10, 18, 1),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x40, 0x10, 19, 1),
+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x40, 0x10, 12, 1),
+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x40, 0x10, 22, 1),
+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x40, 0x10, 23, 1),
+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x40, 0x10, 20, 1),
+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x40, 0x10, 21, 1),
+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x40, 0x10, 26, 1),
+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x40, 0x10, 27, 1),
+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x40, 0x10, 24, 1),
+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x40, 0x10, 25, 1),
+ PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0x30, 0x10, 2, 1),
+ PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0x30, 0x10, 3, 1),
+ PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0x30, 0x10, 4, 1),
+ PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0x30, 0x10, 5, 1),
+ PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0x30, 0x10, 6, 1),
+ PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0x30, 0x10, 7, 1),
+ PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0x30, 0x10, 8, 1),
+ PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0x30, 0x10, 9, 1),
+ PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x30, 0x10, 1, 1),
+ PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x30, 0x10, 0, 1),
+ PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0x30, 0x10, 10, 1),
+ PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0x30, 0x10, 11, 1),
+ PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x40, 0x10, 15, 1),
+ PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x40, 0x10, 14, 1),
+ PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x40, 0x10, 13, 1),
+ PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x40, 0x10, 16, 1),
+ PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x20, 0x10, 2, 1),
+ PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x20, 0x10, 3, 1),
+ PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x20, 0x10, 4, 1),
+ PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1),
+ PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1),
+ PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x30, 0x10, 14, 1),
+ PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x30, 0x10, 15, 1),
+ PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1),
+ PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x30, 0x10, 6, 1),
+ PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x30, 0x10, 7, 1),
+ PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x30, 0x10, 8, 1),
+ PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x30, 0x10, 2, 1),
+ PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x30, 0x10, 3, 1),
+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x30, 0x10, 9, 1),
+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x30, 0x10, 10, 1),
+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x30, 0x10, 11, 1),
+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x30, 0x10, 12, 1),
+ PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x30, 0x10, 13, 1),
+ PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1),
+ PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
+ PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
+ PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
+ PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
+ PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x30, 0x10, 13, 1),
+ PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
+ PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x30, 0x10, 5, 1),
+ PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x30, 0x10, 6, 1),
+ PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x30, 0x10, 7, 1),
+ PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
+ PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x30, 0x10, 3, 1),
+ PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
+ PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x30, 0x10, 9, 1),
+ PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x30, 0x10, 10, 1),
+ PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x30, 0x10, 11, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986b_pin_ies_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1),
+ PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x20, 0x10, 10, 1),
+ PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x20, 0x10, 11, 1),
+ PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x20, 0x10, 0, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x20, 0x10, 1, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x40, 0x10, 0, 1),
+ PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x40, 0x10, 1, 1),
+ PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x20, 0x10, 0, 1),
+ PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x20, 0x10, 1, 1),
+ PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x20, 0x10, 2, 1),
+ PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x20, 0x10, 3, 1),
+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x40, 0x10, 8, 1),
+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x40, 0x10, 9, 1),
+ PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x40, 0x10, 10, 1),
+ PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x40, 0x10, 11, 1),
+ PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x40, 0x10, 2, 1),
+ PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x40, 0x10, 3, 1),
+ PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x40, 0x10, 4, 1),
+ PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x40, 0x10, 5, 1),
+ PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x40, 0x10, 6, 1),
+ PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x40, 0x10, 7, 1),
+ PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x30, 0x10, 12, 1),
+ PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x30, 0x10, 13, 1),
+ PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x30, 0x10, 14, 1),
+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1),
+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1),
+ PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x30, 0x10, 15, 1),
+ PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x30, 0x10, 16, 1),
+ PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x30, 0x10, 19, 1),
+ PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x30, 0x10, 20, 1),
+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1),
+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1),
+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1),
+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1),
+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1),
+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1),
+ PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x20, 0x10, 5, 1),
+ PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x20, 0x10, 6, 1),
+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x40, 0x10, 18, 1),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x40, 0x10, 19, 1),
+ PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x20, 0x10, 2, 1),
+ PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x20, 0x10, 3, 1),
+ PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x20, 0x10, 4, 1),
+ PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1),
+ PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1),
+ PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x30, 0x10, 14, 1),
+ PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x30, 0x10, 15, 1),
+ PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1),
+ PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x30, 0x10, 6, 1),
+ PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x30, 0x10, 7, 1),
+ PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x30, 0x10, 8, 1),
+ PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x30, 0x10, 2, 1),
+ PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x30, 0x10, 3, 1),
+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x30, 0x10, 9, 1),
+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x30, 0x10, 10, 1),
+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x30, 0x10, 11, 1),
+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x30, 0x10, 12, 1),
+ PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x30, 0x10, 13, 1),
+ PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1),
+ PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
+ PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
+ PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
+ PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
+ PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x30, 0x10, 13, 1),
+ PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
+ PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x30, 0x10, 5, 1),
+ PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x30, 0x10, 6, 1),
+ PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x30, 0x10, 7, 1),
+ PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
+ PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x30, 0x10, 3, 1),
+ PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
+ PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x30, 0x10, 9, 1),
+ PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x30, 0x10, 10, 1),
+ PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x30, 0x10, 11, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986a_pin_smt_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1),
+ PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x90, 0x10, 10, 1),
+ PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x90, 0x10, 11, 1),
+ PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x90, 0x10, 0, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x90, 0x10, 1, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1),
+ PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0xf0, 0x10, 1, 1),
+ PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x90, 0x10, 0, 1),
+ PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x90, 0x10, 1, 1),
+ PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x90, 0x10, 2, 1),
+ PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x90, 0x10, 3, 1),
+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1),
+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0xf0, 0x10, 9, 1),
+ PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0xf0, 0x10, 10, 1),
+ PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0xf0, 0x10, 11, 1),
+ PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1),
+ PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0xf0, 0x10, 3, 1),
+ PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0xf0, 0x10, 4, 1),
+ PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0xf0, 0x10, 5, 1),
+ PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0xf0, 0x10, 6, 1),
+ PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0xf0, 0x10, 7, 1),
+ PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1),
+ PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0xc0, 0x10, 13, 1),
+ PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0xc0, 0x10, 14, 1),
+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1),
+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1),
+ PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1),
+ PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0xc0, 0x10, 16, 1),
+ PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1),
+ PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0xc0, 0x10, 20, 1),
+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1),
+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1),
+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1),
+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1),
+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1),
+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1),
+ PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x90, 0x10, 5, 1),
+ PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x90, 0x10, 6, 1),
+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0xf0, 0x10, 19, 1),
+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xf0, 0x10, 12, 1),
+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0xf0, 0x10, 22, 1),
+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0xf0, 0x10, 23, 1),
+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0xf0, 0x10, 20, 1),
+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0xf0, 0x10, 21, 1),
+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0xf0, 0x10, 26, 1),
+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0xf0, 0x10, 27, 1),
+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0xf0, 0x10, 24, 1),
+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0xf0, 0x10, 25, 1),
+ PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0xc0, 0x10, 2, 1),
+ PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0xc0, 0x10, 3, 1),
+ PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0xc0, 0x10, 4, 1),
+ PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0xc0, 0x10, 5, 1),
+ PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0xc0, 0x10, 6, 1),
+ PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0xc0, 0x10, 7, 1),
+ PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0xc0, 0x10, 8, 1),
+ PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0xc0, 0x10, 9, 1),
+ PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0xc0, 0x10, 1, 1),
+ PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0xc0, 0x10, 0, 1),
+ PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0xc0, 0x10, 10, 1),
+ PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0xc0, 0x10, 11, 1),
+ PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0xf0, 0x10, 15, 1),
+ PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0xf0, 0x10, 14, 1),
+ PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0xf0, 0x10, 13, 1),
+ PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0xf0, 0x10, 16, 1),
+ PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x90, 0x10, 2, 1),
+ PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x90, 0x10, 3, 1),
+ PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x90, 0x10, 4, 1),
+ PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
+ PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
+ PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
+ PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x80, 0x10, 15, 1),
+ PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
+ PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
+ PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x80, 0x10, 7, 1),
+ PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x80, 0x10, 8, 1),
+ PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
+ PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x80, 0x10, 3, 1),
+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x80, 0x10, 10, 1),
+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x80, 0x10, 11, 1),
+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x80, 0x10, 12, 1),
+ PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x80, 0x10, 13, 1),
+ PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
+ PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
+ PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
+ PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1),
+ PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x70, 0x10, 12, 1),
+ PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x70, 0x10, 13, 1),
+ PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
+ PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x70, 0x10, 5, 1),
+ PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x70, 0x10, 6, 1),
+ PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x70, 0x10, 7, 1),
+ PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
+ PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x70, 0x10, 3, 1),
+ PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
+ PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x70, 0x10, 9, 1),
+ PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x70, 0x10, 10, 1),
+ PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x70, 0x10, 11, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986b_pin_smt_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1),
+ PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x90, 0x10, 10, 1),
+ PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x90, 0x10, 11, 1),
+ PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x90, 0x10, 0, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x90, 0x10, 1, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1),
+ PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0xf0, 0x10, 1, 1),
+ PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x90, 0x10, 0, 1),
+ PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x90, 0x10, 1, 1),
+ PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x90, 0x10, 2, 1),
+ PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x90, 0x10, 3, 1),
+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1),
+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0xf0, 0x10, 9, 1),
+ PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0xf0, 0x10, 10, 1),
+ PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0xf0, 0x10, 11, 1),
+ PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1),
+ PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0xf0, 0x10, 3, 1),
+ PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0xf0, 0x10, 4, 1),
+ PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0xf0, 0x10, 5, 1),
+ PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0xf0, 0x10, 6, 1),
+ PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0xf0, 0x10, 7, 1),
+ PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1),
+ PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0xc0, 0x10, 13, 1),
+ PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0xc0, 0x10, 14, 1),
+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1),
+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1),
+ PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1),
+ PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0xc0, 0x10, 16, 1),
+ PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1),
+ PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0xc0, 0x10, 20, 1),
+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1),
+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1),
+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1),
+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1),
+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1),
+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1),
+ PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x90, 0x10, 5, 1),
+ PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x90, 0x10, 6, 1),
+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0xf0, 0x10, 19, 1),
+ PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x90, 0x10, 2, 1),
+ PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x90, 0x10, 3, 1),
+ PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x90, 0x10, 4, 1),
+ PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
+ PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
+ PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
+ PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x80, 0x10, 15, 1),
+ PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
+ PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
+ PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x80, 0x10, 7, 1),
+ PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x80, 0x10, 8, 1),
+ PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
+ PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x80, 0x10, 3, 1),
+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x80, 0x10, 10, 1),
+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x80, 0x10, 11, 1),
+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x80, 0x10, 12, 1),
+ PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x80, 0x10, 13, 1),
+ PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
+ PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
+ PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
+ PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1),
+ PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x70, 0x10, 12, 1),
+ PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x70, 0x10, 13, 1),
+ PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
+ PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x70, 0x10, 5, 1),
+ PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x70, 0x10, 6, 1),
+ PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x70, 0x10, 7, 1),
+ PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
+ PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x70, 0x10, 3, 1),
+ PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
+ PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x70, 0x10, 9, 1),
+ PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x70, 0x10, 10, 1),
+ PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x70, 0x10, 11, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986_pin_pu_range[] = {
+ PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
+ PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1),
+ PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x50, 0x10, 14, 1),
+ PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x50, 0x10, 15, 1),
+ PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1),
+ PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x50, 0x10, 6, 1),
+ PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x50, 0x10, 7, 1),
+ PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x50, 0x10, 8, 1),
+ PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
+ PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x50, 0x10, 3, 1),
+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x50, 0x10, 9, 1),
+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x50, 0x10, 10, 1),
+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x50, 0x10, 11, 1),
+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x50, 0x10, 12, 1),
+ PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x50, 0x10, 13, 1),
+ PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1),
+ PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
+ PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
+ PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x50, 0x10, 14, 1),
+ PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x50, 0x10, 12, 1),
+ PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x50, 0x10, 13, 1),
+ PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
+ PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x50, 0x10, 5, 1),
+ PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x50, 0x10, 6, 1),
+ PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x50, 0x10, 7, 1),
+ PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
+ PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x50, 0x10, 3, 1),
+ PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
+ PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x50, 0x10, 9, 1),
+ PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x50, 0x10, 10, 1),
+ PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x50, 0x10, 11, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986_pin_pd_range[] = {
+ PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
+ PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x40, 0x10, 0, 1),
+ PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x40, 0x10, 16, 1),
+ PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x40, 0x10, 14, 1),
+ PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x40, 0x10, 15, 1),
+ PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x40, 0x10, 4, 1),
+ PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x40, 0x10, 6, 1),
+ PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x40, 0x10, 7, 1),
+ PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x40, 0x10, 8, 1),
+ PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x40, 0x10, 2, 1),
+ PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x40, 0x10, 3, 1),
+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x40, 0x10, 9, 1),
+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x40, 0x10, 10, 1),
+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x40, 0x10, 11, 1),
+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x40, 0x10, 12, 1),
+ PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x40, 0x10, 13, 1),
+ PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x40, 0x10, 5, 1),
+ PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
+ PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
+ PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x40, 0x10, 14, 1),
+ PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x40, 0x10, 12, 1),
+ PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x40, 0x10, 13, 1),
+ PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
+ PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x40, 0x10, 5, 1),
+ PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x40, 0x10, 6, 1),
+ PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x40, 0x10, 7, 1),
+ PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
+ PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x40, 0x10, 3, 1),
+ PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x40, 0x10, 8, 1),
+ PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x40, 0x10, 9, 1),
+ PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x40, 0x10, 10, 1),
+ PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x40, 0x10, 11, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986a_pin_drv_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
+ PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x10, 0x10, 0, 3),
+ PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x10, 0x10, 3, 3),
+ PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x00, 0x10, 0, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x00, 0x10, 1, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x00, 0x10, 6, 3),
+ PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x00, 0x10, 9, 3),
+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x00, 0x10, 27, 3),
+ PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
+ PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x10, 0x10, 3, 3),
+ PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x00, 0x10, 6, 3),
+ PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x00, 0x10, 9, 3),
+ PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x00, 0x10, 12, 3),
+ PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x00, 0x10, 18, 3),
+ PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x10, 0x10, 6, 3),
+ PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x10, 0x10, 9, 3),
+ PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x10, 0x10, 12, 3),
+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3),
+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3),
+ PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x10, 0x10, 15, 3),
+ PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x10, 0x10, 18, 3),
+ PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3),
+ PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3),
+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3),
+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3),
+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3),
+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3),
+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x00, 0x10, 18, 3),
+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x10, 0x10, 6, 3),
+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x20, 0x10, 9, 3),
+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x20, 0x10, 12, 3),
+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x20, 0x10, 3, 3),
+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x20, 0x10, 6, 3),
+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x20, 0x10, 21, 3),
+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x20, 0x10, 24, 3),
+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x20, 0x10, 15, 3),
+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x20, 0x10, 18, 3),
+ PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0x00, 0x10, 6, 3),
+ PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0x00, 0x10, 9, 3),
+ PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0x00, 0x10, 12, 3),
+ PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0x00, 0x10, 18, 3),
+ PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0x00, 0x10, 27, 3),
+ PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0x10, 0x10, 0, 3),
+ PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0x10, 0x10, 3, 3),
+ PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x10, 0x10, 15, 3),
+ PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x10, 0x10, 12, 3),
+ PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x10, 0x10, 9, 3),
+ PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x10, 0x10, 18, 3),
+ PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x00, 0x10, 2, 3),
+ PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x00, 0x10, 5, 3),
+ PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x00, 0x10, 8, 3),
+ PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
+ PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
+ PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x10, 0x10, 15, 3),
+ PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x00, 0x10, 18, 3),
+ PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
+ PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x00, 0x10, 9, 3),
+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x10, 0x10, 3, 3),
+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x10, 0x10, 6, 3),
+ PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x10, 0x10, 9, 3),
+ PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
+ PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3),
+ PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x10, 0x10, 6, 3),
+ PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x10, 0x10, 9, 3),
+ PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
+ PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x00, 0x10, 18, 3),
+ PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
+ PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x00, 0x10, 9, 3),
+ PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x00, 0x10, 27, 3),
+ PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x10, 0x10, 2, 3),
+ PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x10, 0x10, 5, 3),
+};
+
+static const struct mtk_pin_field_calc mt7986b_pin_drv_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
+ PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x10, 0x10, 0, 3),
+ PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x10, 0x10, 3, 3),
+ PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x00, 0x10, 0, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x00, 0x10, 1, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x00, 0x10, 6, 3),
+ PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x00, 0x10, 9, 3),
+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x00, 0x10, 27, 3),
+ PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
+ PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x10, 0x10, 3, 3),
+ PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x00, 0x10, 6, 3),
+ PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x00, 0x10, 9, 3),
+ PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x00, 0x10, 12, 3),
+ PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x00, 0x10, 18, 3),
+ PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x10, 0x10, 6, 3),
+ PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x10, 0x10, 9, 3),
+ PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x10, 0x10, 12, 3),
+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3),
+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3),
+ PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x10, 0x10, 15, 3),
+ PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x10, 0x10, 18, 3),
+ PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3),
+ PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3),
+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3),
+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3),
+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3),
+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3),
+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x00, 0x10, 18, 3),
+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
+ PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x00, 0x10, 2, 3),
+ PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x00, 0x10, 5, 3),
+ PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x00, 0x10, 8, 3),
+ PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
+ PIN_FIELD_BASE(72, 72, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
+ PIN_FIELD_BASE(73, 73, IOCFG_TR_BASE, 0x10, 0x10, 15, 3),
+ PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(75, 75, IOCFG_TR_BASE, 0x00, 0x10, 18, 3),
+ PIN_FIELD_BASE(76, 76, IOCFG_TR_BASE, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(77, 77, IOCFG_TR_BASE, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(78, 78, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
+ PIN_FIELD_BASE(79, 79, IOCFG_TR_BASE, 0x00, 0x10, 9, 3),
+ PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
+ PIN_FIELD_BASE(81, 81, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
+ PIN_FIELD_BASE(82, 82, IOCFG_TR_BASE, 0x10, 0x10, 3, 3),
+ PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x10, 0x10, 6, 3),
+ PIN_FIELD_BASE(84, 84, IOCFG_TR_BASE, 0x10, 0x10, 9, 3),
+ PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
+ PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
+ PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
+ PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3),
+ PIN_FIELD_BASE(89, 89, IOCFG_TL_BASE, 0x10, 0x10, 6, 3),
+ PIN_FIELD_BASE(90, 90, IOCFG_TL_BASE, 0x10, 0x10, 9, 3),
+ PIN_FIELD_BASE(91, 91, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
+ PIN_FIELD_BASE(92, 92, IOCFG_TL_BASE, 0x00, 0x10, 15, 3),
+ PIN_FIELD_BASE(93, 93, IOCFG_TL_BASE, 0x00, 0x10, 18, 3),
+ PIN_FIELD_BASE(94, 94, IOCFG_TL_BASE, 0x00, 0x10, 21, 3),
+ PIN_FIELD_BASE(95, 95, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
+ PIN_FIELD_BASE(96, 96, IOCFG_TL_BASE, 0x00, 0x10, 9, 3),
+ PIN_FIELD_BASE(97, 97, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
+ PIN_FIELD_BASE(98, 98, IOCFG_TL_BASE, 0x00, 0x10, 27, 3),
+ PIN_FIELD_BASE(99, 99, IOCFG_TL_BASE, 0x10, 0x10, 2, 3),
+ PIN_FIELD_BASE(100, 100, IOCFG_TL_BASE, 0x10, 0x10, 5, 3),
+};
+
+static const struct mtk_pin_field_calc mt7986a_pin_pupd_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1),
+ PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x30, 0x10, 10, 1),
+ PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x30, 0x10, 11, 1),
+ PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x40, 0x10, 1, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
+ PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x60, 0x10, 1, 1),
+ PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x30, 0x10, 0, 1),
+ PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x30, 0x10, 1, 1),
+ PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x30, 0x10, 2, 1),
+ PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x30, 0x10, 3, 1),
+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x60, 0x10, 8, 1),
+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x60, 0x10, 9, 1),
+ PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x60, 0x10, 10, 1),
+ PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x60, 0x10, 11, 1),
+ PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x60, 0x10, 2, 1),
+ PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x60, 0x10, 3, 1),
+ PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x60, 0x10, 4, 1),
+ PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x60, 0x10, 5, 1),
+ PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x60, 0x10, 6, 1),
+ PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x60, 0x10, 7, 1),
+ PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x40, 0x10, 12, 1),
+ PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x40, 0x10, 13, 1),
+ PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x40, 0x10, 14, 1),
+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1),
+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1),
+ PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x40, 0x10, 15, 1),
+ PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x40, 0x10, 16, 1),
+ PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x40, 0x10, 19, 1),
+ PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x40, 0x10, 20, 1),
+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1),
+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1),
+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1),
+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1),
+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1),
+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1),
+ PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x30, 0x10, 5, 1),
+ PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x30, 0x10, 6, 1),
+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x60, 0x10, 18, 1),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x60, 0x10, 19, 1),
+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1),
+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x60, 0x10, 22, 1),
+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1),
+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x60, 0x10, 20, 1),
+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1),
+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x60, 0x10, 26, 1),
+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1),
+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x60, 0x10, 24, 1),
+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1),
+ PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0x40, 0x10, 2, 1),
+ PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0x40, 0x10, 3, 1),
+ PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0x40, 0x10, 4, 1),
+ PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0x40, 0x10, 5, 1),
+ PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0x40, 0x10, 6, 1),
+ PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0x40, 0x10, 7, 1),
+ PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0x40, 0x10, 8, 1),
+ PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0x40, 0x10, 9, 1),
+ PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1),
+ PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1),
+ PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0x40, 0x10, 10, 1),
+ PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0x40, 0x10, 11, 1),
+ PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x60, 0x10, 15, 1),
+ PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x60, 0x10, 14, 1),
+ PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x60, 0x10, 13, 1),
+ PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x60, 0x10, 16, 1),
+ PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
+ PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x40, 0x10, 3, 1),
+ PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x40, 0x10, 4, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986b_pin_pupd_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1),
+ PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x30, 0x10, 10, 1),
+ PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x30, 0x10, 11, 1),
+ PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x40, 0x10, 1, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
+ PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x60, 0x10, 1, 1),
+ PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x30, 0x10, 0, 1),
+ PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x30, 0x10, 1, 1),
+ PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x30, 0x10, 2, 1),
+ PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x30, 0x10, 3, 1),
+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x60, 0x10, 8, 1),
+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x60, 0x10, 9, 1),
+ PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x60, 0x10, 10, 1),
+ PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x60, 0x10, 11, 1),
+ PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x60, 0x10, 2, 1),
+ PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x60, 0x10, 3, 1),
+ PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x60, 0x10, 4, 1),
+ PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x60, 0x10, 5, 1),
+ PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x60, 0x10, 6, 1),
+ PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x60, 0x10, 7, 1),
+ PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x40, 0x10, 12, 1),
+ PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x40, 0x10, 13, 1),
+ PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x40, 0x10, 14, 1),
+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1),
+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1),
+ PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x40, 0x10, 15, 1),
+ PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x40, 0x10, 16, 1),
+ PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x40, 0x10, 19, 1),
+ PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x40, 0x10, 20, 1),
+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1),
+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1),
+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1),
+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1),
+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1),
+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1),
+ PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x30, 0x10, 5, 1),
+ PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x30, 0x10, 6, 1),
+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x60, 0x10, 18, 1),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x60, 0x10, 19, 1),
+ PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
+ PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x40, 0x10, 3, 1),
+ PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x40, 0x10, 4, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986b_pin_r0_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
+ PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x40, 0x10, 10, 1),
+ PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x40, 0x10, 11, 1),
+ PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x50, 0x10, 1, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
+ PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x70, 0x10, 1, 1),
+ PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x40, 0x10, 0, 1),
+ PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x40, 0x10, 1, 1),
+ PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x40, 0x10, 2, 1),
+ PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x40, 0x10, 3, 1),
+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x70, 0x10, 9, 1),
+ PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x70, 0x10, 10, 1),
+ PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x70, 0x10, 11, 1),
+ PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
+ PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x70, 0x10, 3, 1),
+ PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x70, 0x10, 4, 1),
+ PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x70, 0x10, 5, 1),
+ PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x70, 0x10, 6, 1),
+ PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x70, 0x10, 7, 1),
+ PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x50, 0x10, 12, 1),
+ PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x50, 0x10, 13, 1),
+ PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x50, 0x10, 14, 1),
+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1),
+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1),
+ PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x50, 0x10, 15, 1),
+ PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x50, 0x10, 16, 1),
+ PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x50, 0x10, 19, 1),
+ PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x50, 0x10, 20, 1),
+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1),
+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1),
+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1),
+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1),
+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1),
+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1),
+ PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x40, 0x10, 5, 1),
+ PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x40, 0x10, 6, 1),
+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x70, 0x10, 19, 1),
+ PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
+ PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x50, 0x10, 3, 1),
+ PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x50, 0x10, 4, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986a_pin_r0_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
+ PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x40, 0x10, 10, 1),
+ PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x40, 0x10, 11, 1),
+ PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x50, 0x10, 1, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
+ PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x70, 0x10, 1, 1),
+ PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x40, 0x10, 0, 1),
+ PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x40, 0x10, 1, 1),
+ PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x40, 0x10, 2, 1),
+ PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x40, 0x10, 3, 1),
+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x70, 0x10, 9, 1),
+ PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x70, 0x10, 10, 1),
+ PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x70, 0x10, 11, 1),
+ PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
+ PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x70, 0x10, 3, 1),
+ PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x70, 0x10, 4, 1),
+ PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x70, 0x10, 5, 1),
+ PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x70, 0x10, 6, 1),
+ PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x70, 0x10, 7, 1),
+ PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x50, 0x10, 12, 1),
+ PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x50, 0x10, 13, 1),
+ PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x50, 0x10, 14, 1),
+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1),
+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1),
+ PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x50, 0x10, 15, 1),
+ PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x50, 0x10, 16, 1),
+ PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x50, 0x10, 19, 1),
+ PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x50, 0x10, 20, 1),
+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1),
+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1),
+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1),
+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1),
+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1),
+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1),
+ PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x40, 0x10, 5, 1),
+ PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x40, 0x10, 6, 1),
+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x70, 0x10, 19, 1),
+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x70, 0x10, 22, 1),
+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1),
+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x70, 0x10, 20, 1),
+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1),
+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x70, 0x10, 26, 1),
+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1),
+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x70, 0x10, 24, 1),
+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1),
+ PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0x50, 0x10, 2, 1),
+ PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0x50, 0x10, 3, 1),
+ PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0x50, 0x10, 4, 1),
+ PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0x50, 0x10, 5, 1),
+ PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0x50, 0x10, 6, 1),
+ PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0x50, 0x10, 7, 1),
+ PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0x50, 0x10, 8, 1),
+ PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0x50, 0x10, 9, 1),
+ PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1),
+ PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1),
+ PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0x50, 0x10, 10, 1),
+ PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0x50, 0x10, 11, 1),
+ PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x70, 0x10, 15, 1),
+ PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x70, 0x10, 14, 1),
+ PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x70, 0x10, 13, 1),
+ PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x70, 0x10, 16, 1),
+ PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
+ PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x50, 0x10, 3, 1),
+ PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x50, 0x10, 4, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986a_pin_r1_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1),
+ PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x50, 0x10, 10, 1),
+ PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x50, 0x10, 11, 1),
+ PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x60, 0x10, 1, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
+ PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x80, 0x10, 1, 1),
+ PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x50, 0x10, 0, 1),
+ PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x50, 0x10, 1, 1),
+ PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x50, 0x10, 2, 1),
+ PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x50, 0x10, 3, 1),
+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x80, 0x10, 8, 1),
+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x80, 0x10, 9, 1),
+ PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x80, 0x10, 10, 1),
+ PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x80, 0x10, 11, 1),
+ PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x80, 0x10, 2, 1),
+ PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x80, 0x10, 3, 1),
+ PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x80, 0x10, 4, 1),
+ PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x80, 0x10, 5, 1),
+ PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x80, 0x10, 6, 1),
+ PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x80, 0x10, 7, 1),
+ PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x60, 0x10, 12, 1),
+ PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x60, 0x10, 13, 1),
+ PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x60, 0x10, 14, 1),
+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1),
+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1),
+ PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x60, 0x10, 15, 1),
+ PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x60, 0x10, 16, 1),
+ PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x60, 0x10, 19, 1),
+ PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x60, 0x10, 20, 1),
+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1),
+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1),
+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1),
+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1),
+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1),
+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1),
+ PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x50, 0x10, 5, 1),
+ PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x50, 0x10, 6, 1),
+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x80, 0x10, 18, 1),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x80, 0x10, 19, 1),
+ PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1),
+ PIN_FIELD_BASE(42, 42, IOCFG_RB_BASE, 0x80, 0x10, 22, 1),
+ PIN_FIELD_BASE(43, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1),
+ PIN_FIELD_BASE(44, 44, IOCFG_RB_BASE, 0x80, 0x10, 20, 1),
+ PIN_FIELD_BASE(45, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1),
+ PIN_FIELD_BASE(46, 46, IOCFG_RB_BASE, 0x80, 0x10, 26, 1),
+ PIN_FIELD_BASE(47, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1),
+ PIN_FIELD_BASE(48, 48, IOCFG_RB_BASE, 0x80, 0x10, 24, 1),
+ PIN_FIELD_BASE(49, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1),
+ PIN_FIELD_BASE(50, 50, IOCFG_RT_BASE, 0x60, 0x10, 2, 1),
+ PIN_FIELD_BASE(51, 51, IOCFG_RT_BASE, 0x60, 0x10, 3, 1),
+ PIN_FIELD_BASE(52, 52, IOCFG_RT_BASE, 0x60, 0x10, 4, 1),
+ PIN_FIELD_BASE(53, 53, IOCFG_RT_BASE, 0x60, 0x10, 5, 1),
+ PIN_FIELD_BASE(54, 54, IOCFG_RT_BASE, 0x60, 0x10, 6, 1),
+ PIN_FIELD_BASE(55, 55, IOCFG_RT_BASE, 0x60, 0x10, 7, 1),
+ PIN_FIELD_BASE(56, 56, IOCFG_RT_BASE, 0x60, 0x10, 8, 1),
+ PIN_FIELD_BASE(57, 57, IOCFG_RT_BASE, 0x60, 0x10, 9, 1),
+ PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1),
+ PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1),
+ PIN_FIELD_BASE(60, 60, IOCFG_RT_BASE, 0x60, 0x10, 10, 1),
+ PIN_FIELD_BASE(61, 61, IOCFG_RT_BASE, 0x60, 0x10, 11, 1),
+ PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x80, 0x10, 15, 1),
+ PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x80, 0x10, 14, 1),
+ PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1),
+ PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1),
+ PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
+ PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x60, 0x10, 3, 1),
+ PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x60, 0x10, 4, 1),
+};
+
+static const struct mtk_pin_field_calc mt7986b_pin_r1_range[] = {
+ PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1),
+ PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x50, 0x10, 10, 1),
+ PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x50, 0x10, 11, 1),
+ PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
+ PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x60, 0x10, 1, 1),
+ PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
+ PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x80, 0x10, 1, 1),
+ PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x50, 0x10, 0, 1),
+ PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x50, 0x10, 1, 1),
+ PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x50, 0x10, 2, 1),
+ PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x50, 0x10, 3, 1),
+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x80, 0x10, 8, 1),
+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x80, 0x10, 9, 1),
+ PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x80, 0x10, 10, 1),
+ PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x80, 0x10, 11, 1),
+ PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x80, 0x10, 2, 1),
+ PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x80, 0x10, 3, 1),
+ PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x80, 0x10, 4, 1),
+ PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x80, 0x10, 5, 1),
+ PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x80, 0x10, 6, 1),
+ PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x80, 0x10, 7, 1),
+ PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x60, 0x10, 12, 1),
+ PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x60, 0x10, 13, 1),
+ PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x60, 0x10, 14, 1),
+ PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1),
+ PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1),
+ PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x60, 0x10, 15, 1),
+ PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x60, 0x10, 16, 1),
+ PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x60, 0x10, 19, 1),
+ PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x60, 0x10, 20, 1),
+ PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1),
+ PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1),
+ PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1),
+ PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1),
+ PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1),
+ PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1),
+ PIN_FIELD_BASE(36, 36, IOCFG_LT_BASE, 0x50, 0x10, 5, 1),
+ PIN_FIELD_BASE(37, 37, IOCFG_LT_BASE, 0x50, 0x10, 6, 1),
+ PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1),
+ PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x80, 0x10, 18, 1),
+ PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x80, 0x10, 19, 1),
+ PIN_FIELD_BASE(66, 66, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
+ PIN_FIELD_BASE(67, 67, IOCFG_LB_BASE, 0x60, 0x10, 3, 1),
+ PIN_FIELD_BASE(68, 68, IOCFG_LB_BASE, 0x60, 0x10, 4, 1),
+};
+
+static const struct mtk_pin_reg_calc mt7986a_reg_cals[] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986a_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986a_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986a_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986a_pin_do_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986a_pin_smt_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986a_pin_ies_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986a_pin_drv_range),
+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range),
+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range),
+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986a_pin_pupd_range),
+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986a_pin_r0_range),
+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986a_pin_r1_range),
+};
+
+static const struct mtk_pin_reg_calc mt7986b_reg_cals[] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986b_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986b_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986b_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986b_pin_do_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986b_pin_smt_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986b_pin_ies_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986b_pin_drv_range),
+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range),
+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range),
+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986b_pin_pupd_range),
+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986b_pin_r0_range),
+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986b_pin_r1_range),
+};
+
+static const struct mtk_pin_desc mt7986a_pins[] = {
+ MT7986_PIN(0, "SYS_WATCHDOG"),
+ MT7986_PIN(1, "WF2G_LED"),
+ MT7986_PIN(2, "WF5G_LED"),
+ MT7986_PIN(3, "I2C_SCL"),
+ MT7986_PIN(4, "I2C_SDA"),
+ MT7986_PIN(5, "GPIO_0"),
+ MT7986_PIN(6, "GPIO_1"),
+ MT7986_PIN(7, "GPIO_2"),
+ MT7986_PIN(8, "GPIO_3"),
+ MT7986_PIN(9, "GPIO_4"),
+ MT7986_PIN(10, "GPIO_5"),
+ MT7986_PIN(11, "GPIO_6"),
+ MT7986_PIN(12, "GPIO_7"),
+ MT7986_PIN(13, "GPIO_8"),
+ MT7986_PIN(14, "GPIO_9"),
+ MT7986_PIN(15, "GPIO_10"),
+ MT7986_PIN(16, "GPIO_11"),
+ MT7986_PIN(17, "GPIO_12"),
+ MT7986_PIN(18, "GPIO_13"),
+ MT7986_PIN(19, "GPIO_14"),
+ MT7986_PIN(20, "GPIO_15"),
+ MT7986_PIN(21, "PWM0"),
+ MT7986_PIN(22, "PWM1"),
+ MT7986_PIN(23, "SPI0_CLK"),
+ MT7986_PIN(24, "SPI0_MOSI"),
+ MT7986_PIN(25, "SPI0_MISO"),
+ MT7986_PIN(26, "SPI0_CS"),
+ MT7986_PIN(27, "SPI0_HOLD"),
+ MT7986_PIN(28, "SPI0_WP"),
+ MT7986_PIN(29, "SPI1_CLK"),
+ MT7986_PIN(30, "SPI1_MOSI"),
+ MT7986_PIN(31, "SPI1_MISO"),
+ MT7986_PIN(32, "SPI1_CS"),
+ MT7986_PIN(33, "SPI2_CLK"),
+ MT7986_PIN(34, "SPI2_MOSI"),
+ MT7986_PIN(35, "SPI2_MISO"),
+ MT7986_PIN(36, "SPI2_CS"),
+ MT7986_PIN(37, "SPI2_HOLD"),
+ MT7986_PIN(38, "SPI2_WP"),
+ MT7986_PIN(39, "UART0_RXD"),
+ MT7986_PIN(40, "UART0_TXD"),
+ MT7986_PIN(41, "PCIE_PERESET_N"),
+ MT7986_PIN(42, "UART1_RXD"),
+ MT7986_PIN(43, "UART1_TXD"),
+ MT7986_PIN(44, "UART1_CTS"),
+ MT7986_PIN(45, "UART1_RTS"),
+ MT7986_PIN(46, "UART2_RXD"),
+ MT7986_PIN(47, "UART2_TXD"),
+ MT7986_PIN(48, "UART2_CTS"),
+ MT7986_PIN(49, "UART2_RTS"),
+ MT7986_PIN(50, "EMMC_DATA_0"),
+ MT7986_PIN(51, "EMMC_DATA_1"),
+ MT7986_PIN(52, "EMMC_DATA_2"),
+ MT7986_PIN(53, "EMMC_DATA_3"),
+ MT7986_PIN(54, "EMMC_DATA_4"),
+ MT7986_PIN(55, "EMMC_DATA_5"),
+ MT7986_PIN(56, "EMMC_DATA_6"),
+ MT7986_PIN(57, "EMMC_DATA_7"),
+ MT7986_PIN(58, "EMMC_CMD"),
+ MT7986_PIN(59, "EMMC_CK"),
+ MT7986_PIN(60, "EMMC_DSL"),
+ MT7986_PIN(61, "EMMC_RSTB"),
+ MT7986_PIN(62, "PCM_DTX"),
+ MT7986_PIN(63, "PCM_DRX"),
+ MT7986_PIN(64, "PCM_CLK"),
+ MT7986_PIN(65, "PCM_FS"),
+ MT7986_PIN(66, "MT7531_INT"),
+ MT7986_PIN(67, "SMI_MDC"),
+ MT7986_PIN(68, "SMI_MDIO"),
+ MT7986_PIN(69, "WF0_DIG_RESETB"),
+ MT7986_PIN(70, "WF0_CBA_RESETB"),
+ MT7986_PIN(71, "WF0_XO_REQ"),
+ MT7986_PIN(72, "WF0_TOP_CLK"),
+ MT7986_PIN(73, "WF0_TOP_DATA"),
+ MT7986_PIN(74, "WF0_HB1"),
+ MT7986_PIN(75, "WF0_HB2"),
+ MT7986_PIN(76, "WF0_HB3"),
+ MT7986_PIN(77, "WF0_HB4"),
+ MT7986_PIN(78, "WF0_HB0"),
+ MT7986_PIN(79, "WF0_HB0_B"),
+ MT7986_PIN(80, "WF0_HB5"),
+ MT7986_PIN(81, "WF0_HB6"),
+ MT7986_PIN(82, "WF0_HB7"),
+ MT7986_PIN(83, "WF0_HB8"),
+ MT7986_PIN(84, "WF0_HB9"),
+ MT7986_PIN(85, "WF0_HB10"),
+ MT7986_PIN(86, "WF1_DIG_RESETB"),
+ MT7986_PIN(87, "WF1_CBA_RESETB"),
+ MT7986_PIN(88, "WF1_XO_REQ"),
+ MT7986_PIN(89, "WF1_TOP_CLK"),
+ MT7986_PIN(90, "WF1_TOP_DATA"),
+ MT7986_PIN(91, "WF1_HB1"),
+ MT7986_PIN(92, "WF1_HB2"),
+ MT7986_PIN(93, "WF1_HB3"),
+ MT7986_PIN(94, "WF1_HB4"),
+ MT7986_PIN(95, "WF1_HB0"),
+ MT7986_PIN(96, "WF1_HB0_B"),
+ MT7986_PIN(97, "WF1_HB5"),
+ MT7986_PIN(98, "WF1_HB6"),
+ MT7986_PIN(99, "WF1_HB7"),
+ MT7986_PIN(100, "WF1_HB8"),
+};
+
+static const struct mtk_pin_desc mt7986b_pins[] = {
+ MT7986_PIN(0, "SYS_WATCHDOG"),
+ MT7986_PIN(1, "WF2G_LED"),
+ MT7986_PIN(2, "WF5G_LED"),
+ MT7986_PIN(3, "I2C_SCL"),
+ MT7986_PIN(4, "I2C_SDA"),
+ MT7986_PIN(5, "GPIO_0"),
+ MT7986_PIN(6, "GPIO_1"),
+ MT7986_PIN(7, "GPIO_2"),
+ MT7986_PIN(8, "GPIO_3"),
+ MT7986_PIN(9, "GPIO_4"),
+ MT7986_PIN(10, "GPIO_5"),
+ MT7986_PIN(11, "GPIO_6"),
+ MT7986_PIN(12, "GPIO_7"),
+ MT7986_PIN(13, "GPIO_8"),
+ MT7986_PIN(14, "GPIO_9"),
+ MT7986_PIN(15, "GPIO_10"),
+ MT7986_PIN(16, "GPIO_11"),
+ MT7986_PIN(17, "GPIO_12"),
+ MT7986_PIN(18, "GPIO_13"),
+ MT7986_PIN(19, "GPIO_14"),
+ MT7986_PIN(20, "GPIO_15"),
+ MT7986_PIN(21, "PWM0"),
+ MT7986_PIN(22, "PWM1"),
+ MT7986_PIN(23, "SPI0_CLK"),
+ MT7986_PIN(24, "SPI0_MOSI"),
+ MT7986_PIN(25, "SPI0_MISO"),
+ MT7986_PIN(26, "SPI0_CS"),
+ MT7986_PIN(27, "SPI0_HOLD"),
+ MT7986_PIN(28, "SPI0_WP"),
+ MT7986_PIN(29, "SPI1_CLK"),
+ MT7986_PIN(30, "SPI1_MOSI"),
+ MT7986_PIN(31, "SPI1_MISO"),
+ MT7986_PIN(32, "SPI1_CS"),
+ MT7986_PIN(33, "SPI2_CLK"),
+ MT7986_PIN(34, "SPI2_MOSI"),
+ MT7986_PIN(35, "SPI2_MISO"),
+ MT7986_PIN(36, "SPI2_CS"),
+ MT7986_PIN(37, "SPI2_HOLD"),
+ MT7986_PIN(38, "SPI2_WP"),
+ MT7986_PIN(39, "UART0_RXD"),
+ MT7986_PIN(40, "UART0_TXD"),
+ MT7986_PIN(66, "MT7531_INT"),
+ MT7986_PIN(67, "SMI_MDC"),
+ MT7986_PIN(68, "SMI_MDIO"),
+ MT7986_PIN(69, "WF0_DIG_RESETB"),
+ MT7986_PIN(70, "WF0_CBA_RESETB"),
+ MT7986_PIN(71, "WF0_XO_REQ"),
+ MT7986_PIN(72, "WF0_TOP_CLK"),
+ MT7986_PIN(73, "WF0_TOP_DATA"),
+ MT7986_PIN(74, "WF0_HB1"),
+ MT7986_PIN(75, "WF0_HB2"),
+ MT7986_PIN(76, "WF0_HB3"),
+ MT7986_PIN(77, "WF0_HB4"),
+ MT7986_PIN(78, "WF0_HB0"),
+ MT7986_PIN(79, "WF0_HB0_B"),
+ MT7986_PIN(80, "WF0_HB5"),
+ MT7986_PIN(81, "WF0_HB6"),
+ MT7986_PIN(82, "WF0_HB7"),
+ MT7986_PIN(83, "WF0_HB8"),
+ MT7986_PIN(84, "WF0_HB9"),
+ MT7986_PIN(85, "WF0_HB10"),
+ MT7986_PIN(86, "WF1_DIG_RESETB"),
+ MT7986_PIN(87, "WF1_CBA_RESETB"),
+ MT7986_PIN(88, "WF1_XO_REQ"),
+ MT7986_PIN(89, "WF1_TOP_CLK"),
+ MT7986_PIN(90, "WF1_TOP_DATA"),
+ MT7986_PIN(91, "WF1_HB1"),
+ MT7986_PIN(92, "WF1_HB2"),
+ MT7986_PIN(93, "WF1_HB3"),
+ MT7986_PIN(94, "WF1_HB4"),
+ MT7986_PIN(95, "WF1_HB0"),
+ MT7986_PIN(96, "WF1_HB0_B"),
+ MT7986_PIN(97, "WF1_HB5"),
+ MT7986_PIN(98, "WF1_HB6"),
+ MT7986_PIN(99, "WF1_HB7"),
+ MT7986_PIN(100, "WF1_HB8"),
+};
+
+/* List all groups consisting of these pins dedicated to the enablement of
+ * certain hardware block and the corresponding mode for all of the pins.
+ * The hardware probably has multiple combinations of these pinouts.
+ */
+
+static int mt7986_watchdog_pins[] = { 0, };
+static int mt7986_watchdog_funcs[] = { 1, };
+
+static int mt7986_wifi_led_pins[] = { 1, 2, };
+static int mt7986_wifi_led_funcs[] = { 1, 1, };
+
+static int mt7986_i2c_pins[] = { 3, 4, };
+static int mt7986_i2c_funcs[] = { 1, 1, };
+
+static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
+static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
+
+static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
+static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
+
+static int mt7986_pwm1_1_pins[] = { 20, };
+static int mt7986_pwm1_1_funcs[] = { 2, };
+
+static int mt7986_pwm0_pins[] = { 21, };
+static int mt7986_pwm0_funcs[] = { 1, };
+
+static int mt7986_pwm1_0_pins[] = { 22, };
+static int mt7986_pwm1_0_funcs[] = { 1, };
+
+static int mt7986_emmc_45_pins[] = {
+ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, };
+static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
+
+static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
+static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
+
+static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
+static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
+
+static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
+static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
+
+static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
+static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
+
+static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
+static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
+
+static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
+static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
+
+static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
+static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
+
+static int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
+static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
+
+static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
+static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
+
+static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
+static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
+
+static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
+static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
+
+static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
+static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
+
+static int mt7986_uart0_pins[] = { 39, 40, };
+static int mt7986_uart0_funcs[] = { 1, 1, };
+
+static int mt7986_pcie_reset_pins[] = { 41, };
+static int mt7986_pcie_reset_funcs[] = { 1, };
+
+static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
+static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
+
+static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
+static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
+
+static int mt7986_emmc_51_pins[] = {
+ 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, };
+static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+
+static int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
+static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
+
+static int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
+static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
+
+static int mt7986_switch_int_pins[] = { 66, };
+static int mt7986_switch_int_funcs[] = { 1, };
+
+static int mt7986_mdc_mdio_pins[] = { 67, 68, };
+static int mt7986_mdc_mdio_funcs[] = { 1, 1, };
+
+static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
+static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+
+static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
+static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+
+static int mt7986_wf_dbdc_pins[] = {
+ 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
+static int mt7986_wf_dbdc_funcs[] = {
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
+
+static int mt7986_pcie_clk_pins[] = { 9, };
+static int mt7986_pcie_clk_funcs[] = { 1, };
+
+static int mt7986_pcie_wake_pins[] = { 10, };
+static int mt7986_pcie_wake_funcs[] = { 1, };
+
+static const struct group_desc mt7986a_groups[] = {
+ PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog),
+ PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
+ PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
+ PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
+ PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
+ PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
+ PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
+ PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1),
+ PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0),
+ PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0),
+ PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45),
+ PINCTRL_PIN_GROUP("snfi", mt7986_snfi),
+ PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
+ PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
+ PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
+ PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2),
+ PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0),
+ PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
+ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
+ PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
+ PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx),
+ PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts),
+ PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3),
+ PINCTRL_PIN_GROUP("uart0", mt7986_uart0),
+ PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int),
+ PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio),
+ PINCTRL_PIN_GROUP("pcie_pereset", mt7986_pcie_reset),
+ PINCTRL_PIN_GROUP("uart1", mt7986_uart1),
+ PINCTRL_PIN_GROUP("uart2", mt7986_uart2),
+ PINCTRL_PIN_GROUP("emmc_51", mt7986_emmc_51),
+ PINCTRL_PIN_GROUP("pcm", mt7986_pcm),
+ PINCTRL_PIN_GROUP("i2s", mt7986_i2s),
+ PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g),
+ PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g),
+ PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc),
+};
+
+static const struct group_desc mt7986b_groups[] = {
+ PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog),
+ PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
+ PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
+ PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
+ PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
+ PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
+ PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
+ PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1),
+ PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0),
+ PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0),
+ PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45),
+ PINCTRL_PIN_GROUP("snfi", mt7986_snfi),
+ PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
+ PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
+ PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
+ PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2),
+ PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0),
+ PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
+ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
+ PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
+ PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx),
+ PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts),
+ PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3),
+ PINCTRL_PIN_GROUP("uart0", mt7986_uart0),
+ PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int),
+ PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio),
+ PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g),
+ PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g),
+ PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc),
+};
+
+/* Joint those groups owning the same capability in user point of view which
+ * allows that people tend to use through the device tree.
+ */
+
+static const char *mt7986_audio_groups[] = { "pcm", "i2s" };
+static const char *mt7986_emmc_groups[] = { "emmc_45", "emmc_51", };
+static const char *mt7986_ethernet_groups[] = { "switch_int", "mdc_mdio", };
+static const char *mt7986_i2c_groups[] = { "i2c", };
+static const char *mt7986_led_groups[] = { "wifi_led", };
+static const char *mt7986_flash_groups[] = { "snfi", };
+static const char *mt7986_pcie_groups[] = {
+ "pcie_clk", "pcie_wake", "pcie_pereset" };
+static const char *mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", };
+static const char *mt7986_spi_groups[] = {
+ "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
+
+static const char *mt7986_uart_groups[] = {
+ "uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts",
+ "uart2_0", "uart2_1", "uart0", "uart1", "uart2",
+};
+static const char *mt7986_wdt_groups[] = { "watchdog", };
+static const char *mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", };
+
+static const struct function_desc mt7986_functions[] = {
+ {"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)},
+ {"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)},
+ {"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)},
+ {"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)},
+ {"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)},
+ {"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)},
+ {"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)},
+ {"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)},
+ {"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)},
+ {"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)},
+ {"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)},
+ {"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)},
+};
+
+static const struct mtk_eint_hw mt7986a_eint_hw = {
+ .port_mask = 7,
+ .ports = 7,
+ .ap_num = ARRAY_SIZE(mt7986a_pins),
+ .db_cnt = 16,
+};
+
+static const struct mtk_eint_hw mt7986b_eint_hw = {
+ .port_mask = 7,
+ .ports = 7,
+ .ap_num = ARRAY_SIZE(mt7986b_pins),
+ .db_cnt = 16,
+};
+
+static struct mtk_pin_soc mt7986a_data = {
+ .reg_cal = mt7986a_reg_cals,
+ .pins = mt7986a_pins,
+ .npins = ARRAY_SIZE(mt7986a_pins),
+ .grps = mt7986a_groups,
+ .ngrps = ARRAY_SIZE(mt7986a_groups),
+ .funcs = mt7986_functions,
+ .nfuncs = ARRAY_SIZE(mt7986_functions),
+ .eint_hw = &mt7986a_eint_hw,
+ .gpio_m = 0,
+ .ies_present = false,
+ .base_names = mt7986_pinctrl_register_base_names,
+ .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
+ .bias_set_combo = mtk_pinconf_bias_set_combo,
+ .bias_get_combo = mtk_pinconf_bias_get_combo,
+ .drive_set = mtk_pinconf_drive_set_rev1,
+ .drive_get = mtk_pinconf_drive_get_rev1,
+ .adv_pull_get = mtk_pinconf_adv_pull_get,
+ .adv_pull_set = mtk_pinconf_adv_pull_set,
+};
+
+static struct mtk_pin_soc mt7986b_data = {
+ .reg_cal = mt7986b_reg_cals,
+ .pins = mt7986b_pins,
+ .npins = ARRAY_SIZE(mt7986b_pins),
+ .grps = mt7986b_groups,
+ .ngrps = ARRAY_SIZE(mt7986b_groups),
+ .funcs = mt7986_functions,
+ .nfuncs = ARRAY_SIZE(mt7986_functions),
+ .eint_hw = &mt7986b_eint_hw,
+ .gpio_m = 0,
+ .ies_present = false,
+ .base_names = mt7986_pinctrl_register_base_names,
+ .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
+ .bias_set_combo = mtk_pinconf_bias_set_combo,
+ .bias_get_combo = mtk_pinconf_bias_get_combo,
+ .drive_set = mtk_pinconf_drive_set_rev1,
+ .drive_get = mtk_pinconf_drive_get_rev1,
+ .adv_pull_get = mtk_pinconf_adv_pull_get,
+ .adv_pull_set = mtk_pinconf_adv_pull_set,
+};
+
+static const struct of_device_id mt7986b_pinctrl_of_match[] = {
+ {.compatible = "mediatek,mt7986b-pinctrl",},
+ {}
+};
+
+static const struct of_device_id mt7986a_pinctrl_of_match[] = {
+ {.compatible = "mediatek,mt7986a-pinctrl",},
+ {}
+};
+
+static int mt7986a_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_moore_pinctrl_probe(pdev, &mt7986a_data);
+}
+
+static int mt7986b_pinctrl_probe(struct platform_device *pdev)
+{
+ return mtk_moore_pinctrl_probe(pdev, &mt7986b_data);
+}
+
+static struct platform_driver mt7986a_pinctrl_driver = {
+ .driver = {
+ .name = "mt7986a-pinctrl",
+ .of_match_table = mt7986a_pinctrl_of_match,
+ },
+ .probe = mt7986a_pinctrl_probe,
+};
+
+static struct platform_driver mt7986b_pinctrl_driver = {
+ .driver = {
+ .name = "mt7986b-pinctrl",
+ .of_match_table = mt7986b_pinctrl_of_match,
+ },
+ .probe = mt7986b_pinctrl_probe,
+};
+
+static int __init mt7986a_pinctrl_init(void)
+{
+ return platform_driver_register(&mt7986a_pinctrl_driver);
+}
+
+static int __init mt7986b_pinctrl_init(void)
+{
+ return platform_driver_register(&mt7986b_pinctrl_driver);
+}
+
+arch_initcall(mt7986a_pinctrl_init);
+arch_initcall(mt7986b_pinctrl_init);
--
2.29.2

2021-07-26 07:18:20

by Sam Shih

[permalink] [raw]
Subject: [PATCH 08/12] dt-bindings: rng: mediatek: add mt7986 to mtk rng binding

Add RNG binding for MT7986 SoC.

Signed-off-by: Sam Shih <[email protected]>
---
Documentation/devicetree/bindings/rng/mtk-rng.yaml | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/rng/mtk-rng.yaml b/Documentation/devicetree/bindings/rng/mtk-rng.yaml
index 61888e07bda0..bb32491ee8ae 100644
--- a/Documentation/devicetree/bindings/rng/mtk-rng.yaml
+++ b/Documentation/devicetree/bindings/rng/mtk-rng.yaml
@@ -21,6 +21,7 @@ properties:
- enum:
- mediatek,mt7622-rng
- mediatek,mt7629-rng
+ - mediatek,mt7986-rng
- mediatek,mt8365-rng
- mediatek,mt8516-rng
- const: mediatek,mt7623-rng
--
2.29.2

2021-07-26 07:18:20

by Sam Shih

[permalink] [raw]
Subject: [PATCH 05/12] dt-bindings: pinctrl: update bindings for MT7986 SoC

This updates bindings for MT7986 pinctrl driver.
The difference of pinctrl between mt7986a and mt7986b
is that pin-41 to pin-65 do not exist on mt7986b

Signed-off-by: Sam Shih <[email protected]>
---
.../bindings/pinctrl/pinctrl-mt7622.txt | 284 ++++++++++++++++++
1 file changed, 284 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
index 7a7aca1ed705..3c42eaad7a5e 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt
@@ -4,6 +4,8 @@ Required properties for the root node:
- compatible: Should be one of the following
"mediatek,mt7622-pinctrl" for MT7622 SoC
"mediatek,mt7629-pinctrl" for MT7629 SoC
+ "mediatek,mt7986a-pinctrl" for MT7986a SoC
+ "mediatek,mt7986b-pinctrl" for MT7986b SoC
- reg: offset and length of the pinctrl space

- gpio-controller: Marks the device node as a GPIO controller.
@@ -455,6 +457,288 @@ Valid values for groups are:
"wf0_5g" "wifi" 0, 1, 2, 3, 4, 5, 6,
7, 8, 9, 10

+== Valid values for pins, function and groups on MT7986a ==
+
+Valid values for pins are:
+pins can be referenced via the pin names as the below table shown and the
+related physical number is also put ahead of those names which helps cross
+references to pins between groups to know whether pins assignment conflict
+happens among devices try to acquire those available pins.
+
+ Pin #: Valid values for pins
+ -----------------------------
+ PIN 0: "SYS_WATCHDOG"
+ PIN 1: "WF2G_LED"
+ PIN 2: "WF5G_LED"
+ PIN 3: "I2C_SCL"
+ PIN 4: "I2C_SDA"
+ PIN 5: "GPIO_0"
+ PIN 6: "GPIO_1"
+ PIN 7: "GPIO_2"
+ PIN 8: "GPIO_3"
+ PIN 9: "GPIO_4"
+ PIN 10: "GPIO_5"
+ PIN 11: "GPIO_6"
+ PIN 12: "GPIO_7"
+ PIN 13: "GPIO_8"
+ PIN 14: "GPIO_9"
+ PIN 15: "GPIO_10"
+ PIN 16: "GPIO_11"
+ PIN 17: "GPIO_12"
+ PIN 18: "GPIO_13"
+ PIN 19: "GPIO_14"
+ PIN 20: "GPIO_15"
+ PIN 21: "PWM0"
+ PIN 22: "PWM1"
+ PIN 23: "SPI0_CLK"
+ PIN 24: "SPI0_MOSI"
+ PIN 25: "SPI0_MISO"
+ PIN 26: "SPI0_CS"
+ PIN 27: "SPI0_HOLD"
+ PIN 28: "SPI0_WP"
+ PIN 29: "SPI1_CLK"
+ PIN 30: "SPI1_MOSI"
+ PIN 31: "SPI1_MISO"
+ PIN 32: "SPI1_CS"
+ PIN 33: "SPI2_CLK"
+ PIN 34: "SPI2_MOSI"
+ PIN 35: "SPI2_MISO"
+ PIN 36: "SPI2_CS"
+ PIN 37: "SPI2_HOLD"
+ PIN 38: "SPI2_WP"
+ PIN 39: "UART0_RXD"
+ PIN 40: "UART0_TXD"
+ PIN 41: "PCIE_PERESET_N"
+ PIN 42: "UART1_RXD"
+ PIN 43: "UART1_TXD"
+ PIN 44: "UART1_CTS"
+ PIN 45: "UART1_RTS"
+ PIN 46: "UART2_RXD"
+ PIN 47: "UART2_TXD"
+ PIN 48: "UART2_CTS"
+ PIN 49: "UART2_RTS"
+ PIN 50: "EMMC_DATA_0"
+ PIN 51: "EMMC_DATA_1"
+ PIN 52: "EMMC_DATA_2"
+ PIN 53: "EMMC_DATA_3"
+ PIN 54: "EMMC_DATA_4"
+ PIN 55: "EMMC_DATA_5"
+ PIN 56: "EMMC_DATA_6"
+ PIN 57: "EMMC_DATA_7"
+ PIN 58: "EMMC_CMD"
+ PIN 59: "EMMC_CK"
+ PIN 60: "EMMC_DSL"
+ PIN 61: "EMMC_RSTB"
+ PIN 62: "PCM_DTX"
+ PIN 63: "PCM_DRX"
+ PIN 64: "PCM_CLK"
+ PIN 65: "PCM_FS"
+ PIN 66: "MT7531_INT"
+ PIN 67: "SMI_MDC"
+ PIN 68: "SMI_MDIO"
+ PIN 69: "WF0_DIG_RESETB"
+ PIN 70: "WF0_CBA_RESETB"
+ PIN 71: "WF0_XO_REQ"
+ PIN 72: "WF0_TOP_CLK"
+ PIN 73: "WF0_TOP_DATA"
+ PIN 74: "WF0_HB1"
+ PIN 75: "WF0_HB2"
+ PIN 76: "WF0_HB3"
+ PIN 77: "WF0_HB4"
+ PIN 78: "WF0_HB0"
+ PIN 79: "WF0_HB0_B"
+ PIN 80: "WF0_HB5"
+ PIN 81: "WF0_HB6"
+ PIN 82: "WF0_HB7"
+ PIN 83: "WF0_HB8"
+ PIN 84: "WF0_HB9"
+ PIN 85: "WF0_HB10"
+ PIN 86: "WF1_DIG_RESETB"
+ PIN 87: "WF1_CBA_RESETB"
+ PIN 88: "WF1_XO_REQ"
+ PIN 89: "WF1_TOP_CLK"
+ PIN 90: "WF1_TOP_DATA"
+ PIN 91: "WF1_HB1"
+ PIN 92: "WF1_HB2"
+ PIN 93: "WF1_HB3"
+ PIN 94: "WF1_HB4"
+ PIN 95: "WF1_HB0"
+ PIN 96: "WF1_HB0_B"
+ PIN 97: "WF1_HB5"
+ PIN 98: "WF1_HB6"
+ PIN 99: "WF1_HB7"
+ PIN 100: "WF1_HB8"
+
+Valid values for function are:
+ "audio, "emmc", "eth", "i2c", "wifi", "led", "flash", "pcie",
+ "pwm", "spi", "uart", "watchdog"
+
+Valid values for groups are:
+additional data is put followingly with valid value allowing us to know which
+applicable function and which relevant pins (in pin#) are able applied for that
+group.
+
+ Valid value function pins (in pin#)
+ -------------------------------------------------------------------------
+ "watchdog" "watchdog" 0
+ "wifi_led" "led" 1, 2
+ "i2c" "i2c" 3, 4
+ "uart1_0" "uart" 7, 8, 9, 10
+ "pcie_clk" "pcie" 9
+ "pcie_wake" "pcie" 10
+ "spi1_0" "spi" 11, 12, 13, 14
+ "pwm1_1" "pwm" 20,
+ "pwm0" "pwm" 21,
+ "pwm1_0" "pwm" 22,
+ "snfi" "flash" 23, 24, 25, 26, 27, 28
+ "spi1_2" "spi" 29, 30, 31, 32
+ "emmc_45" "emmc" 22, 23, 24, 25, 26, 27,
+ 28, 29, 30, 31, 32
+ "spi1_1" "spi" 23, 24, 25, 26
+ "uart1_2" "uart" 29, 30, 31, 32
+ "uart1_1" "uart" 23, 24, 25, 26
+ "uart2_0" "uart" 29, 30, 31, 32
+ "spi0" "spi" 33, 34, 35, 36
+ "spi0_wp_hold" "spi" 37, 38
+ "uart1_3_rx_tx" "uart" 35, 36
+ "uart1_3_cts_rts" "uart" 37, 38
+ "uart2_1" "uart" 33, 34, 35, 36
+ "spi1_3" "spi" 33, 34, 35, 36
+ "uart0" "uart" 39, 40
+ "pcie_pereset" "pcie" 41
+ "uart1" "uart" 42, 43, 44, 45
+ "uart2" "uart" 46, 47, 48, 49
+ "emmc_51" "emmc" 50, 51, 52, 53, 54, 55,
+ 56, 57, 57, 59, 60, 61
+ "pcm" "audio" 62, 63, 64, 65
+ "i2s" "audio" 62, 63, 64, 65
+ "switch_int" "eth" 66
+ "mdc_mdio" "eth" 67
+
+== Valid values for pins, function and groups on MT7986b ==
+
+Valid values for pins are:
+pins can be referenced via the pin names as the below table shown and the
+related physical number is also put ahead of those names which helps cross
+references to pins between groups to know whether pins assignment conflict
+happens among devices try to acquire those available pins.
+
+ Pin #: Valid values for pins
+ -----------------------------
+ PIN 0: "SYS_WATCHDOG"
+ PIN 1: "WF2G_LED"
+ PIN 2: "WF5G_LED"
+ PIN 3: "I2C_SCL"
+ PIN 4: "I2C_SDA"
+ PIN 5: "GPIO_0"
+ PIN 6: "GPIO_1"
+ PIN 7: "GPIO_2"
+ PIN 8: "GPIO_3"
+ PIN 9: "GPIO_4"
+ PIN 10: "GPIO_5"
+ PIN 11: "GPIO_6"
+ PIN 12: "GPIO_7"
+ PIN 13: "GPIO_8"
+ PIN 14: "GPIO_9"
+ PIN 15: "GPIO_10"
+ PIN 16: "GPIO_11"
+ PIN 17: "GPIO_12"
+ PIN 18: "GPIO_13"
+ PIN 19: "GPIO_14"
+ PIN 20: "GPIO_15"
+ PIN 21: "PWM0"
+ PIN 22: "PWM1"
+ PIN 23: "SPI0_CLK"
+ PIN 24: "SPI0_MOSI"
+ PIN 25: "SPI0_MISO"
+ PIN 26: "SPI0_CS"
+ PIN 27: "SPI0_HOLD"
+ PIN 28: "SPI0_WP"
+ PIN 29: "SPI1_CLK"
+ PIN 30: "SPI1_MOSI"
+ PIN 31: "SPI1_MISO"
+ PIN 32: "SPI1_CS"
+ PIN 33: "SPI2_CLK"
+ PIN 34: "SPI2_MOSI"
+ PIN 35: "SPI2_MISO"
+ PIN 36: "SPI2_CS"
+ PIN 37: "SPI2_HOLD"
+ PIN 38: "SPI2_WP"
+ PIN 39: "UART0_RXD"
+ PIN 40: "UART0_TXD"
+ PIN 66: "MT7531_INT"
+ PIN 67: "SMI_MDC"
+ PIN 68: "SMI_MDIO"
+ PIN 69: "WF0_DIG_RESETB"
+ PIN 70: "WF0_CBA_RESETB"
+ PIN 71: "WF0_XO_REQ"
+ PIN 72: "WF0_TOP_CLK"
+ PIN 73: "WF0_TOP_DATA"
+ PIN 74: "WF0_HB1"
+ PIN 75: "WF0_HB2"
+ PIN 76: "WF0_HB3"
+ PIN 77: "WF0_HB4"
+ PIN 78: "WF0_HB0"
+ PIN 79: "WF0_HB0_B"
+ PIN 80: "WF0_HB5"
+ PIN 81: "WF0_HB6"
+ PIN 82: "WF0_HB7"
+ PIN 83: "WF0_HB8"
+ PIN 84: "WF0_HB9"
+ PIN 85: "WF0_HB10"
+ PIN 86: "WF1_DIG_RESETB"
+ PIN 87: "WF1_CBA_RESETB"
+ PIN 88: "WF1_XO_REQ"
+ PIN 89: "WF1_TOP_CLK"
+ PIN 90: "WF1_TOP_DATA"
+ PIN 91: "WF1_HB1"
+ PIN 92: "WF1_HB2"
+ PIN 93: "WF1_HB3"
+ PIN 94: "WF1_HB4"
+ PIN 95: "WF1_HB0"
+ PIN 96: "WF1_HB0_B"
+ PIN 97: "WF1_HB5"
+ PIN 98: "WF1_HB6"
+ PIN 99: "WF1_HB7"
+ PIN 100: "WF1_HB8"
+
+Valid values for function are:
+ "emmc", "eth", "i2c", "wifi", "led", "flash", "pwm", "spi",
+ "uart", "watchdog"
+
+Valid values for groups are:
+additional data is put followingly with valid value allowing us to know which
+applicable function and which relevant pins (in pin#) are able applied for that
+group.
+
+ Valid value function pins (in pin#)
+ -------------------------------------------------------------------------
+ "watchdog" "watchdog" 0
+ "wifi_led" "led" 1, 2
+ "i2c" "i2c" 3, 4
+ "uart1_0" "uart" 7, 8, 9, 10
+ "spi1_0" "spi" 11, 12, 13, 14
+ "pwm1_1" "pwm" 20,
+ "pwm0" "pwm" 21,
+ "pwm1_0" "pwm" 22,
+ "snfi" "flash" 23, 24, 25, 26, 27, 28
+ "spi1_2" "spi" 29, 30, 31, 32
+ "emmc_45" "emmc" 22, 23, 24, 25, 26, 27,
+ 28, 29, 30, 31, 32
+ "spi1_1" "spi" 23, 24, 25, 26
+ "uart1_2" "uart" 29, 30, 31, 32
+ "uart1_1" "uart" 23, 24, 25, 26
+ "uart2_0" "uart" 29, 30, 31, 32
+ "spi0" "spi" 33, 34, 35, 36
+ "spi0_wp_hold" "spi" 37, 38
+ "uart1_3_rx_tx" "uart" 35, 36
+ "uart1_3_cts_rts" "uart" 37, 38
+ "uart2_1" "uart" 33, 34, 35, 36
+ "spi1_3" "spi" 33, 34, 35, 36
+ "switch_int" "eth" 66
+ "mdc_mdio" "eth" 67
+
+
Example:

pio: [email protected] {
--
2.29.2

2021-07-26 07:18:26

by Sam Shih

[permalink] [raw]
Subject: [PATCH 09/12] dt-bindings: serial: Add compatible for Mediatek MT7986

This commit adds dt-binding documentation of uart for Mediatek MT7986 SoC
Platform.

Signed-off-by: Sam Shih <[email protected]>
---
Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
index 64c4fb59acd1..b3a0bfef0d54 100644
--- a/Documentation/devicetree/bindings/serial/mtk-uart.txt
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -15,6 +15,7 @@ Required properties:
* "mediatek,mt7622-uart" for MT7622 compatible UARTS
* "mediatek,mt7623-uart" for MT7623 compatible UARTS
* "mediatek,mt7629-uart" for MT7629 compatible UARTS
+ * "mediatek,mt7986-uart", "mediatek,mt6577-uart" for MT7986 compatible UARTS
* "mediatek,mt8127-uart" for MT8127 compatible UARTS
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
--
2.29.2

2021-07-26 07:18:35

by Sam Shih

[permalink] [raw]
Subject: [PATCH 10/12] dt-bindings: watchdog: Add compatible for Mediatek MT7986

This commit adds dt-binding documentation of watchdog for Mediatek MT7986
SoC Platform.

Signed-off-by: Sam Shih <[email protected]>
---
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 416d716403f6..a4e31ce96e0e 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -13,6 +13,7 @@ Required properties:
"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
"mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
+ "mediatek,mt7986-wdt", "mediatek,mt6589-wdt": for MT7986
"mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
"mediatek,mt8192-wdt": for MT8192
--
2.29.2

2021-07-26 07:18:50

by Sam Shih

[permalink] [raw]
Subject: [PATCH 12/12] arm64: dts: mediatek: add mt7986b support

Add basic chip support for Mediatek mt7986b, include
uart nodes with correct clocks, rng node with correct clock,
watchdog node and mt7986b pinctrl node.

Add cpu node, timer node, gic node, psci and reserved-memory node
for ARM Trusted Firmware,

Add clock controller nodes, include 40M clock source, topckgen, infracfg,
infracfg_ao (always on), apmixedsys and ethernet subsystem.

Signed-off-by: Sam Shih <[email protected]>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 21 ++
arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 235 +++++++++++++++++++
3 files changed, 257 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt7986b.dtsi

diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index e6c3a73b9e4a..d555e43d1ccc 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
new file mode 100644
index 000000000000..8296f1d27e77
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Sam.Shih <[email protected]>
+ */
+
+/dts-v1/;
+#include "mt7986b.dtsi"
+
+/ {
+ model = "MediaTek MT7986b RFB";
+ compatible = "mediatek,mt7986b-rfb";
+ chosen {
+ bootargs = "console=ttyS0,115200n1 loglevel=8 \
+ earlycon=uart8250,mmio32,0x11002000";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
new file mode 100644
index 000000000000..4b001729b50e
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Sam.Shih <[email protected]>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt7986-clk.h>
+
+/ {
+ compatible = "mediatek,mt7986b";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clk40m: [email protected] {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <40000000>;
+ clock-output-names = "clkxtal";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu0: [email protected] {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: [email protected] {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2: [email protected] {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x2>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3: [email protected] {
+ device_type = "cpu";
+ enable-method = "psci";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: [email protected] {
+ reg = <0 0x43000000 0 0x30000>;
+ no-map;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ clock-frequency = <13000000>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: [email protected] {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>,
+ <0 0x0c080000 0 0x200000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ infracfg_ao: [email protected] {
+ compatible = "mediatek,mt7986-infracfg_ao", "syscon";
+ reg = <0 0x10001000 0 0x68>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: [email protected] {
+ compatible = "mediatek,mt7986-infracfg", "syscon";
+ reg = <0 0x1000106c 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen: [email protected] {
+ compatible = "mediatek,mt7986-topckgen", "syscon";
+ reg = <0 0x1001B000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ watchdog: [email protected] {
+ compatible = "mediatek,mt7986-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x1001c000 0 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ status = "disabled";
+ };
+
+ apmixedsys: [email protected] {
+ compatible = "mediatek,mt7986-apmixedsys";
+ reg = <0 0x1001E000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pio: [email protected] {
+ compatible = "mediatek,mt7986b-pinctrl";
+ reg = <0 0x1001f000 0 0x1000>,
+ <0 0x11c30000 0 0x1000>,
+ <0 0x11c40000 0 0x1000>,
+ <0 0x11e20000 0 0x1000>,
+ <0 0x11e30000 0 0x1000>,
+ <0 0x11f00000 0 0x1000>,
+ <0 0x11f10000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base",
+ "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base",
+ "iocfg_tl_base", "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 41>, <&pio 66 66 35>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ };
+
+ sgmiisys0: [email protected] {
+ compatible = "mediatek,mt7986-sgmiisys",
+ "mediatek,mt7986-sgmiisys_0",
+ "syscon";
+ reg = <0 0x10060000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sgmiisys1: [email protected] {
+ compatible = "mediatek,mt7986-sgmiisys",
+ "mediatek,mt7986-sgmiisys_1",
+ "syscon";
+ reg = <0 0x10070000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ trng: [email protected] {
+ compatible = "mediatek,mt7986-rng",
+ "mediatek,mt7623-rng";
+ reg = <0 0x1020f000 0 0x100>;
+ clocks = <&infracfg_ao CK_INFRA_TRNG_CK>;
+ clock-names = "rng";
+ status = "disabled";
+ };
+
+ uart0: [email protected] {
+ compatible = "mediatek,mt7986-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg_ao CK_INFRA_UART0_SEL>,
+ <&infracfg_ao CK_INFRA_UART0_CK>;
+ clock-names = "baud", "bus";
+ assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
+ <&infracfg_ao CK_INFRA_UART0_SEL>;
+ assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
+ <&infracfg CK_INFRA_UART>;
+ status = "disabled";
+ };
+
+ uart1: [email protected] {
+ compatible = "mediatek,mt7986-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg_ao CK_INFRA_UART1_SEL>,
+ <&infracfg_ao CK_INFRA_UART1_CK>;
+ clock-names = "baud", "bus";
+ assigned-clocks = <&infracfg_ao CK_INFRA_UART1_SEL>;
+ assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
+ status = "disabled";
+ };
+
+ uart2: [email protected] {
+ compatible = "mediatek,mt7986-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x400>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg_ao CK_INFRA_UART2_SEL>,
+ <&infracfg_ao CK_INFRA_UART2_CK>;
+ clock-names = "baud", "bus";
+ assigned-clocks = <&infracfg_ao CK_INFRA_UART2_SEL>;
+ assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
+ status = "disabled";
+ };
+
+ ethsys: [email protected] {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mediatek,mt7986-ethsys",
+ "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ };
+
+};
--
2.29.2

2021-07-26 09:20:56

by Chen-Yu Tsai

[permalink] [raw]
Subject: Re: [PATCH 01/12] dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC

On Mon, Jul 26, 2021 at 3:17 PM Sam Shih <[email protected]> wrote:
>
> This patch adds the binding documentation for topckgen, apmixedsys,
> infracfg, infracfg_ao, and ethernet subsystem clocks.
>
> Signed-off-by: Sam Shih <[email protected]>
> ---
> .../devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 +
> .../devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
> .../devicetree/bindings/arm/mediatek/mediatek,infracfg.txt | 2 ++
> .../devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt | 2 ++
> .../devicetree/bindings/arm/mediatek/mediatek,topckgen.txt | 1 +
> 5 files changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
> index ea827e8763de..3fa755866528 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
> @@ -14,6 +14,7 @@ Required Properties:
> - "mediatek,mt7622-apmixedsys"
> - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
> - "mediatek,mt7629-apmixedsys"
> + - "mediatek,mt7986-apmixedsys"
> - "mediatek,mt8135-apmixedsys"
> - "mediatek,mt8167-apmixedsys", "syscon"
> - "mediatek,mt8173-apmixedsys"
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> index 6b7e8067e7aa..0502db73686b 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> @@ -10,6 +10,7 @@ Required Properties:
> - "mediatek,mt7622-ethsys", "syscon"
> - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
> - "mediatek,mt7629-ethsys", "syscon"
> + - "mediatek,mt7986-ethsys", "syscon"
> - #clock-cells: Must be 1
> - #reset-cells: Must be 1
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
> index eb3523c7a7be..5f68c30162bf 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
> @@ -15,6 +15,8 @@ Required Properties:
> - "mediatek,mt7622-infracfg", "syscon"
> - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
> - "mediatek,mt7629-infracfg", "syscon"
> + - "mediatek,mt7986-infracfg", "syscon"
> + - "mediatek,mt7986-infracfg_ao", "syscon"
> - "mediatek,mt8135-infracfg", "syscon"
> - "mediatek,mt8167-infracfg", "syscon"
> - "mediatek,mt8173-infracfg", "syscon"
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
> index 30cb645c0e54..0e1184392941 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
> @@ -8,6 +8,8 @@ Required Properties:
> - compatible: Should be:
> - "mediatek,mt7622-sgmiisys", "syscon"
> - "mediatek,mt7629-sgmiisys", "syscon"
> + - "mediatek,mt7986-sgmiisys", "mediatek,mt7986-sgmiisys_0", "syscon"
> + - "mediatek,mt7986-sgmiisys", "mediatek,mt7986-sgmiisys_1", "syscon"

The order should be: most specific compatible string first, followed by
fallbacks.

Furthermore, based on the driver patch and the fact that they share the
same compatible string, it seems you shouldn't need to have two compatible
strings for two identical hardware blocks. The need for separate entries
to have different clock names is an implementation detail. Please consider
using and supporting clock-output-names.

Also, please check out the MT8195 clock driver series [1]. I'm guessing
a lot of the comments apply to this one as well.

Regards
ChenYu

[1] https://lore.kernel.org/linux-mediatek/[email protected]/T/#t


> - #clock-cells: Must be 1
>
> The SGMIISYS controller uses the common clk binding from
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
> index 5ce7578cf274..b82422bb717f 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
> @@ -14,6 +14,7 @@ Required Properties:
> - "mediatek,mt7622-topckgen"
> - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
> - "mediatek,mt7629-topckgen"
> + - "mediatek,mt7986-topckgen", "syscon"
> - "mediatek,mt8135-topckgen"
> - "mediatek,mt8167-topckgen", "syscon"
> - "mediatek,mt8173-topckgen"
> --
> 2.29.2
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek