The series contains Qualcomm Crypto Engine DT bindings documentation and
driver changes, which modify a set of accepted compatible property values,
which is needed to provide a unified and fine-grained support of the driver
on old and new platforms. In addition due to QCE IP changes on new Qualcomm
platforms, it is reflected in updates to valid device tree properties,
namely added iommu, interconnects and optional clocks.
Qualcomm crypto engine (QCE) is available on several Snapdragon SoCs.
The QCE block supports hardware accelerated algorithms for encryption
and authentication. It also provides support for aes, des, 3des
encryption algorithms and sha1, sha256, hmac(sha1), hmac(sha256)
authentication algorithms.
Changes since v10:
=================
- v10 can be found here: https://lore.kernel.org/all/[email protected]/
- Fixed 05/10 commit message per request from Krzysztof and added his
reviewed-by tag.
- Rebased the series on top of the linux-next.
Changes since v9:
=================
- v9 can be found here: https://lore.kernel.org/linux-crypto/[email protected]/
- Added a new generic 'qcom,qce' compatible name, since IP is runtime
discoverable, however two new SoC name based compatibles are left
due to necessity to differentiate various lists of required properties.
- Updated documentation according to review comments by Krzysztof.
- Removed platform specific changes in dtsi files, only one bisectable
change in sm8550.dtsi is left in the series.
- Added some commit tags, however a few given tags by Krzysztof are not
added, since the previous tagged changes were noticeably reworked.
Changes since v8:
=================
- v8 can be found here: https://lore.kernel.org/all/[email protected]/
- Rebased the series on top of linux-next, sm8550 qce support is already
found in the tree.
- Reduced the list of QCE IP compatibles in the driver, added one more
compatible for backward DTB ABI compatibility.
- Replaced a documentation change from Neil Armstrong by a more advanced
version of it per review comments from Krzysztof Kozlowski about clock
and clock-names properties.
- Added changes to all relevant Qualcomm platform dtsi files according to
the changes in the scheme file.
- Added QCE support on SM8250 platform.
Changes since v7:
=================
- v7 can be found here: https://lore.kernel.org/linux-arm-msm/[email protected]
- Added a change by Neil Armstrong to document clocks and clock-names
properties as optional,
- At the moment do not add Bhupesh as a new QCE driver maintainer,
- Minor updates to device tree binding documentation and qce driver,
in particular added more compatibles and fixed lesser issues.
Changes since v6:
=================
- v6 can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- As per Krzysztof's suggestion on v6, clubbed the crypto driver and
dt-bindings changes together. Now the overall v5 patchset into 3
separate patchsets, one each for the following areas to allow easier
review and handling from the maintainer: arm-msm, crypto and dma
Changes since v5:
=================
- v5 can be seen here: https://lore.kernel.org/lkml/[email protected]/
- As per Bjorn's suggestion on irc, broke down the patchset into 4
separate patchsets, one each for the following areas to allow easier
review and handling from the maintainer: arm-msm, crypto, dma and devicetree
- Addressed Rob's, Vladimir's and Bjorn's review comments received on v5.
- Added Tested-by from Jordan received on the v5.
Changes since v4:
=================
- v4 for sm8250 can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- v1 for sm8150 qce enablement can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- Merged the sm8150 and sm8250 enablement patches in the same patchset,
as per suggestions from Bjorn.
- Dropped a couple of patches from v4, as these have been picked by
Bjorn already via his tree.
- Addressed review comments from Vladimir, Thara and Rob.
- Collect Reviewed-by from Rob and Thara on some of the patches from the
v4 patchset.
Changes since v3:
=================
- v3 can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- Dropped a couple of patches from v3, on basis of the review comments:
~ [PATCH 13/17] crypto: qce: core: Make clocks optional
~ [PATCH 15/17] crypto: qce: Convert the device found dev_dbg() to dev_info()
- Addressed review comments from Thara, Rob and Stephan Gerhold.
- Collect Reviewed-by from Rob and Thara on some of the patches from the
v3 patchset.
Changes since v2:
=================
- v2 can be seen here: https://lore.kernel.org/dmaengine/[email protected]/
- Drop a couple of patches from v1, which tried to address the defered
probing of qce driver in case bam dma driver is not yet probed.
Replace it instead with a single (simpler) patch [PATCH 16/17].
- Convert bam dma and qce crypto dt-bindings to YAML.
- Addressed review comments from Thara, Bjorn, Vinod and Rob.
Changes since v1:
=================
- v1 can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
- v1 did not work well as reported earlier by Dmitry, so v2 contains the following
changes/fixes:
~ Enable the interconnect path b/w BAM DMA and main memory first
before trying to access the BAM DMA registers.
~ Enable the interconnect path b/w qce crytpo and main memory first
before trying to access the qce crypto registers.
~ Make sure to document the required and optional properties for both
BAM DMA and qce crypto drivers.
~ Add a few debug related print messages in case the qce crypto driver
passes or fails to probe.
~ Convert the qce crypto driver probe to a defered one in case the BAM DMA
or the interconnect driver(s) (needed on specific Qualcomm parts) are not
yet probed.
Bhupesh Sharma (4):
dt-bindings: qcom-qce: Convert bindings to yaml
MAINTAINERS: Add qcom-qce dt-binding file to QUALCOMM CRYPTO DRIVERS section
dt-bindings: qcom-qce: Add 'interconnects' and 'interconnect-names'
dt-bindings: qcom-qce: Add 'iommus' to optional properties
Thara Gopinath (2):
crypto: qce: core: Add support to initialize interconnect path
crypto: qce: core: Make clocks optional
Vladimir Zapolskiy (4):
dt-bindings: qcom-qce: Add new SoC compatible strings for Qualcomm QCE IP
dt-bindings: qcom-qce: document optional clocks and clock-names properties
arm64: dts: qcom: sm8550: add QCE IP family compatible values
crypto: qce: core: Add a QCE IP family compatible 'qcom,qce'
.../devicetree/bindings/crypto/qcom-qce.txt | 25 ----
.../devicetree/bindings/crypto/qcom-qce.yaml | 123 ++++++++++++++++++
MAINTAINERS | 1 +
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
drivers/crypto/qce/core.c | 23 +++-
drivers/crypto/qce/core.h | 1 +
6 files changed, 145 insertions(+), 30 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.txt
create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml
--
2.33.0
From: Bhupesh Sharma <[email protected]>
Convert Qualcomm QCE crypto devicetree binding to YAML.
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Tested-by: Jordan Crouse <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
.../devicetree/bindings/crypto/qcom-qce.txt | 25 -------
.../devicetree/bindings/crypto/qcom-qce.yaml | 67 +++++++++++++++++++
2 files changed, 67 insertions(+), 25 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.txt
create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
deleted file mode 100644
index fdd53b184ba8..000000000000
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Qualcomm crypto engine driver
-
-Required properties:
-
-- compatible : should be "qcom,crypto-v5.1"
-- reg : specifies base physical address and size of the registers map
-- clocks : phandle to clock-controller plus clock-specifier pair
-- clock-names : "iface" clocks register interface
- "bus" clocks data transfer interface
- "core" clocks rest of the crypto block
-- dmas : DMA specifiers for tx and rx dma channels. For more see
- Documentation/devicetree/bindings/dma/dma.txt
-- dma-names : DMA request names should be "rx" and "tx"
-
-Example:
- crypto@fd45a000 {
- compatible = "qcom,crypto-v5.1";
- reg = <0xfd45a000 0x6000>;
- clocks = <&gcc GCC_CE2_AHB_CLK>,
- <&gcc GCC_CE2_AXI_CLK>,
- <&gcc GCC_CE2_CLK>;
- clock-names = "iface", "bus", "core";
- dmas = <&cryptobam 2>, <&cryptobam 3>;
- dma-names = "rx", "tx";
- };
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
new file mode 100644
index 000000000000..8df47e8513b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm crypto engine driver
+
+maintainers:
+ - Bhupesh Sharma <[email protected]>
+
+description:
+ This document defines the binding for the QCE crypto
+ controller found on Qualcomm parts.
+
+properties:
+ compatible:
+ const: qcom,crypto-v5.1
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: iface clocks register interface.
+ - description: bus clocks data transfer interface.
+ - description: core clocks rest of the crypto block.
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ dmas:
+ items:
+ - description: DMA specifiers for rx dma channel.
+ - description: DMA specifiers for tx dma channel.
+
+ dma-names:
+ items:
+ - const: rx
+ - const: tx
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - dmas
+ - dma-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-apq8084.h>
+ crypto-engine@fd45a000 {
+ compatible = "qcom,crypto-v5.1";
+ reg = <0xfd45a000 0x6000>;
+ clocks = <&gcc GCC_CE2_AHB_CLK>,
+ <&gcc GCC_CE2_AXI_CLK>,
+ <&gcc GCC_CE2_CLK>;
+ clock-names = "iface", "bus", "core";
+ dmas = <&cryptobam 2>, <&cryptobam 3>;
+ dma-names = "rx", "tx";
+ };
--
2.33.0
From: Bhupesh Sharma <[email protected]>
Add 'interconnects' and 'interconnect-names' as optional properties
to the device-tree binding documentation for Qualcomm crypto IP.
These properties describe the interconnect path between crypto and main
memory and the interconnect type respectively.
Cc: Bjorn Andersson <[email protected]>
Acked-by: Rob Herring <[email protected]>
Tested-by: Jordan Crouse <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index 8df47e8513b8..94f96ebc5dac 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -32,6 +32,14 @@ properties:
- const: bus
- const: core
+ interconnects:
+ maxItems: 1
+ description:
+ Interconnect path between qce crypto and main memory.
+
+ interconnect-names:
+ const: memory
+
dmas:
items:
- description: DMA specifiers for rx dma channel.
--
2.33.0
From: Bhupesh Sharma <[email protected]>
Add the entry for 'Documentation/devicetree/bindings/crypto/qcom-qce.yaml'
to the appropriate section for 'QUALCOMM CRYPTO DRIVERS' in
MAINTAINERS file.
Reviewed-by: Bjorn Andersson <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b0db911207ba..0d54050f2f51 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17275,6 +17275,7 @@ M: Thara Gopinath <[email protected]>
L: [email protected]
L: [email protected]
S: Maintained
+F: Documentation/devicetree/bindings/crypto/qcom-qce.yaml
F: drivers/crypto/qce/
QUALCOMM EMAC GIGABIT ETHERNET DRIVER
--
2.33.0
From: Bhupesh Sharma <[email protected]>
Add the missing optional property - 'iommus' to the
device-tree binding documentation for qcom-qce crypto IP.
This property describes the phandle(s) to apps_smmu node with sid mask.
Cc: Bjorn Andersson <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Tested-by: Jordan Crouse <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
Documentation/devicetree/bindings/crypto/qcom-qce.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index 94f96ebc5dac..4e00e7925fed 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -32,6 +32,12 @@ properties:
- const: bus
- const: core
+ iommus:
+ minItems: 1
+ maxItems: 8
+ description:
+ phandle to apps_smmu node with sid mask.
+
interconnects:
maxItems: 1
description:
@@ -72,4 +78,8 @@ examples:
clock-names = "iface", "bus", "core";
dmas = <&cryptobam 2>, <&cryptobam 3>;
dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x584 0x0011>,
+ <&apps_smmu 0x586 0x0011>,
+ <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
};
--
2.33.0
Introduce a generic IP family compatible 'qcom,qce' and its two derivatives
based on SoC names rather than on IP versions. Having a generic compatible
is only partially sufficient, the QCE IP version can be discovered in
runtime, however there are two known groups of QCE IP versions, which
require different DT properties, these two groups are populated with SoC
based compatibles known at the moment.
Keep the old compatible 'qcom,crypto-v5.1' and document an existing and
already used but not previously documented compatible 'qcom,crypto-v5.4'
for backward compatibility of DTB ABI, mark both of the compatibles as
deprecated.
The change is based on the original one written by Bhupesh Sharma, adding
a generic family compatible is suggested by Neil Armstrong.
Cc: Bhupesh Sharma <[email protected]>
Cc: Neil Armstrong <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
.../devicetree/bindings/crypto/qcom-qce.yaml | 29 +++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index 4e00e7925fed..84f57f44bb71 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -15,7 +15,32 @@ description:
properties:
compatible:
- const: qcom,crypto-v5.1
+ oneOf:
+ - const: qcom,crypto-v5.1
+ deprecated: true
+ description: Kept only for ABI backward compatibility
+
+ - const: qcom,crypto-v5.4
+ deprecated: true
+ description: Kept only for ABI backward compatibility
+
+ - items:
+ - enum:
+ - qcom,ipq6018-qce
+ - qcom,ipq8074-qce
+ - qcom,msm8996-qce
+ - qcom,sdm845-qce
+ - const: qcom,ipq4019-qce
+ - const: qcom,qce
+
+ - items:
+ - enum:
+ - qcom,sm8250-qce
+ - qcom,sm8350-qce
+ - qcom,sm8450-qce
+ - qcom,sm8550-qce
+ - const: qcom,sm8150-qce
+ - const: qcom,qce
reg:
maxItems: 1
@@ -70,7 +95,7 @@ examples:
- |
#include <dt-bindings/clock/qcom,gcc-apq8084.h>
crypto-engine@fd45a000 {
- compatible = "qcom,crypto-v5.1";
+ compatible = "qcom,ipq6018-qce", "qcom,ipq4019-qce", "qcom,qce";
reg = <0xfd45a000 0x6000>;
clocks = <&gcc GCC_CE2_AHB_CLK>,
<&gcc GCC_CE2_AXI_CLK>,
--
2.33.0
On newer Qualcomm SoCs the crypto engine clocks are enabled by default
by security firmware. To drop clocks and clock-names from the list of
required properties use 'qcom,sm8150-qce' compatible name.
The change is based on Neil Armstrong's observation and an original change.
Cc: Neil Armstrong <[email protected]>
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
.../devicetree/bindings/crypto/qcom-qce.yaml | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
index 84f57f44bb71..e375bd981300 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml
@@ -81,11 +81,24 @@ properties:
- const: rx
- const: tx
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,crypto-v5.1
+ - qcom,crypto-v5.4
+ - qcom,ipq4019-qce
+
+ then:
+ required:
+ - clocks
+ - clock-names
+
required:
- compatible
- reg
- - clocks
- - clock-names
- dmas
- dma-names
--
2.33.0
Add a family compatible for QCE IP on SM8550 SoC, which is equal to QCE IP
found on SM8150 SoC and described in the recently updated device tree
bindings documentation, as well add a generic QCE IP family compatible.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index ff4d342c0725..05ab0d5014c6 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1861,7 +1861,7 @@ cryptobam: dma-controller@1dc4000 {
};
crypto: crypto@1de0000 {
- compatible = "qcom,sm8550-qce";
+ compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
reg = <0x0 0x01dfa000 0x0 0x6000>;
dmas = <&cryptobam 4>, <&cryptobam 5>;
dma-names = "rx", "tx";
--
2.33.0
From: Thara Gopinath <[email protected]>
Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350
etc. requires interconnect path between the engine and memory to be
explicitly enabled and bandwidth set prior to any operations. Add support
in the qce core to enable the interconnect path appropriately.
Tested-by: Jordan Crouse <[email protected]>
Signed-off-by: Thara Gopinath <[email protected]>
[Bhupesh: Make header file inclusion alphabetical and use devm_of_icc_get()]
Signed-off-by: Bhupesh Sharma <[email protected]>
[vladimir: moved icc bandwidth setup closer to its acquisition]
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
drivers/crypto/qce/core.c | 16 +++++++++++++++-
drivers/crypto/qce/core.h | 1 +
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 74deca4f96e0..0654b94cfb95 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -5,6 +5,7 @@
#include <linux/clk.h>
#include <linux/dma-mapping.h>
+#include <linux/interconnect.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
@@ -22,6 +23,8 @@
#define QCE_MAJOR_VERSION5 0x05
#define QCE_QUEUE_LENGTH 1
+#define QCE_DEFAULT_MEM_BANDWIDTH 393600
+
static const struct qce_algo_ops *qce_ops[] = {
#ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
&skcipher_ops,
@@ -218,10 +221,18 @@ static int qce_crypto_probe(struct platform_device *pdev)
if (IS_ERR(qce->bus))
return PTR_ERR(qce->bus);
- ret = clk_prepare_enable(qce->core);
+ qce->mem_path = devm_of_icc_get(qce->dev, "memory");
+ if (IS_ERR(qce->mem_path))
+ return PTR_ERR(qce->mem_path);
+
+ ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
if (ret)
return ret;
+ ret = clk_prepare_enable(qce->core);
+ if (ret)
+ goto err_mem_path_disable;
+
ret = clk_prepare_enable(qce->iface);
if (ret)
goto err_clks_core;
@@ -260,6 +271,9 @@ static int qce_crypto_probe(struct platform_device *pdev)
clk_disable_unprepare(qce->iface);
err_clks_core:
clk_disable_unprepare(qce->core);
+err_mem_path_disable:
+ icc_set_bw(qce->mem_path, 0, 0);
+
return ret;
}
diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h
index 085774cdf641..228fcd69ec51 100644
--- a/drivers/crypto/qce/core.h
+++ b/drivers/crypto/qce/core.h
@@ -35,6 +35,7 @@ struct qce_device {
void __iomem *base;
struct device *dev;
struct clk *core, *iface, *bus;
+ struct icc_path *mem_path;
struct qce_dma_data dma;
int burst_size;
unsigned int pipe_pair_id;
--
2.33.0
From: Thara Gopinath <[email protected]>
On certain Snapdragon processors, the crypto engine clocks are enabled by
default by security firmware and the driver should not handle the clocks.
Make acquiring of all the clocks optional in crypto engine driver, so that
the driver initializes properly even if no clocks are specified in the dt.
Tested-by: Jordan Crouse <[email protected]>
Signed-off-by: Thara Gopinath <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
[Bhupesh: Massage the commit log]
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
drivers/crypto/qce/core.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 0654b94cfb95..5bb2128c95ca 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -209,15 +209,15 @@ static int qce_crypto_probe(struct platform_device *pdev)
if (ret < 0)
return ret;
- qce->core = devm_clk_get(qce->dev, "core");
+ qce->core = devm_clk_get_optional(qce->dev, "core");
if (IS_ERR(qce->core))
return PTR_ERR(qce->core);
- qce->iface = devm_clk_get(qce->dev, "iface");
+ qce->iface = devm_clk_get_optional(qce->dev, "iface");
if (IS_ERR(qce->iface))
return PTR_ERR(qce->iface);
- qce->bus = devm_clk_get(qce->dev, "bus");
+ qce->bus = devm_clk_get_optional(qce->dev, "bus");
if (IS_ERR(qce->bus))
return PTR_ERR(qce->bus);
--
2.33.0
The added 'qcom,qce' compatible value will serve as a sole QCE IP family
compatible, since a particular QCE IP version is discoverablem thus, if
it'd be needed to differentiate various IP versions, it can be obtained
in runtime.
Two IP version based compatibles are left untouched to preserve backward
DTB ABI compatibility.
Signed-off-by: Vladimir Zapolskiy <[email protected]>
---
drivers/crypto/qce/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index 5bb2128c95ca..fce49c0dee3e 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -293,6 +293,7 @@ static int qce_crypto_remove(struct platform_device *pdev)
static const struct of_device_id qce_crypto_of_match[] = {
{ .compatible = "qcom,crypto-v5.1", },
{ .compatible = "qcom,crypto-v5.4", },
+ { .compatible = "qcom,qce", },
{}
};
MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
--
2.33.0
On 22.02.2023 18:22, Vladimir Zapolskiy wrote:
> From: Thara Gopinath <[email protected]>
>
> Crypto engine on certain Snapdragon processors like sm8150, sm8250, sm8350
> etc. requires interconnect path between the engine and memory to be
> explicitly enabled and bandwidth set prior to any operations. Add support
> in the qce core to enable the interconnect path appropriately.
>
> Tested-by: Jordan Crouse <[email protected]>
> Signed-off-by: Thara Gopinath <[email protected]>
> [Bhupesh: Make header file inclusion alphabetical and use devm_of_icc_get()]
> Signed-off-by: Bhupesh Sharma <[email protected]>
> [vladimir: moved icc bandwidth setup closer to its acquisition]
> Signed-off-by: Vladimir Zapolskiy <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> drivers/crypto/qce/core.c | 16 +++++++++++++++-
> drivers/crypto/qce/core.h | 1 +
> 2 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index 74deca4f96e0..0654b94cfb95 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -5,6 +5,7 @@
>
> #include <linux/clk.h>
> #include <linux/dma-mapping.h>
> +#include <linux/interconnect.h>
> #include <linux/interrupt.h>
> #include <linux/module.h>
> #include <linux/mod_devicetable.h>
> @@ -22,6 +23,8 @@
> #define QCE_MAJOR_VERSION5 0x05
> #define QCE_QUEUE_LENGTH 1
>
> +#define QCE_DEFAULT_MEM_BANDWIDTH 393600
> +
> static const struct qce_algo_ops *qce_ops[] = {
> #ifdef CONFIG_CRYPTO_DEV_QCE_SKCIPHER
> &skcipher_ops,
> @@ -218,10 +221,18 @@ static int qce_crypto_probe(struct platform_device *pdev)
> if (IS_ERR(qce->bus))
> return PTR_ERR(qce->bus);
>
> - ret = clk_prepare_enable(qce->core);
> + qce->mem_path = devm_of_icc_get(qce->dev, "memory");
> + if (IS_ERR(qce->mem_path))
> + return PTR_ERR(qce->mem_path);
> +
> + ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
> if (ret)
> return ret;
>
> + ret = clk_prepare_enable(qce->core);
> + if (ret)
> + goto err_mem_path_disable;
> +
> ret = clk_prepare_enable(qce->iface);
> if (ret)
> goto err_clks_core;
> @@ -260,6 +271,9 @@ static int qce_crypto_probe(struct platform_device *pdev)
> clk_disable_unprepare(qce->iface);
> err_clks_core:
> clk_disable_unprepare(qce->core);
> +err_mem_path_disable:
> + icc_set_bw(qce->mem_path, 0, 0);
> +
> return ret;
> }
>
> diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h
> index 085774cdf641..228fcd69ec51 100644
> --- a/drivers/crypto/qce/core.h
> +++ b/drivers/crypto/qce/core.h
> @@ -35,6 +35,7 @@ struct qce_device {
> void __iomem *base;
> struct device *dev;
> struct clk *core, *iface, *bus;
> + struct icc_path *mem_path;
> struct qce_dma_data dma;
> int burst_size;
> unsigned int pipe_pair_id;
On 22.02.2023 18:22, Vladimir Zapolskiy wrote:
> From: Thara Gopinath <[email protected]>
>
> On certain Snapdragon processors, the crypto engine clocks are enabled by
> default by security firmware and the driver should not handle the clocks.
> Make acquiring of all the clocks optional in crypto engine driver, so that
> the driver initializes properly even if no clocks are specified in the dt.
>
> Tested-by: Jordan Crouse <[email protected]>
> Signed-off-by: Thara Gopinath <[email protected]>
> Signed-off-by: Bhupesh Sharma <[email protected]>
> [Bhupesh: Massage the commit log]
> Signed-off-by: Vladimir Zapolskiy <[email protected]>
> ---
I'm not sure which is the preferred approach, but generally I'd
stick with keeping them non-optional for the SoCs that need them..
So perhaps introducing a flag in of_match_data for qcom,sm8150-qce
(which was created solely to take care of the no-HLOS-clocks cases)
and then skipping the clock operations based on that would be a
good idea.
Konrad
> drivers/crypto/qce/core.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index 0654b94cfb95..5bb2128c95ca 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -209,15 +209,15 @@ static int qce_crypto_probe(struct platform_device *pdev)
> if (ret < 0)
> return ret;
>
> - qce->core = devm_clk_get(qce->dev, "core");
> + qce->core = devm_clk_get_optional(qce->dev, "core");
> if (IS_ERR(qce->core))
> return PTR_ERR(qce->core);
>
> - qce->iface = devm_clk_get(qce->dev, "iface");
> + qce->iface = devm_clk_get_optional(qce->dev, "iface");
> if (IS_ERR(qce->iface))
> return PTR_ERR(qce->iface);
>
> - qce->bus = devm_clk_get(qce->dev, "bus");
> + qce->bus = devm_clk_get_optional(qce->dev, "bus");
> if (IS_ERR(qce->bus))
> return PTR_ERR(qce->bus);
>
On 22.02.2023 18:22, Vladimir Zapolskiy wrote:
> The added 'qcom,qce' compatible value will serve as a sole QCE IP family
> compatible, since a particular QCE IP version is discoverablem thus, if
> it'd be needed to differentiate various IP versions, it can be obtained
> in runtime.
>
> Two IP version based compatibles are left untouched to preserve backward
> DTB ABI compatibility.
>
> Signed-off-by: Vladimir Zapolskiy <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> drivers/crypto/qce/core.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
> index 5bb2128c95ca..fce49c0dee3e 100644
> --- a/drivers/crypto/qce/core.c
> +++ b/drivers/crypto/qce/core.c
> @@ -293,6 +293,7 @@ static int qce_crypto_remove(struct platform_device *pdev)
> static const struct of_device_id qce_crypto_of_match[] = {
> { .compatible = "qcom,crypto-v5.1", },
> { .compatible = "qcom,crypto-v5.4", },
> + { .compatible = "qcom,qce", },
> {}
> };
> MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
Hi Konrad,
On 2/22/23 19:33, Konrad Dybcio wrote:
>
>
> On 22.02.2023 18:22, Vladimir Zapolskiy wrote:
>> From: Thara Gopinath <[email protected]>
>>
>> On certain Snapdragon processors, the crypto engine clocks are enabled by
>> default by security firmware and the driver should not handle the clocks.
>> Make acquiring of all the clocks optional in crypto engine driver, so that
>> the driver initializes properly even if no clocks are specified in the dt.
>>
>> Tested-by: Jordan Crouse <[email protected]>
>> Signed-off-by: Thara Gopinath <[email protected]>
>> Signed-off-by: Bhupesh Sharma <[email protected]>
>> [Bhupesh: Massage the commit log]
>> Signed-off-by: Vladimir Zapolskiy <[email protected]>
>> ---
> I'm not sure which is the preferred approach, but generally I'd
> stick with keeping them non-optional for the SoCs that need them..
> So perhaps introducing a flag in of_match_data for qcom,sm8150-qce
> (which was created solely to take care of the no-HLOS-clocks cases)
> and then skipping the clock operations based on that would be a
> good idea.
thank you for review. As you can get it from 06/10 the task to distinguish
IPs with clocks and without clocks is offloaded to dtb. I believe a better
support of two cases should be added to the driver on the basis of QCE IP
versions obtained in runtime, or, alternatively and like you propose, it
can be taken from a compatible. IMHO the latter one is a weak improvement,
since it can be considered as a workaround in the driver to a known to be
broken device tree node.
--
Best wishes,
Vladimir
On 22/02/2023 18:22, Vladimir Zapolskiy wrote:
> On newer Qualcomm SoCs the crypto engine clocks are enabled by default
> by security firmware. To drop clocks and clock-names from the list of
> required properties use 'qcom,sm8150-qce' compatible name.
>
> The change is based on Neil Armstrong's observation and an original change.
>
> Cc: Neil Armstrong <[email protected]>
> Signed-off-by: Vladimir Zapolskiy <[email protected]>
> ---
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 22/02/2023 18:22, Vladimir Zapolskiy wrote:
> Add a family compatible for QCE IP on SM8550 SoC, which is equal to QCE IP
> found on SM8150 SoC and described in the recently updated device tree
> bindings documentation, as well add a generic QCE IP family compatible.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Vladimir Zapolskiy <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index ff4d342c0725..05ab0d5014c6 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1861,7 +1861,7 @@ cryptobam: dma-controller@1dc4000 {
> };
>
> crypto: crypto@1de0000 {
> - compatible = "qcom,sm8550-qce";
> + compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
> reg = <0x0 0x01dfa000 0x0 0x6000>;
> dmas = <&cryptobam 4>, <&cryptobam 5>;
> dma-names = "rx", "tx";
Reviewed-by: Neil Armstrong <[email protected]>
On Wed, Feb 22, 2023 at 07:22:30PM +0200, Vladimir Zapolskiy wrote:
> The series contains Qualcomm Crypto Engine DT bindings documentation and
> driver changes, which modify a set of accepted compatible property values,
> which is needed to provide a unified and fine-grained support of the driver
> on old and new platforms. In addition due to QCE IP changes on new Qualcomm
> platforms, it is reflected in updates to valid device tree properties,
> namely added iommu, interconnects and optional clocks.
>
> Qualcomm crypto engine (QCE) is available on several Snapdragon SoCs.
> The QCE block supports hardware accelerated algorithms for encryption
> and authentication. It also provides support for aes, des, 3des
> encryption algorithms and sha1, sha256, hmac(sha1), hmac(sha256)
> authentication algorithms.
>
> Changes since v10:
> =================
> - v10 can be found here: https://lore.kernel.org/all/[email protected]/
> - Fixed 05/10 commit message per request from Krzysztof and added his
> reviewed-by tag.
> - Rebased the series on top of the linux-next.
>
> Changes since v9:
> =================
> - v9 can be found here: https://lore.kernel.org/linux-crypto/[email protected]/
> - Added a new generic 'qcom,qce' compatible name, since IP is runtime
> discoverable, however two new SoC name based compatibles are left
> due to necessity to differentiate various lists of required properties.
> - Updated documentation according to review comments by Krzysztof.
> - Removed platform specific changes in dtsi files, only one bisectable
> change in sm8550.dtsi is left in the series.
> - Added some commit tags, however a few given tags by Krzysztof are not
> added, since the previous tagged changes were noticeably reworked.
>
> Changes since v8:
> =================
> - v8 can be found here: https://lore.kernel.org/all/[email protected]/
> - Rebased the series on top of linux-next, sm8550 qce support is already
> found in the tree.
> - Reduced the list of QCE IP compatibles in the driver, added one more
> compatible for backward DTB ABI compatibility.
> - Replaced a documentation change from Neil Armstrong by a more advanced
> version of it per review comments from Krzysztof Kozlowski about clock
> and clock-names properties.
> - Added changes to all relevant Qualcomm platform dtsi files according to
> the changes in the scheme file.
> - Added QCE support on SM8250 platform.
>
> Changes since v7:
> =================
> - v7 can be found here: https://lore.kernel.org/linux-arm-msm/[email protected]
> - Added a change by Neil Armstrong to document clocks and clock-names
> properties as optional,
> - At the moment do not add Bhupesh as a new QCE driver maintainer,
> - Minor updates to device tree binding documentation and qce driver,
> in particular added more compatibles and fixed lesser issues.
>
> Changes since v6:
> =================
> - v6 can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
> - As per Krzysztof's suggestion on v6, clubbed the crypto driver and
> dt-bindings changes together. Now the overall v5 patchset into 3
> separate patchsets, one each for the following areas to allow easier
> review and handling from the maintainer: arm-msm, crypto and dma
>
> Changes since v5:
> =================
> - v5 can be seen here: https://lore.kernel.org/lkml/[email protected]/
> - As per Bjorn's suggestion on irc, broke down the patchset into 4
> separate patchsets, one each for the following areas to allow easier
> review and handling from the maintainer: arm-msm, crypto, dma and devicetree
> - Addressed Rob's, Vladimir's and Bjorn's review comments received on v5.
> - Added Tested-by from Jordan received on the v5.
>
> Changes since v4:
> =================
> - v4 for sm8250 can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
> - v1 for sm8150 qce enablement can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
> - Merged the sm8150 and sm8250 enablement patches in the same patchset,
> as per suggestions from Bjorn.
> - Dropped a couple of patches from v4, as these have been picked by
> Bjorn already via his tree.
> - Addressed review comments from Vladimir, Thara and Rob.
> - Collect Reviewed-by from Rob and Thara on some of the patches from the
> v4 patchset.
>
> Changes since v3:
> =================
> - v3 can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
> - Dropped a couple of patches from v3, on basis of the review comments:
> ~ [PATCH 13/17] crypto: qce: core: Make clocks optional
> ~ [PATCH 15/17] crypto: qce: Convert the device found dev_dbg() to dev_info()
> - Addressed review comments from Thara, Rob and Stephan Gerhold.
> - Collect Reviewed-by from Rob and Thara on some of the patches from the
> v3 patchset.
>
> Changes since v2:
> =================
> - v2 can be seen here: https://lore.kernel.org/dmaengine/[email protected]/
> - Drop a couple of patches from v1, which tried to address the defered
> probing of qce driver in case bam dma driver is not yet probed.
> Replace it instead with a single (simpler) patch [PATCH 16/17].
> - Convert bam dma and qce crypto dt-bindings to YAML.
> - Addressed review comments from Thara, Bjorn, Vinod and Rob.
>
> Changes since v1:
> =================
> - v1 can be seen here: https://lore.kernel.org/linux-arm-msm/[email protected]/
> - v1 did not work well as reported earlier by Dmitry, so v2 contains the following
> changes/fixes:
> ~ Enable the interconnect path b/w BAM DMA and main memory first
> before trying to access the BAM DMA registers.
> ~ Enable the interconnect path b/w qce crytpo and main memory first
> before trying to access the qce crypto registers.
> ~ Make sure to document the required and optional properties for both
> BAM DMA and qce crypto drivers.
> ~ Add a few debug related print messages in case the qce crypto driver
> passes or fails to probe.
> ~ Convert the qce crypto driver probe to a defered one in case the BAM DMA
> or the interconnect driver(s) (needed on specific Qualcomm parts) are not
> yet probed.
>
> Bhupesh Sharma (4):
> dt-bindings: qcom-qce: Convert bindings to yaml
> MAINTAINERS: Add qcom-qce dt-binding file to QUALCOMM CRYPTO DRIVERS section
> dt-bindings: qcom-qce: Add 'interconnects' and 'interconnect-names'
> dt-bindings: qcom-qce: Add 'iommus' to optional properties
>
> Thara Gopinath (2):
> crypto: qce: core: Add support to initialize interconnect path
> crypto: qce: core: Make clocks optional
>
> Vladimir Zapolskiy (4):
> dt-bindings: qcom-qce: Add new SoC compatible strings for Qualcomm QCE IP
> dt-bindings: qcom-qce: document optional clocks and clock-names properties
> arm64: dts: qcom: sm8550: add QCE IP family compatible values
> crypto: qce: core: Add a QCE IP family compatible 'qcom,qce'
>
> .../devicetree/bindings/crypto/qcom-qce.txt | 25 ----
> .../devicetree/bindings/crypto/qcom-qce.yaml | 123 ++++++++++++++++++
> MAINTAINERS | 1 +
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
> drivers/crypto/qce/core.c | 23 +++-
> drivers/crypto/qce/core.h | 1 +
> 6 files changed, 145 insertions(+), 30 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.txt
> create mode 100644 Documentation/devicetree/bindings/crypto/qcom-qce.yaml
>
> --
> 2.33.0
All applied. Thanks.
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt