Received-SPF: pass (google.com: domain of linux-ext4-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Date:   Tue, 12 Oct 2021 15:56:29 -0300
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     Andrew Morton <akpm@linux-foundation.org>
Cc:     Alex Sierra <alex.sierra@amd.com>, Felix.Kuehling@amd.com,
        linux-mm@kvack.org, rcampbell@nvidia.com,
        linux-ext4@vger.kernel.org, linux-xfs@vger.kernel.org,
        amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
        hch@lst.de, jglisse@redhat.com, apopple@nvidia.com
Subject: Re: [PATCH v1 00/12] MEMORY_DEVICE_COHERENT for CPU-accessible
 coherent device memory
Message-ID: <20211012185629.GZ2744544@nvidia.com>
References: <20211012171247.2861-1-alex.sierra@amd.com>
 <20211012113957.53f05928dd60f3686331fede@linux-foundation.org>
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20211012113957.53f05928dd60f3686331fede@linux-foundation.org>
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?yZwX9ciqG4i6oWSUACRd0NbclweFKv5fU5VMl8DT63Tf6JAdWHUm+MSAs9JH?=
 =?us-ascii?Q?MwUkzYSmKFZ9F3n41pdHpZjosN7BvIgtWwxuUQLWDsDmaDQr9IOSfimpAb1j?=
 =?us-ascii?Q?EJGICuTBlwAv3cu1i9I8gd/NNTHVSSeXMv3Q2QYXRhhkugc8B81tPpVcMIw3?=
 =?us-ascii?Q?Ncmb9xiRRjrz2aLitljbVBvVUxQVSFQ0RCIrAmgsbBFY+YvprNICyOJJgVZl?=
 =?us-ascii?Q?TuwJJ1CX2tqCg5OYULsZqah3sLWrZjgbGlPYi7j4CL7XIjzAyjiSqYiahpHK?=
 =?us-ascii?Q?P5JmxGtL2dO3GGq419O8XAaSapH3mCXkom2HEoWOCQfTmcx24njwlFthXRo3?=
 =?us-ascii?Q?hVVsIuITEm97JnhH1QMCHZe7urUyyyKaFP8QPgx0GQJ/E43bCxuEeEqfdyd7?=
 =?us-ascii?Q?pX+YnS2KTrZTOlVGrGMIKRyi6WYE98aqQUjSDX6NRmTC+aNnXlg10fdea91P?=
 =?us-ascii?Q?vKp0aFFv2KmLvLyZgaid5ElwIEgFV7uROtnxgUVdGnKuuoyQHitB8CXYf5TG?=
 =?us-ascii?Q?di+H8OXI6veE1Xg3AQJrT9Jtz4i4+/jbu43l6i7wv9pHwO9ZsHXdqyXGZLNx?=
 =?us-ascii?Q?HblyPzygHGi9i1pPfLBpxWjoisFZ+sHkWdrqd25t2epFkBJ5tgH5LFVwI0J6?=
 =?us-ascii?Q?EUJwrsqFYM5qI8aF6MXD1DKuOaicOTyG9ctideJgP4OSmPiktTvgH4Pt0o+D?=
 =?us-ascii?Q?osD8G5kVVL4adtM9FyTYjEDYhL+f7f7db0AWw99KhvY5yAtvMlaMzWG5J8Sw?=
 =?us-ascii?Q?ZZcGdW2hXUB5cX9iLLsV72arH1+GFJhONtkld62lYTwZqNaiJp3UwjQs8gbV?=
 =?us-ascii?Q?eGjBN0+IpbOjIQkok0Bcwf7+/swjOm/qz86jX8g1UywNQiA1e5bOinjJ1ikB?=
 =?us-ascii?Q?DtCkyA5b3bDJhrd0Ho5UqilSs+JuCBAr8K36LS7fES8vGdhNZjuFrzNEapZs?=
 =?us-ascii?Q?ObxsWrC3Jcu2pybzIdmd4CuXqgSVQs1AQhGr3x/ulXRoDjuZQrNvgHh4G6Eh?=
 =?us-ascii?Q?WZm27DprxL+LNY1CGmYTIKME6EYlIDVLT3ZyYLgAAz1AlL6UksJdlVJx3BW/?=
 =?us-ascii?Q?EkFMZ50WODDj8rzM5qiW26tNIvkPiJAXmpqrcA4EPdiBZa2cnr2yGkPHiXfB?=
 =?us-ascii?Q?Kr7npPFTC/HaFK+YA1NSeUnl01+ZaD4zTRnUDP6dyIVFfAObOg/+uzf+Tey8?=
 =?us-ascii?Q?jy0KtRwyK7j/UiThGD+fxrAfKBKnqrCVEh057O+WlWACo4O1zup9WBfvDsZi?=
 =?us-ascii?Q?BCyw1jdQyly6WRkiqOA3W+xuy4ry6QNsRBhm2B0+71oWVRk2IJtymq1i14z3?=
 =?us-ascii?Q?xnh/71GOZZWlmAulQ6w7WpM+dCREuAw6OTspt69NIzBUNg=3D=3D?=
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-Network-Message-Id: d818ce8e-e5a7-4c3a-c500-08d98db200cd
X-MS-Exchange-CrossTenant-AuthSource: BL0PR12MB5506.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Oct 2021 18:56:30.8797
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: nOG43RYjvGhpxW5PCLUX8/dB5tj/DK0RKj+npKZR5dAUxe+kUIr9pKzbEHzi78ra
X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5030
Precedence: bulk
List-ID: <linux-ext4.vger.kernel.org>
X-Mailing-List: linux-ext4@vger.kernel.org

On Tue, Oct 12, 2021 at 11:39:57AM -0700, Andrew Morton wrote:
> On Tue, 12 Oct 2021 12:12:35 -0500 Alex Sierra <alex.sierra@amd.com> wrote:
> 
> > This patch series introduces MEMORY_DEVICE_COHERENT, a type of memory
> > owned by a device that can be mapped into CPU page tables like
> > MEMORY_DEVICE_GENERIC and can also be migrated like MEMORY_DEVICE_PRIVATE.
> > With MEMORY_DEVICE_COHERENT, we isolate the new memory type from other
> > subsystems as far as possible, though there are some small changes to
> > other subsystems such as filesystem DAX, to handle the new memory type
> > appropriately.
> > 
> > We use ZONE_DEVICE for this instead of NUMA so that the amdgpu
> > allocator can manage it without conflicting with core mm for non-unified
> > memory use cases.
> > 
> > How it works: The system BIOS advertises the GPU device memory (aka VRAM)
> > as SPM (special purpose memory) in the UEFI system address map.
> > The amdgpu driver registers the memory with devmap as
> > MEMORY_DEVICE_COHERENT using devm_memremap_pages.
> > 
> > The initial user for this hardware page migration capability will be
> > the Frontier supercomputer project.
> 
> To what other uses will this infrastructure be put?
> 
> Because I must ask: if this feature is for one single computer which
> presumably has a custom kernel, why add it to mainline Linux?

Well, it certainly isn't just "one single computer". Overall I know of
about, hmm, ~10 *datacenters* worth of installations that are using
similar technology underpinnings.

"Frontier" is the code name for a specific installation but as the
technology is proven out there will be many copies made of that same
approach.

The previous program "Summit" was done with NVIDIA GPUs and PowerPC
CPUs and also included a very similar capability. I think this is a
good sign that this coherently attached accelerator will continue to
be a theme in computing going foward. IIRC this was done using out of
tree kernel patches and NUMA localities.

Specifically with CXL now being standardized and on a path to ubiquity
I think we will see an explosion in deployments of coherently attached
accelerator memory. This is the high end trickling down to wider
usage.

I strongly think many CXL accelerators are going to want to manage
their on-accelerator memory in this way as it makes universal sense to
want to carefully manage memory access locality to optimize for
performance.

Jason