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From: "Luis R. Rodriguez" <mcgrof@gmail.com>
Date: Wed, 4 Nov 2009 14:04:11 -0800
Message-ID: <43e72e890911041404q5f491bbbw123d8761037f9c63@mail.gmail.com>
Subject: Re: pci_set_mwi() and ath5k
To: Matthew Wilcox <matthew@wil.cx>
Cc: Nick Kossifidis <mickflemm@gmail.com>,
	linux-wireless <linux-wireless@vger.kernel.org>,
	ath5k-devel@lists.ath5k.org,
	Stephen Hemminger <shemminger@vyatta.com>,
	Kyle McMartin <kyle@mcmartin.ca>
Content-Type: text/plain; charset=UTF-8
Sender: linux-wireless-owner@vger.kernel.org

On Wed, Nov 4, 2009 at 2:00 PM, Matthew Wilcox <matthew@wil.cx> wrote:
> On Wed, Nov 04, 2009 at 01:52:30PM -0800, Luis R. Rodriguez wrote:
>> > Even better: I just confirmation from our systems team that our legacy
>> > devices and 11n PCI devices don't support MWR so I'll remove all that
>> > cruft crap.
>>
>> I meant MWI of course.
>
> Yes, but they don't necessarily just use cacheline size for MWI ... some
> devices use cacheline size for setting up data structures.  Might be
> worth just checking explicitly that they don't use the cacheline size
> register for anything.

Oh right -- so the typical Atheros hack for this is to check the cache
line size, and if its 0 set it to L1_CACHE_BYTES. Then eventually read
from PCI_CACHE_LINE_SIZE pci config to align the skb data. So what I
was doing now is removing all this cruft and replacing it with a
generic allocator for atheros drivers that aligns simply to the
L1_CACHE_BYTES. Sound kosher?

  Luis