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From: =?ISO-8859-1?Q?G=E1bor_Stefanik?= <netrolller.3d@gmail.com>
Date: Mon, 1 Mar 2010 00:03:05 +0100
Message-ID: <69e28c911002281503l7259c897hafa26171adeaf0b1@mail.gmail.com>
Subject: Re: LP-PHY Fatal DMA error 0x00000800 on non-ULV Core 2 Duo?!?!!??!
To: Nathan Schulte <reklipz@gmail.com>
Cc: Larry Finger <Larry.Finger@lwfinger.net>,
	Michael Buesch <mb@bu3sch.de>, bcm43xx-dev@lists.berlios.de,
	linux-wireless@vger.kernel.org
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2010/2/28 Nathan Schulte <reklipz@gmail.com>:
> 2010/2/28 G?bor Stefanik <netrolller.3d@gmail.com>:
>> OK, this dump shows the 0x280a write happening with core 3, i.e. PCIE,
>> active. So, it is indeed probably the "PCIE misc configuration"
>> routine. Why it's 0x280a is still a mystery to me, it should be 0x100a
>> according to the specs.
> Unless I'm reading the logs wrong, isn't wl setting bit 0x8000 when
> core 1 is mapped (0 indexed cores, 0x18001000 mapped to space 0)?
> And b43 appears to do it when core 0 is mapped (0x18000000 mapped to
> space 0). ?b43 also reads from 0x100a after writing to 0x280a, and it
> reads as 0x8000 not set (while the 0x280a check show it is set).
>
> This is when comparing the wl_cold and b43_cold logs.
>
> -Nate
>

The latest patch, which is a partial success according to some
testers, writes to core 1 (PCI-E) instead of core 0 (ChipCommon).

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