Return-path: Received: from cavan.codon.org.uk ([93.93.128.6]:41524 "EHLO cavan.codon.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752411Ab0GZW3T (ORCPT ); Mon, 26 Jul 2010 18:29:19 -0400 Date: Mon, 26 Jul 2010 23:29:09 +0100 From: Matthew Garrett To: "Luis R. Rodriguez" Cc: Maxim Levitsky , "ath5k-devel@lists.ath5k.org" , "linux-wireless@vger.kernel.org" , David Quan , "Luis R. Rodriguez" , linux-kernel , "kernel-team@lists.ubuntu.com" , Luis Rodriguez , Jussi Kivilinna , "tim.gardner@canonical.com" Subject: Re: [ath5k-devel] [PATCH v3] ath5k: disable ASPM Message-ID: <20100726222909.GA6773@srcf.ucam.org> References: <1276952554.3332.3.camel@maxim-laptop> <1276961564.5173.12.camel@maxim-laptop> <20100726201322.GI14855@tux> <1280177362.3721.7.camel@maxim-laptop> <20100726210651.GJ14855@tux> <1280179033.3721.15.camel@maxim-laptop> <20100726212543.GA5424@srcf.ucam.org> <20100726222113.GA6487@srcf.ucam.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: Sender: linux-wireless-owner@vger.kernel.org List-ID: On Mon, Jul 26, 2010 at 03:26:37PM -0700, Luis R. Rodriguez wrote: > What I meant was that the PCI config space would already have L1 > enabled if L1 worked, so I don't see why we would need to nitpick out > specifics here. All Atheros PCIE chips should work with L1. The advise > given is to disable L0s though. I believe AR2425 would be one which > likely had L0s enabled but requires it to be disabled. Not sure of > others. But this is why I am saying this can be done globally for all > ath5k chipsets. If L1 is set but the chip is pre-PCIe 1.1 then we'll disable L1 unless the driver tells us that it's functional. The .inf from the Windows driver seemed to suggest that only a subset of the chips re-enabled L1 there, but if it's ok in general then that's a straightforward one-line patch. -- Matthew Garrett | mjg59@srcf.ucam.org