Return-path: Received: from mail-qw0-f46.google.com ([209.85.216.46]:40150 "EHLO mail-qw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752197Ab1BIUAH (ORCPT ); Wed, 9 Feb 2011 15:00:07 -0500 Received: by qwa26 with SMTP id 26so443055qwa.19 for ; Wed, 09 Feb 2011 12:00:06 -0800 (PST) MIME-Version: 1.0 Date: Wed, 9 Feb 2011 21:00:04 +0100 Message-ID: Subject: Notes on ssb specs and implementation From: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= To: linux-wireless@vger.kernel.org, Michael Buesch , Larry Finger Cc: b43-dev Content-Type: multipart/mixed; boundary=0016e6891d104ac305049bdee9e7 Sender: linux-wireless-owner@vger.kernel.org List-ID: --0016e6891d104ac305049bdee9e7 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Hi, I've N-PHY card that doesn't report any scan results, so after checking N-PHY code (it looks fine so far) I decided to dig into ssb. Hopefully this will lead to some fixes and maybe working card. I've dumped MMIO operations performed by wl and ssb/b43, compared them, documented with parts from specs and noted differences. As you should know, we have to enable wireless core twice: first time to get basic information about hardware, second to configure it in correct (like PHY specific) way. ssb_device_enable_1 is for first reset ssb_device_enable_2 is for second reset Notes from ssb_device_enable_1: 1) There are few undocumented flushes performed by both drivers. Could be nice to document it in specs 2) wl does not reset PHY (no B43_TMSLOW_PHYRESET and no taking it out of reset after enabling wireless core) 3) After reset (last step in ssb_device_enable) wl doesn't leave core specific flags Notes from ssb_device_enable_2: 1) ssb does not implement fast disable in case clocks are not enabled 2) ssb uses different Reject bit than wl 3) ssb doesn't check for "If the Core ID Low register has the "Initiator" bit set" 4) wl checks for "Busy" bit in IM STATE, not TM as documented in specs 5) when writing "Force Gated Clocks On", "Clock Enable", and "Reset" both drivers keep Reject set, however specs don't mention that 6) wl checks "If the "Initiator" bit in TM State Low is set" using ff8 register which is Core ID Low, not TMSLOW 7) rest differences are duplicated from ssb_device_enable_1 Larry: could you care for specs notes I collected? Michael: was there any reasons why we didn't implement some parts of core-disabling code? Michael: should we care about the way wl sets core specific flags? I didn't dig into that moment in MMIO dumps, but as ssb_device_enable implementation ignores flags at the end, it has to set flags somehow differently on it's own. --=20 Rafa=C5=82 --0016e6891d104ac305049bdee9e7 Content-Type: text/plain; charset=US-ASCII; name="ssb_device_enable_1.wl.txt" Content-Disposition: attachment; filename="ssb_device_enable_1.wl.txt" Content-Transfer-Encoding: base64 X-Attachment-Id: f_gjyn7ea40 d2w6Cgo+Pj4gc3NiX2RldmljZV9lbmFibGUgc3RhcnQKPj4+IHNzYl9kZXZpY2VfZGlzYWJsZSBz dGFydAkJRGlzYWJsZSB0aGUgQ29yZSB0byBhY2NvdW50IGZvciBhIGNvcmUgaW4gYSByYW5kb20g c3RhdGUKc3NiX3JlYWQzMigweGY5OCkgLT4gMHgwMDAwMDAwMwkJSWYgdGhlIGNvcmUgaXMgYWxy ZWFkeSBpbiByZXNldCAodGhlICJSZXNldCIgYml0IGluIFRNIFN0YXRlIExvdyBpcyBzZXQpIGl0 J3MgYWxyZWFkeSBkaXNhYmxlZCwgcmV0dXJuCnNzYl9yZWFkMzIoMHhmOTgpIC0+IDB4MDAwMDAw MDMJCUlmIHRoZSBjb3JlIGlzIGFscmVhZHkgaW4gcmVzZXQgKHRoZSAiUmVzZXQiIGJpdCBpbiBU TSBTdGF0ZSBMb3cgaXMgc2V0KSBpdCdzIGFscmVhZHkgZGlzYWJsZWQsIHJldHVybgo+Pj4gc3Ni X2RldmljZV9kaXNhYmxlIGVuZAoKc3NiX3dyaXRlMzIoMHhmOTgpIDwtIDB4MDAwNzAwMDEJKHNw ZWNpZmljPT1CNDNfVE1TTE9XX1BIWUNMS0VOKSBXcml0ZSB0aGUgIkZvcmNlIEdhdGVkIENsb2Nr cyBPbiIsICJDbG9jayBFbmFibGUiLGFuZCAiUmVzZXQiIGJpdHMgYWxvbmcgd2l0aCBhbnkgZGV2 aWNlIHNwZWNpZmljIGZsYWdzIHJlcXVlc3RlZCwgdG8gdGhlIFRNIFN0YXRlIExvdyByZWdpc3Rl ciAodW5zZXQgdGhlIHJlc3QpCnNzYl9yZWFkMzIoMHhmOTgpIC0+IDB4MDAwNzAwMDEJCVBlcmZv cm0gYSBkdW1teSByZWFkIG9uIHRoZSBUTSBTdGF0ZSBMb3cgcmVnaXN0ZXIKCnNzYl9yZWFkMzIo MHhmOWMpIC0+IDB4MTAwYzAwMDAJCUlmIHRoZSBTIEVycm9yIGJpdCBpcyBzZXQgaW4gdGhlIFRN IFN0YXRlIEhpZ2ggcmVnaXN0ZXIKc3NiX3JlYWQzMigweGY5MCkgLT4gMHgwMDAwMDAyMAkJVW5z ZXQgdGhlICJJbiBCYW5kIEVycm9yIiBvciAiVGltZW91dCIgYml0cyBpZiB0aGUgSU0gU3RhdGUg cmVnaXN0ZXIgaGFzIHRoZW0gc2V0Cgpzc2Jfd3JpdGUzMigweGY5OCkgPC0gMHgwMDA3MDAwMAko c3BlY2lmaWM9PUI0M19UTVNMT1dfUEhZQ0xLRU4pIFdyaXRlIHRoZSAiRm9yY2UgR2F0ZWQgQ2xv Y2tzIE9uIiwgIkNsb2NrIEVuYWJsZSIgYml0cywgYWxvbmcgd2l0aCBhbnkgZGV2aWNlIHNwZWNp ZmljIGZsYWdzIHJlcXVlc3RlZCwgdG8gdGhlIFRNIFN0YXRlIExvdyByZWdpc3RlciAodW5zZXQg dGhlIHJlc3QpIApzc2JfcmVhZDMyKDB4Zjk4KSAtPiAweDAwMDcwMDAwCQlQZXJmb3JtIGEgZHVt bXkgcmVhZCBvbiB0aGUgVE0gU3RhdGUgTG93IHJlZ2lzdGVyCgpzc2Jfd3JpdGUzMigweGY5OCkg PC0gMHgwMDAxMDAwMAkoV2h5IG5vIEI0M19UTVNMT1dfUEhZQ0xLRU4/KSBXcml0ZSB0aGUgIkNs b2NrIEVuYWJsZSIgYml0IGFsb25nIHdpdGggYW55IGRldmljZSBzcGVjaWZpYyBmbGFncyByZXF1 ZXN0ZWQgdG8gdGhlIFRNIFN0YXRlIExvdyByZWdpc3RlciAodW5zZXQgdGhlIHJlc3QpCnNzYl9y ZWFkMzIoMHhmOTgpIC0+IDB4MDAwMTAwMDAJCVVuZG9jdW1lbnRlZCBmbHVzaAo+Pj4gc3NiX2Rl dmljZV9lbmFibGUgZW5kCg== --0016e6891d104ac305049bdee9e7 Content-Type: text/plain; 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