Subject: Re: [RFC][PATCH] bcmai: introduce AI driver
From: George Kashperko <george@znau.edu.ua>
To: =?UTF-8?Q?Rafa=C5=82_Mi=C5=82ecki?= <zajec5@gmail.com>
Cc: Arend van Spriel <arend@broadcom.com>,
	"linux-wireless@vger.kernel.org" <linux-wireless@vger.kernel.org>,
	"John W. Linville" <linville@tuxdriver.com>,
	Larry Finger <Larry.Finger@lwfinger.net>,
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	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	Russell King <rmk@arm.linux.org.uk>,
	Arnd Bergmann <arnd@arndb.de>,
	linuxdriverproject <devel@linuxdriverproject.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
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Date: Thu, 07 Apr 2011 04:02:19 +0300
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> W dniu 7 kwietnia 2011 02:00 użytkownik George Kashperko
> <george@znau.edu.ua> napisał:
> > For PCI function description take a look at PCI specs or PCI
> > configuration space description (e. g.
> > http://en.wikipedia.org/wiki/PCI_configuration_space)
> >
> > Sorry for missleading short-ups, w11 - bcm80211 core, under two-head I
> > mean ssb/axi with two functional cores on same interconnect (like w11
> > +w11, not a lot of these exists I guess). Also there were some b43+b44
> > on single PCI ssb host and those where implemented as ssb interconnect
> > on multifunctional PCI host therefore providing separate access windows
> > for each function.
> >
> > Might I mussunderstood something (its late night here at my place) when
> > you where talking about using coreswitching involved for two drivers
> > therefore I remembered about those functions. Seems now you were talking
> > about chipcommon+b43 access sharing same window.
> >
> > As for core switching requirments for earlier SSB interconnects on PCI
> > hosts where there were no direct chipcommon access, that one can be
> > accomplished without spin_lock/mutex for b43 or b44 cores with proper
> > bus design.
> >
> > AXI doesn't need spinlocks/mutexes as both chipcommon and pci bridge are
> > available directly and b43 will be the only one requiring window access.
> 
> Ahh, so while talking about 4 windows, I guess you counted fixes
> windows as well. That would be right, matching my knowledge.
Nop, I mean sliding windows only.

> 
> When asking question about amount of cores we may want to use
> simultaneously I didn't think about ChipCommon or PCIe. The real
> problem would be to support for example two 802.11 cores and one
> ethernet core at the same time. That gives us 3 cores while we have
> only 2 sliding windows. But I would not care for that too much for
> now.
That will give us 3 PCI functions, each with own sliding windows.

> 
> For the rest (PCI function) I have to sleep before reading specs ;)
> 

Have nice day,
George