Return-path: Received: from hqemgate04.nvidia.com ([216.228.121.35]:12952 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753098Ab2H0K0U (ORCPT ); Mon, 27 Aug 2012 06:26:20 -0400 From: Wei Ni To: , , CC: , , , , , , , Wei Ni Subject: [PATCH 1/6] ARM: tegra: set up wlan clocks for tegra dt Date: Mon, 27 Aug 2012 18:25:09 +0800 Message-ID: <1346063114-30361-2-git-send-email-wni@nvidia.com> (sfid-20120827_122649_799691_1932188C) In-Reply-To: <1346063114-30361-1-git-send-email-wni@nvidia.com> References: <1346063114-30361-1-git-send-email-wni@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-wireless-owner@vger.kernel.org List-ID: Set up the wlan clock tree for Tegra20 and Tegra30. Signed-off-by: Wei Ni --- arch/arm/mach-tegra/board-dt-tegra20.c | 4 ++++ arch/arm/mach-tegra/board-dt-tegra30.c | 4 ++++ 2 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c index d9eeae6..5efc219 100644 --- a/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/arch/arm/mach-tegra/board-dt-tegra20.c @@ -79,8 +79,12 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { { "pll_a", "pll_p_out1", 56448000, true }, { "pll_a_out0", "pll_a", 11289600, true }, { "cdev1", NULL, 0, true }, + { "blink", "clk_32k", 32768, true }, { "i2s1", "pll_a_out0", 11289600, false}, { "i2s2", "pll_a_out0", 11289600, false}, + { "sdmmc1", "pll_p", 48000000, false}, + { "sdmmc3", "pll_p", 48000000, false}, + { "sdmmc4", "pll_p", 48000000, false}, { NULL, NULL, 0, 0}, }; diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c index 53bf60f..3277d1e 100644 --- a/arch/arm/mach-tegra/board-dt-tegra30.c +++ b/arch/arm/mach-tegra/board-dt-tegra30.c @@ -61,11 +61,15 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { { "pll_a_out0", "pll_a", 11289600, true }, { "extern1", "pll_a_out0", 0, true }, { "clk_out_1", "extern1", 0, true }, + { "blink", "clk_32k", 32768, true }, { "i2s0", "pll_a_out0", 11289600, false}, { "i2s1", "pll_a_out0", 11289600, false}, { "i2s2", "pll_a_out0", 11289600, false}, { "i2s3", "pll_a_out0", 11289600, false}, { "i2s4", "pll_a_out0", 11289600, false}, + { "sdmmc1", "pll_p", 48000000, false}, + { "sdmmc3", "pll_p", 48000000, false}, + { "sdmmc4", "pll_p", 48000000, false}, { NULL, NULL, 0, 0}, }; -- 1.7.1