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Date: Tue, 26 Mar 2013 10:33:47 -0700
Message-ID: <CAJ-Vmom67dWGVASc-dm03NfG2bWFQ+v6b1UMW7nh1t4Q+j0RJw@mail.gmail.com> (sfid-20130326_183353_794835_DA2621CD)
Subject: Re: [ath9k-devel] Auth Packet TX Delay
From: Adrian Chadd <adrian@freebsd.org>
To: Ben Greear <greearb@candelatech.com>
Cc: Robert Shade <robert.shade@gmail.com>,
	Christian Lamparter <chunkeey@googlemail.com>,
	ath9k-devel@venema.h4ckr.net, linux-wireless@vger.kernel.org,
	Marco Fonseca <marco@tampabay.rr.com>
Content-Type: text/plain; charset=ISO-8859-1
Sender: linux-wireless-owner@vger.kernel.org

Right. Well, when you reset the FIFO chances are you should walk said
FIFO queue in the TXQ (not the pending frames, the "hw" frames) and
requeue each to the hardware.

What I am doing in my EDMA restart routine in FreeBSD:

* (assume TX is stopped, chip is reset, the completed frames are
already removed from the FIFO queue in the TXQ);

* save the old FIFO count
* blank the FIFO count
* walk the FIFO list (NOT the pending list), pushing head pointers
back into the FIFO - and this will bump the FIFO counter by one each
time;
* when I've finished that, compare the FIFO count to the old FIFO
count - they should match.

I've not looked at the ath9k code in too much depth lately as I've
been more interested in getting FreeBSD's EDMA code finished (and I
think it is, woo!); so if you give me an hour or two I'll go do
another code review and see what pops up.


Adrian