Return-path: Received: from mail-ot0-f193.google.com ([74.125.82.193]:40263 "EHLO mail-ot0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932340AbeALBlJ (ORCPT ); Thu, 11 Jan 2018 20:41:09 -0500 Received: by mail-ot0-f193.google.com with SMTP id d10so3850613oti.7 for ; Thu, 11 Jan 2018 17:41:09 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: <151571798296.27429.7166552848688034184.stgit@dwillia2-desk3.amr.corp.intel.com> From: Dan Williams Date: Thu, 11 Jan 2018 17:41:08 -0800 Message-ID: (sfid-20180112_024141_693685_6A1863ED) Subject: Re: [PATCH v2 00/19] prevent bounds-check bypass via speculative execution To: Linus Torvalds Cc: Linux Kernel Mailing List , Mark Rutland , kernel-hardening@lists.openwall.com, Peter Zijlstra , Alan Cox , Will Deacon , Alexei Starovoitov , Solomon Peachy , "H. Peter Anvin" , Christian Lamparter , Elena Reshetova , linux-arch@vger.kernel.org, Andi Kleen , "James E.J. Bottomley" , Linux SCSI List , Jonathan Corbet , "the arch/x86 maintainers" , Russell King , Ingo Molnar , Catalin Marinas , Alexey Kuznetsov , Linux Media Mailing List , Tom Lendacky , Kees Cook , Jan Kara , Al Viro , qla2xxx-upstream@qlogic.com, Thomas Gleixner , Mauro Carvalho Chehab , Kalle Valo , Alan Cox , "Martin K. Petersen" , Hideaki YOSHIFUJI , Greg KH , Linux Wireless List , "Eric W. Biederman" , Network Development , Andrew Morton , "David S. Miller" , Laurent Pinchart Content-Type: text/plain; charset="UTF-8" Sender: linux-wireless-owner@vger.kernel.org List-ID: On Thu, Jan 11, 2018 at 5:19 PM, Linus Torvalds wrote: > On Thu, Jan 11, 2018 at 4:46 PM, Dan Williams wrote: >> >> This series incorporates Mark Rutland's latest ARM changes and adds >> the x86 specific implementation of 'ifence_array_ptr'. That ifence >> based approach is provided as an opt-in fallback, but the default >> mitigation, '__array_ptr', uses a 'mask' approach that removes >> conditional branches instructions, and otherwise aims to redirect >> speculation to use a NULL pointer rather than a user controlled value. > > Do you have any performance numbers and perhaps example code > generation? Is this noticeable? Are there any microbenchmarks showing > the difference between lfence use and the masking model? I don't have performance numbers, but here's a sample code generation from __fcheck_files, where the 'and; lea; and' sequence is portion of array_ptr() after the mask generation with 'sbb'. fdp = array_ptr(fdt->fd, fd, fdt->max_fds); 8e7: 8b 02 mov (%rdx),%eax 8e9: 48 39 c7 cmp %rax,%rdi 8ec: 48 19 c9 sbb %rcx,%rcx 8ef: 48 8b 42 08 mov 0x8(%rdx),%rax 8f3: 48 89 fe mov %rdi,%rsi 8f6: 48 21 ce and %rcx,%rsi 8f9: 48 8d 04 f0 lea (%rax,%rsi,8),%rax 8fd: 48 21 c8 and %rcx,%rax > Having both seems good for testing, but wouldn't we want to pick one in the end? I was thinking we'd keep it as a 'just in case' sort of thing, at least until the 'probably safe' assumption of the 'mask' approach has more time to settle out. > > Also, I do think that there is one particular array load that would > seem to be pretty obvious: the system call function pointer array. > > Yes, yes, the actual call is now behind a retpoline, but that protects > against a speculative BTB access, it's not obvious that it protects > against the mispredict of the __NR_syscall_max comparison in > arch/x86/entry/entry_64.S. > > The act of fetching code is a kind of read too. And retpoline protects > against BTB stuffing etc, but what if the _actual_ system call > function address is wrong (due to mis-prediction of the system call > index check)? > > Should the array access in entry_SYSCALL_64_fastpath be made to use > the masking approach? I'll take a look. I'm firmly in the 'patch first / worry later' stance on these investigations.