Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75E90C10F13 for ; Thu, 11 Apr 2019 10:45:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 46F7D2073F for ; Thu, 11 Apr 2019 10:45:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=megous.com header.i=@megous.com header.b="pCtjZcsu" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726775AbfDKKo6 (ORCPT ); Thu, 11 Apr 2019 06:44:58 -0400 Received: from vps.xff.cz ([195.181.215.36]:49642 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726599AbfDKKo5 (ORCPT ); Thu, 11 Apr 2019 06:44:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1554979493; bh=0gGCEy17EJytU3Qa7YkPYr52jDS0L4gECQ49SrhKOVQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=pCtjZcsuCeA8BCz5/n9dCnKF/hqLw3jZbW+LmEz6djvNqCXHVPTnWF3aV3CE6SZsw UbfK7X8BuBFXbeHwRRG+3NRnbUoGoXmDUGgZoWOu6UtnDAhmGeSTb+/Znka8rirdN0 XYCKOTz32OYTHdLvL+5XJF787IDWJWUcSCs6MOj4= Date: Thu, 11 Apr 2019 12:44:53 +0200 From: =?utf-8?Q?Ond=C5=99ej?= Jirman To: Julian Calaby Cc: linux-sunxi , Maxime Ripard , Chen-Yu Tsai , Rob Herring , Linus Walleij , David Airlie , Daniel Vetter , Mark Rutland , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Maxime Coquelin , Arend van Spriel , Franky Lin , Hante Meuleman , Chi-Hsien Lin , Wright Feng , Kalle Valo , Naveen Gupta , dri-devel , devicetree , "Mailing List, Arm" , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-wireless@vger.kernel.org, brcm80211-dev-list.pdl@broadcom.com, brcm80211-dev-list@cypress.com, linux-gpio@vger.kernel.org Subject: Re: [linux-sunxi] [PATCH v3 03/11] pinctrl: sunxi: Prepare for alternative bias voltage setting methods Message-ID: <20190411104453.fhwhw3gkffikusfl@core.my.home> Mail-Followup-To: Julian Calaby , linux-sunxi , Maxime Ripard , Chen-Yu Tsai , Rob Herring , Linus Walleij , David Airlie , Daniel Vetter , Mark Rutland , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Maxime Coquelin , Arend van Spriel , Franky Lin , Hante Meuleman , Chi-Hsien Lin , Wright Feng , Kalle Valo , Naveen Gupta , dri-devel , devicetree , "Mailing List, Arm" , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-wireless@vger.kernel.org, brcm80211-dev-list.pdl@broadcom.com, brcm80211-dev-list@cypress.com, linux-gpio@vger.kernel.org References: <20190411101951.30223-1-megous@megous.com> <20190411101951.30223-4-megous@megous.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org On Thu, Apr 11, 2019 at 08:34:33PM +1000, Julian Calaby wrote: > Hi Ondrej > > On Thu, Apr 11, 2019 at 8:19 PM megous via linux-sunxi > wrote: > > > > From: Ondrej Jirman > > > > H6 has a different I/O voltage bias setting method than A80. Prepare > > existing code for using alternative bias voltage setting methods. > > > > Signed-off-by: Ondrej Jirman > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h > > index ee15ab067b5f..4bfc8a6d9dce 100644 > > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h > > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h > > @@ -95,6 +95,13 @@ > > #define PINCTRL_SUN7I_A20 BIT(7) > > #define PINCTRL_SUN8I_R40 BIT(8) > > > > +enum sunxi_desc_bias_voltage { > > + BIAS_VOLTAGE_NONE, > > + /* Bias voltage configuration is done through > > + * Pn_GRP_CONFIG registers, as seen on A80 SoC. */ > > + BIAS_VOLTAGE_GRP_CONFIG, > > +}; > > + > > struct sunxi_desc_function { > > unsigned long variant; > > const char *name; > > @@ -117,7 +124,7 @@ struct sunxi_pinctrl_desc { > > const unsigned int *irq_bank_map; > > bool irq_read_needs_mux; > > bool disable_strict_mode; > > - bool has_io_bias_cfg; > > + int io_bias_cfg_variant; > > Shouldn't we be defining this field using the enum rather than as an int? Yes, thank you, I fixed it for v4. regards, o. > Thanks, > > -- > Julian Calaby > > Email: julian.calaby@gmail.com > Profile: http://www.google.com/profiles/julian.calaby/