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From:   viktor.barna@celeno.com
To:     linux-wireless@vger.kernel.org
Cc:     Kalle Valo <kvalo@codeaurora.org>,
        "David S . Miller" <davem@davemloft.net>,
        Jakub Kicinski <kuba@kernel.org>,
        Aviad Brikman <aviad.brikman@celeno.com>,
        Eliav Farber <eliav.farber@gmail.com>,
        Oleksandr Savchenko <oleksandr.savchenko@celeno.com>,
        Shay Bar <shay.bar@celeno.com>,
        Viktor Barna <viktor.barna@celeno.com>
Subject: [RFC v1 094/256] cl8k: add fw/msg_rx.c
Date:   Thu, 17 Jun 2021 15:59:41 +0000
Message-Id: <20210617160223.160998-95-viktor.barna@celeno.com>
In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com>
References: <20210617160223.160998-1-viktor.barna@celeno.com>
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From: Viktor Barna <viktor.barna@celeno.com>

(Part of the split. Please, take a look at the cover letter for more
details).

Signed-off-by: Viktor Barna <viktor.barna@celeno.com>
---
 drivers/net/wireless/celeno/cl8k/fw/msg_rx.c | 349 +++++++++++++++++++
 1 file changed, 349 insertions(+)
 create mode 100644 drivers/net/wireless/celeno/cl8k/fw/msg_rx.c

diff --git a/drivers/net/wireless/celeno/cl8k/fw/msg_rx.c b/drivers/net/wir=
eless/celeno/cl8k/fw/msg_rx.c
new file mode 100644
index 000000000000..be8a6b13392b
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/fw/msg_rx.c
@@ -0,0 +1,349 @@
+// SPDX-License-Identifier: MIT
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#include "tx/tx.h"
+#include "sounding.h"
+#include "fw/msg_rx.h"
+#include "fw/msg_tx.h"
+#include "fw/msg_cfm.h"
+#include "stats.h"
+#include "rssi.h"
+#include "fw/fw_dbg.h"
+#include "utils/utils.h"
+#include "hw_assert.h"
+#include "rate_ctrl.h"
+#include "bus/pci/ipc.h"
+#include "rsrc_mgmt.h"
+#ifdef TRACE_SUPPORT
+#include "trace.h"
+#endif
+
+static inline void rx_mm_start_cfm(struct cl_hw *cl_hw, struct cl_ipc_e2a_=
msg *msg)
+{
+       cl_msg_cfm_clear(cl_hw, msg);
+
+       /* Send indication to the embedded that a new rxbuffer element are =
ready */
+       cl_hw->ipc_host2xmac_trigger_set(cl_hw->chip, IPC_IRQ_A2E_RXBUF_BAC=
K);
+}
+
+static inline void rx_mm_ba_add_cfm(struct cl_hw *cl_hw, struct cl_ipc_e2a=
_msg *msg)
+{
+       if (le16_to_cpu(msg->id) =3D=3D MM_BA_ADD_TX_CFM)
+               cl_msg_cfm_assign_and_clear(cl_hw, msg);
+       else
+               cl_msg_cfm_clear(cl_hw, msg);
+}
+
+static inline void rx_mm_rsrc_mgmt_cfm(struct cl_hw *cl_hw, struct cl_ipc_=
e2a_msg *msg)
+{
+       struct mm_rsrc_mgmt_cfm *cfm =3D (struct mm_rsrc_mgmt_cfm *)msg->pa=
ram;
+
+       cl_rsrc_mgmt_process_cfm(cl_hw, cfm);
+       cl_msg_cfm_clear(cl_hw, msg);
+}
+
+static inline void rx_mm_agg_tx_report_ind(struct cl_hw *cl_hw, struct cl_=
ipc_e2a_msg *msg)
+{
+       struct cl_agg_tx_report *agg_report =3D (struct cl_agg_tx_report *)=
msg->param;
+       struct cl_sta *cl_sta;
+       union cl_rate_ctrl_info rate_ctrl_info;
+
+       /*
+        * Take care of endianness and update gi and format_mod fields of r=
ate
+        * ctrl info in agg_report for the sake of any function that needs =
to
+        * use them
+        */
+       agg_report->rate_cntrl_info =3D le32_to_cpu(agg_report->rate_cntrl_=
info);
+       agg_report->rate_cntrl_info_he =3D le32_to_cpu(agg_report->rate_cnt=
rl_info_he);
+
+       rate_ctrl_info.word =3D agg_report->rate_cntrl_info;
+
+       cl_rate_ctrl_convert(&rate_ctrl_info);
+       agg_report->rate_cntrl_info =3D rate_ctrl_info.word;
+
+       cl_sta_lock(cl_hw);
+       cl_sta =3D cl_sta_get(cl_hw, agg_report->sta_idx);
+
+       if (cl_sta) {
+               /* TX stats */
+               cl_agg_tx_report_handler(cl_hw, cl_sta, (void *)agg_report)=
;
+               cl_stats_update_tx_agg(cl_hw, cl_sta, agg_report);
+
+               /* RSSI stats */
+               if (!agg_report->ba_not_received)
+                       cl_rssi_block_ack_handler(cl_hw, cl_sta, agg_report=
);
+
+               /*
+                * TODO: Do we need to notify upper layer at agg_report->su=
ccess?
+                * Ageout may need to reset ageout counter if at least one
+                * frame was success.
+                * May be needed when sending UDP downlink because BA's are=
 not
+                * forwarded to driver.
+                */
+       }
+
+       cl_sta_unlock(cl_hw);
+}
+
+static inline void rx_mm_sounding_ind(struct cl_hw *cl_hw, struct cl_ipc_e=
2a_msg *msg)
+{
+       struct mm_sounding_ind *ind =3D (struct mm_sounding_ind *)msg->para=
m;
+
+       cl_sounding_indication(cl_hw, ind);
+}
+
+static inline void rx_mm_fw_error_ind(struct cl_hw *cl_hw, struct cl_ipc_e=
2a_msg *msg)
+{
+       struct mm_fw_error_ind *ind =3D (struct mm_fw_error_ind *)msg->para=
m;
+
+       switch (ind->error_type) {
+       case MM_FW_ERROR_TYPE_MU_OFDMA_SLOW_SECONDARY:
+               break;
+       case MM_FW_ERROR_TYPE_MAX:
+       default:
+               cl_dbg_err(cl_hw, "Invalid fw error type %u\n", ind->error_=
type);
+               break;
+       }
+}
+
+static inline void rx_mm_idle_async_ind(struct cl_hw *cl_hw, struct cl_ipc=
_e2a_msg *msg)
+{
+       cl_hw->idle_async_set =3D false;
+
+       cl_dbg_trace(cl_hw, "Clear MM_IDLE_ASYNC_IND\n");
+}
+
+static inline void rx_mm_rsrc_mgmt_ind(struct cl_hw *cl_hw, struct cl_ipc_=
e2a_msg *msg)
+{
+       cl_rsrc_mgmt_process_ind(cl_hw, (struct mm_rsrc_mgmt_ind *)msg->par=
am);
+}
+
+static inline void rx_dbg_print_ind(struct cl_hw *cl_hw, struct cl_ipc_e2a=
_msg *msg)
+{
+       cl_hw_assert_print(cl_hw, msg);
+}
+
+static inline void rx_dbg_info_ind(struct cl_hw *cl_hw, struct cl_ipc_e2a_=
msg *msg)
+{
+       cl_fw_dbg_handler(cl_hw);
+}
+
+static void (*mm_hdlrs[])(struct cl_hw *cl_hw, struct cl_ipc_e2a_msg *msg)=
 =3D {
+       [MM_RESET_CFM]                  =3D cl_msg_cfm_clear,
+       [MM_START_CFM]                  =3D rx_mm_start_cfm,
+       [MM_VERSION_CFM]                =3D cl_msg_cfm_assign_and_clear,
+       [MM_ADD_IF_CFM]                 =3D cl_msg_cfm_assign_and_clear,
+       [MM_REMOVE_IF_CFM]              =3D cl_msg_cfm_clear,
+       [MM_STA_ADD_CFM]                =3D cl_msg_cfm_assign_and_clear,
+       [MM_STA_DEL_CFM]                =3D cl_msg_cfm_clear,
+       [MM_SET_FILTER_CFM]             =3D cl_msg_cfm_clear,
+       [MM_SET_CHANNEL_CFM]            =3D cl_msg_cfm_clear,
+       [MM_SET_DTIM_CFM]               =3D cl_msg_cfm_clear,
+       [MM_SET_BEACON_INT_CFM]         =3D cl_msg_cfm_clear,
+       [MM_SET_BASIC_RATES_CFM]        =3D cl_msg_cfm_clear,
+       [MM_SET_BSSID_CFM]              =3D cl_msg_cfm_clear,
+       [MM_SET_EDCA_CFM]               =3D cl_msg_cfm_clear,
+       [MM_SET_ASSOCIATED_CFM]         =3D cl_msg_cfm_clear,
+       [MM_SET_SLOTTIME_CFM]           =3D cl_msg_cfm_clear,
+       [MM_SET_IDLE_CFM]               =3D cl_msg_cfm_clear,
+       [MM_KEY_ADD_CFM]                =3D cl_msg_cfm_assign_and_clear,
+       [MM_KEY_DEL_CFM]                =3D cl_msg_cfm_clear,
+       [MM_BA_ADD_TX_CFM]              =3D rx_mm_ba_add_cfm,
+       [MM_BA_ADD_RX_CFM]              =3D rx_mm_ba_add_cfm,
+       [MM_BA_DEL_CFM]                 =3D cl_msg_cfm_assign_and_clear,
+       [MM_AVAILABLE_BA_TXQ_CFM]       =3D cl_msg_cfm_assign_and_clear,
+       [MM_UPDATE_RATE_DL_CFM]         =3D cl_msg_cfm_clear,
+       [MM_SET_VNS_CFM]                =3D cl_msg_cfm_clear,
+       [MM_SET_TX_BF_CFM]              =3D cl_msg_cfm_clear,
+       [MM_PHY_RESET_CFM]              =3D cl_msg_cfm_clear,
+       [MM_CONFIG_CCA_CFM]             =3D cl_msg_cfm_clear,
+       [MM_SET_DFS_CFM]                =3D cl_msg_cfm_clear,
+       [MM_SET_ANT_BITMAP_CFM]         =3D cl_msg_cfm_clear,
+       [MM_NDP_TX_CONTROL_CFM]         =3D cl_msg_cfm_clear,
+       [MM_REG_WRITE_CFM]              =3D cl_msg_cfm_clear,
+       [MM_PROT_MODE_CFM]              =3D cl_msg_cfm_clear,
+       [MM_GOTO_POWER_REDUCTION_CFM]   =3D cl_msg_cfm_clear,
+       [MM_SOUNDING_CFM]               =3D cl_msg_cfm_assign_and_clear,
+       [MM_SOUNDING_PAIRING_CFM]       =3D cl_msg_cfm_clear,
+       [MM_SOUNDING_INTERVAL_CFM]      =3D cl_msg_cfm_assign_and_clear,
+       [MM_SOUNDING_STA_SWITCH_CFM]    =3D cl_msg_cfm_assign_and_clear,
+       [MM_BACKUP_BCN_EN_CFM]          =3D cl_msg_cfm_clear,
+       [MM_START_PERIODIC_TX_TIME_CFM] =3D cl_msg_cfm_clear,
+       [MM_ANAMON_READ_CFM]            =3D cl_msg_cfm_assign_and_clear,
+       [MM_REFRESH_PWR_CFM]            =3D cl_msg_cfm_clear,
+       [MM_SET_ANT_PWR_OFFSET_CFM]     =3D cl_msg_cfm_clear,
+       [MM_SET_RATE_FALLBACK_CFM]      =3D cl_msg_cfm_clear,
+       [MM_TWT_SETUP_CFM]              =3D cl_msg_cfm_clear,
+       [MM_TWT_TEARDOWN_CFM]           =3D cl_msg_cfm_clear,
+       [MM_RSRC_MGMT_CFM]              =3D rx_mm_rsrc_mgmt_cfm,
+       [MM_SET_FREQ_OFFSET_CFM]        =3D cl_msg_cfm_clear,
+       [MM_AGG_TX_REPORT_IND]          =3D rx_mm_agg_tx_report_ind,
+       [MM_SOUNDING_IND]               =3D rx_mm_sounding_ind,
+       [MM_FW_ERROR_IND]               =3D rx_mm_fw_error_ind,
+       [MM_IDLE_ASYNC_IND]             =3D rx_mm_idle_async_ind,
+       [MM_RSRC_MGMT_IND]              =3D rx_mm_rsrc_mgmt_ind,
+       [MM_MAX]                        =3D NULL,
+};
+
+#define DBG_MSG_SHIFT(id)  ((id) - FIRST_MSG(TASK_DBG))
+
+static void (*dbg_hdlrs[])(struct cl_hw *cl_hw, struct cl_ipc_e2a_msg *msg=
) =3D {
+       [DBG_MSG_SHIFT(DBG_SET_MOD_FILTER_CFM)]         =3D cl_msg_cfm_clea=
r,
+       [DBG_MSG_SHIFT(DBG_SET_SEV_FILTER_CFM)]         =3D cl_msg_cfm_clea=
r,
+       [DBG_MSG_SHIFT(DBG_CE_SET_MOD_FILTER_CFM)]      =3D cl_msg_cfm_clea=
r,
+       [DBG_MSG_SHIFT(DBG_BEAMFORMING_TX_CFM)]         =3D cl_msg_cfm_clea=
r,
+       [DBG_MSG_SHIFT(DBG_GET_E2W_STATS_CFM)]          =3D cl_msg_cfm_assi=
gn_and_clear,
+       [DBG_MSG_SHIFT(DBG_SET_LA_MPIF_MASK_CFM)]       =3D cl_msg_cfm_clea=
r,
+       [DBG_MSG_SHIFT(DBG_SET_LA_TRIG_POINT_CFM)]      =3D cl_msg_cfm_clea=
r,
+       [DBG_MSG_SHIFT(DBG_SET_LA_MPIF_DEBUG_MODE_CFM)] =3D cl_msg_cfm_clea=
r,
+       [DBG_MSG_SHIFT(DBG_SET_LA_TRIG_RULE_CFM)]       =3D cl_msg_cfm_clea=
r,
+       [DBG_MSG_SHIFT(DBG_TX_TRACE_DEBUG_FLAG_CFM)]    =3D cl_msg_cfm_clea=
r,
+       [DBG_MSG_SHIFT(DBG_PRINT_STATS_CFM)]            =3D cl_msg_cfm_clea=
r,
+       [DBG_MSG_SHIFT(DBG_TRIGGER_CFM)]                =3D cl_msg_cfm_clea=
r,
+       [DBG_MSG_SHIFT(DBG_TEST_MODE_CFM)]              =3D cl_msg_cfm_clea=
r,
+       [DBG_MSG_SHIFT(DBG_SOUNDING_CMD_CFM)]           =3D cl_msg_cfm_clea=
r,
+       [DBG_MSG_SHIFT(DBG_PRINT_IND)]                  =3D rx_dbg_print_in=
d,
+       [DBG_MSG_SHIFT(DBG_INFO_IND)]                   =3D rx_dbg_info_ind=
,
+       [DBG_MSG_SHIFT(DBG_MAX)]                        =3D NULL,
+};
+
+static bool is_dbg_msg(u16 msg_id)
+{
+       return (msg_id >=3D FIRST_MSG(TASK_DBG) && msg_id < DBG_MAX);
+}
+
+static void cl_msg_rx_run_mm(struct cl_hw *cl_hw, struct cl_ipc_e2a_msg *m=
sg, u16 msg_id)
+{
+       if (msg_id < MM_REQ_CFM_MAX)
+               cl_dbg_trace(cl_hw, "%s\n", msg2str[msg_id]);
+
+       mm_hdlrs[msg_id](cl_hw, msg);
+}
+
+static int cl_msg_rx_run_dbg(struct cl_hw *cl_hw, struct cl_ipc_e2a_msg *m=
sg, u16 msg_id)
+{
+       u16 dbg_id =3D DBG_MSG_SHIFT(msg_id);
+
+       if (dbg_hdlrs[dbg_id]) {
+               if (msg_id < DBG_REQ_CFM_MAX) {
+                       u16 str_id =3D DBG_STR_SHIFT(msg_id);
+
+                       cl_dbg_trace(cl_hw, "%s\n", msg2str[str_id]);
+               }
+
+               dbg_hdlrs[dbg_id](cl_hw, msg);
+               return 0;
+       }
+
+       return -1;
+}
+
+static int cl_msg_rx_run(struct cl_hw *cl_hw, struct cl_ipc_e2a_msg *msg)
+{
+       u16 msg_id =3D le16_to_cpu(msg->id);
+
+       if (msg_id < MM_MAX && mm_hdlrs[msg_id]) {
+               cl_msg_rx_run_mm(cl_hw, msg, msg_id);
+               return 0;
+       }
+
+       if (is_dbg_msg(msg_id))
+               return cl_msg_rx_run_dbg(cl_hw, msg, msg_id);
+
+       return -1;
+}
+
+static bool is_cfm_msg(u16 msg_id)
+{
+       /* A confirmation must be an odd id */
+       if ((msg_id & 0x1) =3D=3D 0)
+               return false;
+
+       return ((msg_id < MM_FIRST_IND) || is_dbg_msg(msg_id));
+}
+
+static int cl_msg_rx_handler(struct cl_hw *cl_hw, struct cl_ipc_e2a_msg *m=
sg)
+{
+       int ret =3D 0;
+       u16 msg_id =3D le16_to_cpu(msg->id);
+
+#ifdef TRACE_SUPPORT
+       trace_cl_trace_msg_rx_handler_start(cl_hw->idx, msg_id,
+                                           le32_to_cpu(msg->pattern), cl_h=
w->cfm_flags);
+#endif
+       /* Relay further actions to the msg parser */
+       ret =3D cl_msg_rx_run(cl_hw, msg);
+
+       if (ret) {
+               cl_dbg_err(cl_hw, "Unexpected msg (%u)\n", msg_id);
+       } else {
+               /* Wake up the queue in case the msg is a confirmation */
+               if (is_cfm_msg(msg_id))
+                       wake_up(&cl_hw->wait_queue);
+       }
+
+#ifdef TRACE_SUPPORT
+       trace_cl_trace_msg_rx_handler_end(cl_hw->idx, cl_hw->cfm_flags);
+#endif
+
+       return ret;
+}
+
+void cl_msg_rx_tasklet(unsigned long data)
+{
+       struct cl_hw *cl_hw =3D (struct cl_hw *)data;
+       struct cl_ipc_host_env *ipc_env =3D cl_hw->ipc_env;
+       struct cl_e2a_msg_elem *msg_elem =3D NULL;
+       struct cl_ipc_e2a_msg *msg =3D NULL;
+       int msg_handled =3D 0;
+       u8 idx;
+
+#ifdef TRACE_SUPPORT
+       trace_cl_trace_msg_rx_tasklet_start(cl_hw->idx);
+#endif
+
+       while (1) {
+               idx =3D ipc_env->e2a_msg_host_idx;
+               msg_elem =3D (struct cl_e2a_msg_elem *)(ipc_env->e2a_msg_ho=
stbuf_array[idx].hostid);
+               msg =3D msg_elem->msgbuf_ptr;
+
+               /* Look for pattern which means that this hostbuf has been =
used for a MSG */
+               if (le32_to_cpu(msg->pattern) !=3D IPC_E2A_MSG_VALID_PATTER=
N)
+                       break;
+
+               cl_msg_rx_handler(cl_hw, msg);
+               msg_handled++;
+
+               /* Reset the msg element and re-use it */
+               msg->pattern =3D 0;
+
+               /* Make sure memory is written before push to HW */
+               wmb();
+
+               /* Push back the buffer */
+               cl_ipc_msgbuf_push(ipc_env, (ptrdiff_t)msg_elem, msg_elem->=
dma_addr);
+       }
+
+#ifdef TRACE_SUPPORT
+       trace_cl_trace_msg_rx_tasklet_end(cl_hw->idx, msg_handled);
+#endif
+}
+
+void cl_msg_rx_flush_all(struct cl_hw *cl_hw)
+{
+       int i =3D 0;
+
+       for (i =3D FIRST_MSG(TASK_MM); i < MM_MAX; i++) {
+               if (cl_hw->msg_cfm_params[i]) {
+                       cl_dbg_verbose(cl_hw, "free MM msg_cfm_params %d\n"=
, i);
+                       cl_msg_tx_free_cfm_params(cl_hw, i);
+               }
+       }
+
+       for (i =3D FIRST_MSG(TASK_DBG); i < DBG_MAX; i++) {
+               if (cl_hw->msg_cfm_params[i]) {
+                       cl_dbg_verbose(cl_hw, "free DBG msg_cfm_params %d\n=
", i);
+                       cl_msg_tx_free_cfm_params(cl_hw, i);
+               }
+       }
+}
--
2.30.0

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