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From:   viktor.barna@celeno.com
To:     linux-wireless@vger.kernel.org
Cc:     Kalle Valo <kvalo@codeaurora.org>,
        "David S . Miller" <davem@davemloft.net>,
        Jakub Kicinski <kuba@kernel.org>,
        Aviad Brikman <aviad.brikman@celeno.com>,
        Eliav Farber <eliav.farber@gmail.com>,
        Oleksandr Savchenko <oleksandr.savchenko@celeno.com>,
        Shay Bar <shay.bar@celeno.com>,
        Viktor Barna <viktor.barna@celeno.com>
Subject: [RFC v1 161/256] cl8k: add reg/reg_modem_gcu.h
Date:   Thu, 17 Jun 2021 16:00:48 +0000
Message-Id: <20210617160223.160998-162-viktor.barna@celeno.com>
In-Reply-To: <20210617160223.160998-1-viktor.barna@celeno.com>
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From: Viktor Barna <viktor.barna@celeno.com>

(Part of the split. Please, take a look at the cover letter for more
details).

Signed-off-by: Viktor Barna <viktor.barna@celeno.com>
---
 .../wireless/celeno/cl8k/reg/reg_modem_gcu.h  | 628 ++++++++++++++++++
 1 file changed, 628 insertions(+)
 create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_modem_gcu.h

diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_modem_gcu.h b/drivers=
/net/wireless/celeno/cl8k/reg/reg_modem_gcu.h
new file mode 100644
index 000000000000..3073a364acec
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/reg/reg_modem_gcu.h
@@ -0,0 +1,628 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_REG_MODEM_GCU_H
+#define CL_REG_MODEM_GCU_H
+
+#include <linux/types.h>
+#include "reg/reg_access.h"
+#include "hw.h"
+
+#define REG_MODEM_GCU_BASE_ADDR 0x00480000
+
+/*
+ * @brief MPU register definition
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   21    MPU_CLK_F                 0
+ *   20    MPU_REG_CLK_F             0
+ *   13    MPU_CLK_EN                0
+ *   12    MPU_REG_CLK_EN            0
+ *   01    MPU_RST_N                 0
+ *   00    MPU_REG_RST_N             0
+ * </pre>
+ */
+#define MODEM_GCU_MPU_ADDR        (REG_MODEM_GCU_BASE_ADDR + 0x00000004)
+#define MODEM_GCU_MPU_OFFSET      0x00000004
+#define MODEM_GCU_MPU_INDEX       0x00000001
+#define MODEM_GCU_MPU_RESET       0x00000000
+
+static inline void modem_gcu_mpu_set(struct cl_hw *cl_hw, u32 value)
+{
+       cl_reg_write(cl_hw, MODEM_GCU_MPU_ADDR, value);
+}
+
+/* Field definitions */
+#define MODEM_GCU_MPU_CLK_F_BIT         ((u32)0x00200000)
+#define MODEM_GCU_MPU_CLK_F_POS         21
+#define MODEM_GCU_MPU_REG_CLK_F_BIT     ((u32)0x00100000)
+#define MODEM_GCU_MPU_REG_CLK_F_POS     20
+#define MODEM_GCU_MPU_CLK_EN_BIT        ((u32)0x00002000)
+#define MODEM_GCU_MPU_CLK_EN_POS        13
+#define MODEM_GCU_MPU_REG_CLK_EN_BIT    ((u32)0x00001000)
+#define MODEM_GCU_MPU_REG_CLK_EN_POS    12
+#define MODEM_GCU_MPU_RST_N_BIT         ((u32)0x00000002)
+#define MODEM_GCU_MPU_RST_N_POS         1
+#define MODEM_GCU_MPU_REG_RST_N_BIT     ((u32)0x00000001)
+#define MODEM_GCU_MPU_REG_RST_N_POS     0
+
+/*
+ * @brief BPU register definition
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   24    BPUL_RX_CLK_F             0
+ *   23    BPU_CLK_F                 0
+ *   22    BPU_RX_CLK_F              0
+ *   21    BPU_TX_CLK_F              0
+ *   20    BPU_REG_CLK_F             0
+ *   16    BPUL_RX_CLK_EN            0
+ *   15    BPU_CLK_EN                0
+ *   14    BPU_RX_CLK_EN             0
+ *   13    BPU_TX_CLK_EN             0
+ *   12    BPU_REG_CLK_EN            0
+ *   03    BPU_RST_N                 0
+ *   02    BPU_RX_RST_N              0
+ *   01    BPU_TX_RST_N              0
+ *   00    BPU_REG_RST_N             0
+ * </pre>
+ */
+#define MODEM_GCU_BPU_ADDR        (REG_MODEM_GCU_BASE_ADDR + 0x00000008)
+#define MODEM_GCU_BPU_OFFSET      0x00000008
+#define MODEM_GCU_BPU_INDEX       0x00000002
+#define MODEM_GCU_BPU_RESET       0x00000000
+
+static inline void modem_gcu_bpu_set(struct cl_hw *cl_hw, u32 value)
+{
+       cl_reg_write(cl_hw, MODEM_GCU_BPU_ADDR, value);
+}
+
+/* Field definitions */
+#define MODEM_GCU_BPU_BPUL_RX_CLK_F_BIT  ((u32)0x01000000)
+#define MODEM_GCU_BPU_BPUL_RX_CLK_F_POS  24
+#define MODEM_GCU_BPU_CLK_F_BIT          ((u32)0x00800000)
+#define MODEM_GCU_BPU_CLK_F_POS          23
+#define MODEM_GCU_BPU_RX_CLK_F_BIT       ((u32)0x00400000)
+#define MODEM_GCU_BPU_RX_CLK_F_POS       22
+#define MODEM_GCU_BPU_TX_CLK_F_BIT       ((u32)0x00200000)
+#define MODEM_GCU_BPU_TX_CLK_F_POS       21
+#define MODEM_GCU_BPU_REG_CLK_F_BIT      ((u32)0x00100000)
+#define MODEM_GCU_BPU_REG_CLK_F_POS      20
+#define MODEM_GCU_BPU_BPUL_RX_CLK_EN_BIT ((u32)0x00010000)
+#define MODEM_GCU_BPU_BPUL_RX_CLK_EN_POS 16
+#define MODEM_GCU_BPU_CLK_EN_BIT         ((u32)0x00008000)
+#define MODEM_GCU_BPU_CLK_EN_POS         15
+#define MODEM_GCU_BPU_RX_CLK_EN_BIT      ((u32)0x00004000)
+#define MODEM_GCU_BPU_RX_CLK_EN_POS      14
+#define MODEM_GCU_BPU_TX_CLK_EN_BIT      ((u32)0x00002000)
+#define MODEM_GCU_BPU_TX_CLK_EN_POS      13
+#define MODEM_GCU_BPU_REG_CLK_EN_BIT     ((u32)0x00001000)
+#define MODEM_GCU_BPU_REG_CLK_EN_POS     12
+#define MODEM_GCU_BPU_RST_N_BIT          ((u32)0x00000008)
+#define MODEM_GCU_BPU_RST_N_POS          3
+#define MODEM_GCU_BPU_RX_RST_N_BIT       ((u32)0x00000004)
+#define MODEM_GCU_BPU_RX_RST_N_POS       2
+#define MODEM_GCU_BPU_TX_RST_N_BIT       ((u32)0x00000002)
+#define MODEM_GCU_BPU_TX_RST_N_POS       1
+#define MODEM_GCU_BPU_REG_RST_N_BIT      ((u32)0x00000001)
+#define MODEM_GCU_BPU_REG_RST_N_POS      0
+/*
+ * @brief TFU register definition
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   21    TFU_CLK_F                 0
+ *   20    TFU_REG_CLK_F             0
+ *   13    TFU_CLK_EN                0
+ *   12    TFU_REG_CLK_EN            0
+ *   01    TFU_RST_N                 0
+ *   00    TFU_REG_RST_N             0
+ * </pre>
+ */
+#define MODEM_GCU_TFU_ADDR        (REG_MODEM_GCU_BASE_ADDR + 0x0000000C)
+#define MODEM_GCU_TFU_OFFSET      0x0000000C
+#define MODEM_GCU_TFU_INDEX       0x00000003
+#define MODEM_GCU_TFU_RESET       0x00000000
+
+static inline void modem_gcu_tfu_set(struct cl_hw *cl_hw, u32 value)
+{
+       cl_reg_write(cl_hw, MODEM_GCU_TFU_ADDR, value);
+}
+
+/* Field definitions */
+#define MODEM_GCU_TFU_CLK_F_BIT         ((u32)0x00200000)
+#define MODEM_GCU_TFU_CLK_F_POS         21
+#define MODEM_GCU_TFU_REG_CLK_F_BIT     ((u32)0x00100000)
+#define MODEM_GCU_TFU_REG_CLK_F_POS     20
+#define MODEM_GCU_TFU_CLK_EN_BIT        ((u32)0x00002000)
+#define MODEM_GCU_TFU_CLK_EN_POS        13
+#define MODEM_GCU_TFU_REG_CLK_EN_BIT    ((u32)0x00001000)
+#define MODEM_GCU_TFU_REG_CLK_EN_POS    12
+#define MODEM_GCU_TFU_RST_N_BIT         ((u32)0x00000002)
+#define MODEM_GCU_TFU_RST_N_POS         1
+#define MODEM_GCU_TFU_REG_RST_N_BIT     ((u32)0x00000001)
+#define MODEM_GCU_TFU_REG_RST_N_POS     0
+
+/*
+ * @brief SMU register definition
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   21    SMU_CLK_F                 0
+ *   20    SMU_REG_CLK_F             0
+ *   13    SMU_CLK_EN                0
+ *   12    SMU_REG_CLK_EN            0
+ *   01    SMU_RST_N                 0
+ *   00    SMU_REG_RST_N             0
+ * </pre>
+ */
+#define MODEM_GCU_SMU_ADDR        (REG_MODEM_GCU_BASE_ADDR + 0x00000010)
+#define MODEM_GCU_SMU_OFFSET      0x00000010
+#define MODEM_GCU_SMU_INDEX       0x00000004
+#define MODEM_GCU_SMU_RESET       0x00000000
+
+static inline void modem_gcu_smu_set(struct cl_hw *cl_hw, u32 value)
+{
+       cl_reg_write(cl_hw, MODEM_GCU_SMU_ADDR, value);
+}
+
+/* Field definitions */
+#define MODEM_GCU_SMU_CLK_F_BIT         ((u32)0x00200000)
+#define MODEM_GCU_SMU_CLK_F_POS         21
+#define MODEM_GCU_SMU_REG_CLK_F_BIT     ((u32)0x00100000)
+#define MODEM_GCU_SMU_REG_CLK_F_POS     20
+#define MODEM_GCU_SMU_CLK_EN_BIT        ((u32)0x00002000)
+#define MODEM_GCU_SMU_CLK_EN_POS        13
+#define MODEM_GCU_SMU_REG_CLK_EN_BIT    ((u32)0x00001000)
+#define MODEM_GCU_SMU_REG_CLK_EN_POS    12
+#define MODEM_GCU_SMU_RST_N_BIT         ((u32)0x00000002)
+#define MODEM_GCU_SMU_RST_N_POS         1
+#define MODEM_GCU_SMU_REG_RST_N_BIT     ((u32)0x00000001)
+#define MODEM_GCU_SMU_REG_RST_N_POS     0
+
+/*
+ * @brief MUX_FIC register definition
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   20    MUX_FIC_CLK_F             0
+ *   12    MUX_FIC_CLK_EN            0
+ *   01    FIC_MUX_SOFT_RST_N        1
+ *   00    MUX_FIC_RST_N             0
+ * </pre>
+ */
+#define MODEM_GCU_MUX_FIC_ADDR        (REG_MODEM_GCU_BASE_ADDR + 0x0000001=
4)
+#define MODEM_GCU_MUX_FIC_OFFSET      0x00000014
+#define MODEM_GCU_MUX_FIC_INDEX       0x00000005
+#define MODEM_GCU_MUX_FIC_RESET       0x00000002
+
+static inline void modem_gcu_mux_fic_set(struct cl_hw *cl_hw, u32 value)
+{
+       cl_reg_write(cl_hw, MODEM_GCU_MUX_FIC_ADDR, value);
+}
+
+/* Field definitions */
+#define MODEM_GCU_MUX_FIC_CLK_F_BIT      ((u32)0x00100000)
+#define MODEM_GCU_MUX_FIC_CLK_F_POS      20
+#define MODEM_GCU_MUX_FIC_CLK_EN_BIT     ((u32)0x00001000)
+#define MODEM_GCU_MUX_FIC_CLK_EN_POS     12
+#define MODEM_GCU_MUX_FIC_SOFT_RST_N_BIT ((u32)0x00000002)
+#define MODEM_GCU_MUX_FIC_SOFT_RST_N_POS 1
+#define MODEM_GCU_MUX_FIC_RST_N_BIT      ((u32)0x00000001)
+#define MODEM_GCU_MUX_FIC_RST_N_POS      0
+
+/*
+ * @brief MUX_FIC_CONFIG register definition
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   31    FIC_ISOLATED              0
+ *   17    FIC_ISOLATE               0
+ *   16    DISABLE_FIC_MESS          0
+ *   15:08 MUX_FIC_CONFLICT_DELAY_WRITE 0x0
+ *   07:00 MUX_FIC_CONFLICT_DELAY_READ 0x0
+ * </pre>
+ */
+#define MODEM_GCU_MUX_FIC_CONFIG_ADDR        (REG_MODEM_GCU_BASE_ADDR + 0x=
0000001C)
+#define MODEM_GCU_MUX_FIC_CONFIG_OFFSET      0x0000001C
+#define MODEM_GCU_MUX_FIC_CONFIG_INDEX       0x00000007
+#define MODEM_GCU_MUX_FIC_CONFIG_RESET       0x00000000
+
+static inline void modem_gcu_mux_fic_config_set(struct cl_hw *cl_hw, u32 v=
alue)
+{
+       cl_reg_write(cl_hw, MODEM_GCU_MUX_FIC_CONFIG_ADDR, value);
+}
+
+static inline u8 modem_gcu_mux_fic_config_fic_isolate_getf(struct cl_hw *c=
l_hw)
+{
+       u32 local_val =3D cl_reg_read(cl_hw, MODEM_GCU_MUX_FIC_CONFIG_ADDR)=
;
+
+       return ((local_val & ((u32)0x00020000)) >> 17);
+}
+
+static inline void modem_gcu_mux_fic_config_fic_isolate_setf(struct cl_hw =
*cl_hw, u8 ficisolate)
+{
+       ASSERT_ERR((((u32)ficisolate << 17) & ~((u32)0x00020000)) =3D=3D 0)=
;
+       cl_reg_write(cl_hw, MODEM_GCU_MUX_FIC_CONFIG_ADDR,
+                    (cl_reg_read(cl_hw, MODEM_GCU_MUX_FIC_CONFIG_ADDR) & ~=
((u32)0x00020000)) | ((u32)ficisolate << 17));
+}
+
+static inline u8 modem_gcu_mux_fic_config_fic_isolated_getf(struct cl_hw *=
cl_hw)
+{
+       u32 local_val =3D cl_reg_read(cl_hw, MODEM_GCU_MUX_FIC_CONFIG_ADDR)=
;
+
+       return ((local_val & ((u32)0x80000000)) >> 31);
+}
+
+/*
+ * @brief RIU_RST register definition
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   07    RIUFE_RST_N               0
+ *   06    RIUAGC_RST_N              0
+ *   05    RIU_MDM_B_RST_N           0
+ *   04    RIULB_RST_N               0
+ *   03    RIURC_RST_N               0
+ *   02    RIU_RADAR_RST_N           0
+ *   01    RIU_RST_N                 0
+ *   00    RIU_REG_RST_N             0
+ * </pre>
+ */
+#define MODEM_GCU_RIU_RST_ADDR        (REG_MODEM_GCU_BASE_ADDR + 0x0000002=
0)
+#define MODEM_GCU_RIU_RST_OFFSET      0x00000020
+#define MODEM_GCU_RIU_RST_INDEX       0x00000008
+#define MODEM_GCU_RIU_RST_RESET       0x00000000
+
+static inline void modem_gcu_riu_rst_set(struct cl_hw *cl_hw, u32 value)
+{
+       cl_reg_write(cl_hw, MODEM_GCU_RIU_RST_ADDR, value);
+}
+
+/* Field definitions */
+#define MODEM_GCU_RIU_FE_RST_N_BIT    ((u32)0x00000080)
+#define MODEM_GCU_RIU_FE_RST_N_POS    7
+#define MODEM_GCU_RIU_AGC_RST_N_BIT   ((u32)0x00000040)
+#define MODEM_GCU_RIU_AGC_RST_N_POS   6
+#define MODEM_GCU_RIU_MDM_B_RST_N_BIT ((u32)0x00000020)
+#define MODEM_GCU_RIU_MDM_B_RST_N_POS 5
+#define MODEM_GCU_RIU_LB_RST_N_BIT    ((u32)0x00000010)
+#define MODEM_GCU_RIU_LB_RST_N_POS    4
+#define MODEM_GCU_RIU_RC_RST_N_BIT    ((u32)0x00000008)
+#define MODEM_GCU_RIU_RC_RST_N_POS    3
+#define MODEM_GCU_RIU_RADAR_RST_N_BIT ((u32)0x00000004)
+#define MODEM_GCU_RIU_RADAR_RST_N_POS 2
+#define MODEM_GCU_RIU_RST_N_BIT       ((u32)0x00000002)
+#define MODEM_GCU_RIU_RST_N_POS       1
+#define MODEM_GCU_RIU_REG_RST_N_BIT   ((u32)0x00000001)
+#define MODEM_GCU_RIU_REG_RST_N_POS   0
+
+/*
+ * @brief RIU_CLK register definition
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   31    RIUADC_PWR_CLK_F          0
+ *   30    RIUFEA_5_CLK_F            0
+ *   29    RIUFEA_4_CLK_F            0
+ *   28    RIUFEA_3_CLK_F            0
+ *   27    RIUFEA_2_CLK_F            0
+ *   26    RIUFEA_1_CLK_F            0
+ *   25    RIUFEA_0_CLK_F            0
+ *   24    RIU_MDM_B_TX_CLK_F        0
+ *   23    RIU_MDM_B_RX_CLK_F        0
+ *   22    RIU_MDM_B_CLK_F           0
+ *   21    RIULB_CLK_F               0
+ *   20    RIURC_CLK_F               0
+ *   19    RIU_RADAR_CLK_F           0
+ *   18    RIUAGC_CLK_F              0
+ *   17    RIU_CLK_F                 0
+ *   16    RIU_REG_CLK_F             0
+ *   15    RIUADC_PWR_CLK_EN         0
+ *   14    RIUFEA_5_CLK_EN           0
+ *   13    RIUFEA_4_CLK_EN           0
+ *   12    RIUFEA_3_CLK_EN           0
+ *   11    RIUFEA_2_CLK_EN           0
+ *   10    RIUFEA_1_CLK_EN           0
+ *   09    RIUFEA_0_CLK_EN           0
+ *   08    RIU_MDM_B_TX_CLK_EN       0
+ *   07    RIU_MDM_B_RX_CLK_EN       0
+ *   06    RIU_MDM_B_CLK_EN          0
+ *   05    RIULB_CLK_EN              0
+ *   04    RIURCR_CLK_EN             0
+ *   03    RIU_RADAR_CLK_EN          0
+ *   02    RIUAGC_CLK_EN             0
+ *   01    RIU_CLK_EN                0
+ *   00    RIU_REG_CLK_EN            0
+ * </pre>
+ */
+#define MODEM_GCU_RIU_CLK_ADDR        (REG_MODEM_GCU_BASE_ADDR + 0x0000002=
4)
+#define MODEM_GCU_RIU_CLK_OFFSET      0x00000024
+#define MODEM_GCU_RIU_CLK_INDEX       0x00000009
+#define MODEM_GCU_RIU_CLK_RESET       0x00000000
+
+static inline void modem_gcu_riu_clk_set(struct cl_hw *cl_hw, u32 value)
+{
+       cl_reg_write(cl_hw, MODEM_GCU_RIU_CLK_ADDR, value);
+}
+
+/*
+ * @brief SPU register definition
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   21    SPU_CLK_F                 0
+ *   20    SPU_REG_CLK_F             0
+ *   13    SPU_CLK_EN                0
+ *   12    SPU_REG_CLK_EN            0
+ *   01    SPU_RST_N                 0
+ *   00    SPU_REG_RST_N             0
+ * </pre>
+ */
+#define MODEM_GCU_SPU_ADDR        (REG_MODEM_GCU_BASE_ADDR + 0x00000030)
+#define MODEM_GCU_SPU_OFFSET      0x00000030
+#define MODEM_GCU_SPU_INDEX       0x0000000C
+#define MODEM_GCU_SPU_RESET       0x00000000
+
+static inline void modem_gcu_spu_set(struct cl_hw *cl_hw, u32 value)
+{
+       cl_reg_write(cl_hw, MODEM_GCU_SPU_ADDR, value);
+}
+
+/* Field definitions */
+#define MODEM_GCU_SPU_CLK_F_BIT         ((u32)0x00200000)
+#define MODEM_GCU_SPU_CLK_F_POS         21
+#define MODEM_GCU_SPU_REG_CLK_F_BIT     ((u32)0x00100000)
+#define MODEM_GCU_SPU_REG_CLK_F_POS     20
+#define MODEM_GCU_SPU_CLK_EN_BIT        ((u32)0x00002000)
+#define MODEM_GCU_SPU_CLK_EN_POS        13
+#define MODEM_GCU_SPU_REG_CLK_EN_BIT    ((u32)0x00001000)
+#define MODEM_GCU_SPU_REG_CLK_EN_POS    12
+#define MODEM_GCU_SPU_RST_N_BIT         ((u32)0x00000002)
+#define MODEM_GCU_SPU_RST_N_POS         1
+#define MODEM_GCU_SPU_REG_RST_N_BIT     ((u32)0x00000001)
+#define MODEM_GCU_SPU_REG_RST_N_POS     0
+
+/*
+ * @brief LCU register definition
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   14    LCU_HLF_CLK_EN            0
+ *   13    LCU_CLK_EN                0
+ *   12    LCU_REG_CLK_EN            0
+ *   02    LCU_HLF_RST_N             0
+ *   01    LCU_RST_N                 0
+ *   00    LCU_REG_RST_N             0
+ * </pre>
+ */
+#define MODEM_GCU_LCU_ADDR        (REG_MODEM_GCU_BASE_ADDR + 0x00000034)
+#define MODEM_GCU_LCU_OFFSET      0x00000034
+#define MODEM_GCU_LCU_INDEX       0x0000000D
+#define MODEM_GCU_LCU_RESET       0x00000000
+
+static inline void modem_gcu_lcu_set(struct cl_hw *cl_hw, u32 value)
+{
+       cl_reg_write(cl_hw, MODEM_GCU_LCU_ADDR, value);
+}
+
+/* Field definitions */
+#define MODEM_GCU_LCU_HLF_CLK_EN_BIT    ((u32)0x00004000)
+#define MODEM_GCU_LCU_HLF_CLK_EN_POS    14
+#define MODEM_GCU_LCU_CLK_EN_BIT        ((u32)0x00002000)
+#define MODEM_GCU_LCU_CLK_EN_POS        13
+#define MODEM_GCU_LCU_REG_CLK_EN_BIT    ((u32)0x00001000)
+#define MODEM_GCU_LCU_REG_CLK_EN_POS    12
+#define MODEM_GCU_LCU_HLF_RST_N_BIT     ((u32)0x00000004)
+#define MODEM_GCU_LCU_HLF_RST_N_POS     2
+#define MODEM_GCU_LCU_RST_N_BIT         ((u32)0x00000002)
+#define MODEM_GCU_LCU_RST_N_POS         1
+#define MODEM_GCU_LCU_REG_RST_N_BIT     ((u32)0x00000001)
+#define MODEM_GCU_LCU_REG_RST_N_POS     0
+
+/*
+ * @brief EPA register definition
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   13    EPA_CLK_EN                0
+ *   12    EPA_REG_CLK_EN            0
+ *   01    EPA_RST_N                 0
+ *   00    EPA_REG_RST_N             0
+ * </pre>
+ */
+#define MODEM_GCU_EPA_ADDR        (REG_MODEM_GCU_BASE_ADDR + 0x00000038)
+#define MODEM_GCU_EPA_OFFSET      0x00000038
+#define MODEM_GCU_EPA_INDEX       0x0000000E
+#define MODEM_GCU_EPA_RESET       0x00000000
+
+static inline void modem_gcu_epa_set(struct cl_hw *cl_hw, u32 value)
+{
+       cl_reg_write(cl_hw, MODEM_GCU_EPA_ADDR, value);
+}
+
+/* Field definitions */
+#define MODEM_GCU_EPA_CLK_EN_BIT        ((u32)0x00002000)
+#define MODEM_GCU_EPA_CLK_EN_POS        13
+#define MODEM_GCU_EPA_REG_CLK_EN_BIT    ((u32)0x00001000)
+#define MODEM_GCU_EPA_REG_CLK_EN_POS    12
+#define MODEM_GCU_EPA_RST_N_BIT         ((u32)0x00000002)
+#define MODEM_GCU_EPA_RST_N_POS         1
+#define MODEM_GCU_EPA_REG_RST_N_BIT     ((u32)0x00000001)
+#define MODEM_GCU_EPA_REG_RST_N_POS     0
+
+/*
+ * @brief BF register definition
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   13    BF_CLK_EN                 0
+ *   12    BF_REG_CLK_EN             0
+ *   01    BF_RST_N                  0
+ *   00    BF_REG_RST_N              0
+ * </pre>
+ */
+#define MODEM_GCU_BF_ADDR        (REG_MODEM_GCU_BASE_ADDR + 0x0000003C)
+#define MODEM_GCU_BF_OFFSET      0x0000003C
+#define MODEM_GCU_BF_INDEX       0x0000000F
+#define MODEM_GCU_BF_RESET       0x00000000
+
+static inline void modem_gcu_bf_set(struct cl_hw *cl_hw, u32 value)
+{
+       cl_reg_write(cl_hw, MODEM_GCU_BF_ADDR, value);
+}
+
+/* Field definitions */
+#define MODEM_GCU_BF_CLK_EN_BIT          ((u32)0x00002000)
+#define MODEM_GCU_BF_CLK_EN_POS          13
+#define MODEM_GCU_BF_REG_CLK_EN_BIT      ((u32)0x00001000)
+#define MODEM_GCU_BF_REG_CLK_EN_POS      12
+#define MODEM_GCU_BF_RST_N_BIT           ((u32)0x00000002)
+#define MODEM_GCU_BF_RST_N_POS           1
+#define MODEM_GCU_BF_REG_RST_N_BIT       ((u32)0x00000001)
+#define MODEM_GCU_BF_REG_RST_N_POS       0
+
+/*
+ * @brief RIU_CLK_1 register definition
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   17    RIUFE_EXT_CLK_F           0
+ *   16    RIUFRC_CLK_F              0
+ *   01    RIUFE_EXT_CLK_EN          0
+ *   00    RIUFRC_CLK_EN             0
+ * </pre>
+ */
+#define MODEM_GCU_RIU_CLK_1_ADDR        (REG_MODEM_GCU_BASE_ADDR + 0x00000=
124)
+#define MODEM_GCU_RIU_CLK_1_OFFSET      0x00000124
+#define MODEM_GCU_RIU_CLK_1_INDEX       0x00000049
+#define MODEM_GCU_RIU_CLK_1_RESET       0x00000000
+
+static inline void modem_gcu_riu_clk_1_set(struct cl_hw *cl_hw, u32 value)
+{
+       cl_reg_write(cl_hw, MODEM_GCU_RIU_CLK_1_ADDR, value);
+}
+
+/*
+ * @brief CEVA_CTRL register definition
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   16    MCCI_ADDR_BASE            0
+ *   14    VINTC                     0
+ *   12    NMI                       0
+ *   10:09 EXT_VOM                   0x0
+ *   08    EXT_PV                    0
+ *   07:06 UIA                       0x0
+ *   05    STOP_SD                   0
+ *   04    MON_STAT                  0
+ *   02    EXTERNAL_WAIT             1
+ *   00    BOOT                      0
+ * </pre>
+ */
+#define MODEM_GCU_CEVA_CTRL_ADDR        (REG_MODEM_GCU_BASE_ADDR + 0x00001=
004)
+#define MODEM_GCU_CEVA_CTRL_OFFSET      0x00001004
+#define MODEM_GCU_CEVA_CTRL_INDEX       0x00000401
+#define MODEM_GCU_CEVA_CTRL_RESET       0x00000004
+
+static inline u32 modem_gcu_ceva_ctrl_get(struct cl_hw *cl_hw)
+{
+       return cl_reg_read(cl_hw, MODEM_GCU_CEVA_CTRL_ADDR);
+}
+
+static inline void modem_gcu_ceva_ctrl_set(struct cl_hw *cl_hw, u32 value)
+{
+       cl_reg_write(cl_hw, MODEM_GCU_CEVA_CTRL_ADDR, value);
+}
+
+/* Field definitions */
+#define MODEM_GCU_CEVA_CTRL_MCCI_ADDR_BASE_BIT ((u32)0x00010000)
+#define MODEM_GCU_CEVA_CTRL_MCCI_ADDR_BASE_POS 16
+#define MODEM_GCU_CEVA_CTRL_VINTC_BIT          ((u32)0x00004000)
+#define MODEM_GCU_CEVA_CTRL_VINTC_POS          14
+#define MODEM_GCU_CEVA_CTRL_NMI_BIT            ((u32)0x00001000)
+#define MODEM_GCU_CEVA_CTRL_NMI_POS            12
+#define MODEM_GCU_CEVA_CTRL_EXT_VOM_MASK       ((u32)0x00000600)
+#define MODEM_GCU_CEVA_CTRL_EXT_VOM_LSB        9
+#define MODEM_GCU_CEVA_CTRL_EXT_VOM_WIDTH      ((u32)0x00000002)
+#define MODEM_GCU_CEVA_CTRL_EXT_PV_BIT         ((u32)0x00000100)
+#define MODEM_GCU_CEVA_CTRL_EXT_PV_POS         8
+#define MODEM_GCU_CEVA_CTRL_UIA_MASK           ((u32)0x000000C0)
+#define MODEM_GCU_CEVA_CTRL_UIA_LSB            6
+#define MODEM_GCU_CEVA_CTRL_UIA_WIDTH          ((u32)0x00000002)
+#define MODEM_GCU_CEVA_CTRL_STOP_SD_BIT        ((u32)0x00000020)
+#define MODEM_GCU_CEVA_CTRL_STOP_SD_POS        5
+#define MODEM_GCU_CEVA_CTRL_MON_STAT_BIT       ((u32)0x00000010)
+#define MODEM_GCU_CEVA_CTRL_MON_STAT_POS       4
+#define MODEM_GCU_CEVA_CTRL_EXTERNAL_WAIT_BIT  ((u32)0x00000004)
+#define MODEM_GCU_CEVA_CTRL_EXTERNAL_WAIT_POS  2
+#define MODEM_GCU_CEVA_CTRL_BOOT_BIT           ((u32)0x00000001)
+#define MODEM_GCU_CEVA_CTRL_BOOT_POS           0
+
+static inline void modem_gcu_ceva_ctrl_external_wait_setf(struct cl_hw *cl=
_hw, u8 externalwait)
+{
+       ASSERT_ERR((((u32)externalwait << 2) & ~((u32)0x00000004)) =3D=3D 0=
);
+       cl_reg_write(cl_hw, MODEM_GCU_CEVA_CTRL_ADDR,
+                    (cl_reg_read(cl_hw, MODEM_GCU_CEVA_CTRL_ADDR) & ~((u32=
)0x00000004)) | ((u32)externalwait << 2));
+}
+
+static inline void modem_gcu_ceva_ctrl_boot_setf(struct cl_hw *cl_hw, u8 b=
oot)
+{
+       ASSERT_ERR((((u32)boot << 0) & ~((u32)0x00000001)) =3D=3D 0);
+       cl_reg_write(cl_hw, MODEM_GCU_CEVA_CTRL_ADDR,
+                    (cl_reg_read(cl_hw, MODEM_GCU_CEVA_CTRL_ADDR) & ~((u32=
)0x00000001)) | ((u32)boot << 0));
+}
+
+/*
+ * @brief CEVA_VEC register definition
+ * Ceva Vector register description
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   31:00 VECTOR                    0x0
+ * </pre>
+ */
+#define MODEM_GCU_CEVA_VEC_ADDR        (REG_MODEM_GCU_BASE_ADDR + 0x000010=
08)
+#define MODEM_GCU_CEVA_VEC_OFFSET      0x00001008
+#define MODEM_GCU_CEVA_VEC_INDEX       0x00000402
+#define MODEM_GCU_CEVA_VEC_RESET       0x00000000
+
+static inline void modem_gcu_ceva_vec_set(struct cl_hw *cl_hw, u32 value)
+{
+       cl_reg_write(cl_hw, MODEM_GCU_CEVA_VEC_ADDR, value);
+}
+
+/*
+ * @brief RIU_CLK_BW register definition
+ * RIU clocks BW. register description
+ * <pre>
+ *  Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *   13    agc_clk_bw                0
+ *   12:10 lb_mem_clk_bw             0x2
+ *   09:08 agc_mem_clk_bw            0x1
+ *   07:06 riu_afe_clk_bw            0x2
+ *   05:04 phyfesync_bw              0x2
+ *   03:02 adcpowclk_bw              0x2
+ *   01:00 riulbgclk_bw              0x2
+ * </pre>
+ */
+#define MODEM_GCU_RIU_CLK_BW_ADDR        (REG_MODEM_GCU_BASE_ADDR + 0x0000=
1240)
+#define MODEM_GCU_RIU_CLK_BW_OFFSET      0x00001240
+#define MODEM_GCU_RIU_CLK_BW_INDEX       0x00000490
+#define MODEM_GCU_RIU_CLK_BW_RESET       0x000009AA
+
+static inline void modem_gcu_riu_clk_bw_set(struct cl_hw *cl_hw, u32 value=
)
+{
+       cl_reg_write(cl_hw, MODEM_GCU_RIU_CLK_BW_ADDR, value);
+}
+
+static inline void modem_gcu_riu_clk_bw_agc_mem_clk_bw_setf(struct cl_hw *=
cl_hw, u8 agcmemclkbw)
+{
+       ASSERT_ERR((((u32)agcmemclkbw << 8) & ~((u32)0x00000300)) =3D=3D 0)=
;
+       cl_reg_write(cl_hw, MODEM_GCU_RIU_CLK_BW_ADDR,
+                    (cl_reg_read(cl_hw, MODEM_GCU_RIU_CLK_BW_ADDR) & ~((u3=
2)0x00000300)) | ((u32)agcmemclkbw << 8));
+}
+
+#endif /* CL_REG_MODEM_GCU_H */
--
2.30.0

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