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From:   viktor.barna@celeno.com
To:     linux-wireless@vger.kernel.org
Cc:     Kalle Valo <kvalo@codeaurora.org>,
        "David S . Miller" <davem@davemloft.net>,
        Jakub Kicinski <kuba@kernel.org>,
        Aviad Brikman <aviad.brikman@celeno.com>,
        Eliav Farber <eliav.farber@gmail.com>,
        Oleksandr Savchenko <oleksandr.savchenko@celeno.com>,
        Shay Bar <shay.bar@celeno.com>,
        Viktor Barna <viktor.barna@celeno.com>
Subject: [RFC v1 173/256] cl8k: add rx/rx.h
Date:   Thu, 17 Jun 2021 16:01:00 +0000
Message-Id: <20210617160223.160998-174-viktor.barna@celeno.com>
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From: Viktor Barna <viktor.barna@celeno.com>

(Part of the split. Please, take a look at the cover letter for more
details).

Signed-off-by: Viktor Barna <viktor.barna@celeno.com>
---
 drivers/net/wireless/celeno/cl8k/rx/rx.h | 173 +++++++++++++++++++++++
 1 file changed, 173 insertions(+)
 create mode 100644 drivers/net/wireless/celeno/cl8k/rx/rx.h

diff --git a/drivers/net/wireless/celeno/cl8k/rx/rx.h b/drivers/net/wireles=
s/celeno/cl8k/rx/rx.h
new file mode 100644
index 000000000000..17225990ab50
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/rx/rx.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_RX_H
+#define CL_RX_H
+
+#include "wrs/wrs_db.h"
+#include "hw.h"
+
+/* Decryption status subfields */
+enum cl_rx_hd_decr {
+       CL_RX_HDR_DECR_UNENC,
+       CL_RX_HDR_DECR_ICVFAIL,
+       CL_RX_HDR_DECR_CCMPFAIL,
+       CL_RX_HDR_DECR_AMSDUDISCARD,
+       CL_RX_HDR_DECR_NULLKEY,
+       CL_RX_HDR_DECR_WEPSUCCESS,
+       CL_RX_HDR_DECR_TKIPSUCCESS,
+       CL_RX_HDR_DECR_CCMPSUCCESS
+};
+
+#define CL_PADDING_IN_BYTES 2
+
+struct hw_rxhdr {
+       u32 msdu_cnt           : 8,   /* [7:0] */
+           corrupted_amsdu    : 1,   /* [8] */
+           reserved           : 1,   /* [9] */
+           msdu_dma_align     : 2,   /* [11:10] */
+           amsdu_error_code   : 4,   /* [15:12] */
+           reserved_2         :16;   /* [31:16] */
+
+       /* Total length for the MPDU transfer */
+       u32 len                :14,   /* [13:0] */
+           ampdu_cnt          : 2,   /* [15:14] */
+           rx_padding_done    : 1,   /* [16] */
+           rx_class_rule_res  : 7,   /* [23:17] */
+
+       /* AMPDU Status Information */
+           mpdu_cnt           : 8;   /* [31:24] */
+
+       /* TSF Low */
+       __le32 tsf_lo;
+       /* TSF High */
+       __le32 tsf_hi;
+
+       /* Receive Vector 1a */
+       u32 leg_length         :12,   /* [11:0] */
+           leg_rate           : 4,   /* [15:12] */
+           ht_length_l        :16;   /* [31:16] */
+
+       /* Receive Vector 1b */
+       u32 ht_length_h        : 8,   /* [7:0] */
+           mcs                : 7,   /* [14:8] */
+           pre_type           : 1,   /* [15] */
+           format_mod         : 4,   /* [19:16] */
+           reserved_1b        : 1,   /* [20] */
+           n_sts              : 3,   /* [23:21] */
+           lsig_valid         : 1,   /* [24] */
+           sounding           : 1,   /* [25] */
+           num_extn_ss        : 2,   /* [27:26] */
+           aggregation        : 1,   /* [28] */
+           fec_coding         : 1,   /* [29] */
+           dyn_bw             : 1,   /* [30] */
+           doze_not_allowed   : 1;   /* [31] */
+
+       /* Receive Vector 1c */
+       u32 sn                 : 4,  /* [3:0] */
+           warn_1c            : 1,  /* [4] */
+           stbc               : 2,  /* [6:5] */
+           smoothing          : 1,  /* [7] */
+           partial_aid        : 9,  /* [16:8] */
+           group_id           : 6,  /* [22:17] */
+           reserved_1c        : 1,  /* [23] */
+           rssi1              : 8;  /* [31:24] */
+
+       /* Receive Vector 1d */
+       s32 rssi2              : 8,  /* [7:0] */
+           rssi3              : 8,  /* [15:8] */
+           rssi4              : 8,  /* [23:16] */
+           rx_chains          : 8;  /* [31:24] */
+
+       /* Receive Vector 1e */
+       u32 txop_duration      : 7,  /* [6:0] */
+           beam_change        : 1,  /* [7] */
+           mcs_sig_b          : 3,  /* [10:8] */
+           dcm                : 1,  /* [11] */
+           dcm_sig_b          : 1,  /* [12] */
+           beamformed         : 1,  /* [13] */
+           ltf_type           : 2,  /* [15:14] */
+           ru_band            : 1,  /* [16] */
+           ru_type            : 3,  /* [19:17] */
+           ru_index           : 6,  /* [25:20] */
+           pe_duration        : 3,  /* [28:26] */
+           ch_bw              : 2,  /* [30:29] */
+           reserved_1e        : 1;  /* [31] */
+
+       /* Receive Vector 1f */
+       u32 spatial_reuse      : 16, /* [16:0] */
+           service            : 16; /* [32:17] */
+
+       /* Receive Vector 1g */
+       u32 bss_color          : 6,  /* [5:0] */
+           gi_type            : 2,  /* [7:6] */
+           antenna_set        : 16, /* [23:8] */
+           rssi5              : 8;  /* [31:24] */
+
+       /* Receive Vector 1h */
+       s32 rssi6              : 8,  /* [7:0] */
+           rssi7              : 8,  /* [15:8] */
+           rssi8              : 8,  /* [23:16] */
+           future_1           : 8;  /* [31:24] */
+
+       /* Receive Vector 2a */
+       u32 rcpi               : 8,  /* [7:0] */
+           evm1               : 8,  /* [15:8] */
+           evm2               : 8,  /* [23:16] */
+           evm3               : 8;  /* [31:24] */
+
+       /* Receive Vector 2b */
+       u32 evm4               : 8,  /* [7:0] */
+           warn_2b            : 1,  /* [8] */
+           reserved2b_1       : 7,  /* [15:9] */
+           reserved2b_2       : 8,  /* [23:16] */
+           reserved2b_3       : 8;  /* [31:24] */
+
+       /* Status **/
+       u32 rx_vect2_valid     : 1,  /* [0] */
+           resp_frame         : 1,  /* [1] */
+           decr_status        : 3,  /* [4:2] */
+           rx_fifo_oflow      : 1,  /* [5] */
+           undef_err          : 1,  /* [6] */
+           phy_err            : 1,  /* [7] */
+           fcs_err            : 1,  /* [8] */
+           addr_mismatch      : 1,  /* [9] */
+           ga_frame           : 1,  /* [10] */
+           first_qos_data     : 1,  /* [11] */
+           amsdu_present      : 1,  /* [12] */
+           frm_successful_rx  : 1,  /* [13] */
+           desc_done_rx       : 1,  /* [14] */
+           desc_spare         : 1,  /* [15] */
+           key_sram_index     : 9,  /* [24:16] */
+           key_sram_v         : 1,  /* [25] */
+           type               : 2,  /* [27:26] */
+           subtype            : 4;  /* [31:28] */
+
+       /* PHY channel information 1 */
+       u32 phy_band           : 8,  /* [7:0] */
+           phy_channel_type   : 8,  /* [15:8] */
+           phy_prim20_freq    : 16; /* [31:16] */
+
+       /* PHY channel information 2 */
+       u32 phy_center1_freq   : 16, /* [15:0] */
+           phy_center2_freq   : 16; /* [31:16] */
+
+       /* Patten **/
+       u32 pattern;
+};
+
+void cl_rx_init(struct cl_hw *cl_hw);
+void cl_rx_off(struct cl_hw *cl_hw);
+void cl_rx_remote_tasklet_sched(void *t);
+void cl_rx_remote_cpu_info(struct cl_hw *cl_hw);
+void cl_rx_push_queue(struct cl_hw *cl_hw, struct sk_buff *skb);
+void cl_rx_skb_alloc_handler(struct sk_buff *skb);
+void cl_rx_post_recovery(struct cl_hw *cl_hw);
+void cl_rx_info_reset(struct cl_hw *cl_hw);
+int cl_rx_info_print(struct cl_hw *cl_hw);
+void cl_rx_netif(struct cl_hw *cl_hw, struct cl_vif *cl_vif, struct sk_buf=
f *skb);
+void cl_rx_finish(struct cl_hw *cl_hw, struct sk_buff *skb);
+u8 cl_rx_get_skb_ac(struct ieee80211_hdr *hdr);
+bool cl_rx_process_in_irq(struct cl_hw *cl_hw);
+
+#endif /* CL_RX_H */
--
2.30.0

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