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From:   viktor.barna@celeno.com
To:     linux-wireless@vger.kernel.org
Cc:     Kalle Valo <kvalo@codeaurora.org>,
        "David S . Miller" <davem@davemloft.net>,
        Jakub Kicinski <kuba@kernel.org>,
        Aviad Brikman <aviad.brikman@celeno.com>,
        Eliav Farber <eliav.farber@gmail.com>,
        Oleksandr Savchenko <oleksandr.savchenko@celeno.com>,
        Shay Bar <shay.bar@celeno.com>,
        Viktor Barna <viktor.barna@celeno.com>
Subject: [RFC v1 233/256] cl8k: add version.c
Date:   Thu, 17 Jun 2021 16:02:00 +0000
Message-Id: <20210617160223.160998-234-viktor.barna@celeno.com>
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From: Viktor Barna <viktor.barna@celeno.com>

(Part of the split. Please, take a look at the cover letter for more
details).

Signed-off-by: Viktor Barna <viktor.barna@celeno.com>
---
 drivers/net/wireless/celeno/cl8k/version.c | 129 +++++++++++++++++++++
 1 file changed, 129 insertions(+)
 create mode 100644 drivers/net/wireless/celeno/cl8k/version.c

diff --git a/drivers/net/wireless/celeno/cl8k/version.c b/drivers/net/wirel=
ess/celeno/cl8k/version.c
new file mode 100644
index 000000000000..4ac0bea0ae62
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/version.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: MIT
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#include "version.h"
+#include "fw/msg_tx.h"
+#include "debug.h"
+#include "chip.h"
+#include "utils/utils.h"
+
+/*
+ * Don't move this define to a different file, and
+ * don't change the default version.
+ */
+#define HP_VERSION "8.0.0.0.0.0"
+
+static int cl_version_request(struct cl_hw *cl_hw)
+{
+       struct mm_version_cfm *cfm =3D NULL;
+       struct cl_version_db *vd =3D &cl_hw->version_db;
+       int ret =3D 0;
+
+       ret =3D cl_msg_tx_version(cl_hw);
+       if (ret)
+               return ret;
+
+       cfm =3D (struct mm_version_cfm *)cl_hw->msg_cfm_params[MM_VERSION_C=
FM];
+       if (!cfm)
+               return -ENOMSG;
+
+       vd->last_update =3D jiffies;
+       vd->dsp =3D le32_to_cpu(cfm->versions.dsp);
+       vd->rfic_sw =3D le32_to_cpu(cfm->versions.rfic_sw);
+       vd->rfic_hw =3D le32_to_cpu(cfm->versions.rfic_hw);
+       vd->agcram =3D le32_to_cpu(cfm->versions.agcram);
+
+       cl_hw->rf_crystal_mhz =3D cfm->rf_crystal_mhz;
+
+       strncpy(vd->fw, cfm->versions.fw, sizeof(vd->fw));
+       vd->fw[sizeof(vd->fw) - 1] =3D '\0';
+
+       strncpy(vd->drv, HP_VERSION, sizeof(vd->drv));
+       vd->drv[sizeof(vd->drv) - 1] =3D '\0';
+
+       cl_msg_tx_free_cfm_params(cl_hw, MM_VERSION_CFM);
+
+       return ret;
+}
+
+int cl_version_read(struct cl_hw *cl_hw, bool reply)
+{
+       struct cl_chip *chip =3D cl_hw->chip;
+       struct cl_version_db *vd =3D &cl_hw->version_db;
+       int ret =3D 0;
+       struct cl_agc_profile *agc_profile1 =3D &cl_hw->phy_data_info.data-=
>agc_params.profile1;
+       struct cl_agc_profile *agc_profile2 =3D &cl_hw->phy_data_info.data-=
>agc_params.profile2;
+       char *buf =3D NULL;
+       ssize_t bufsz;
+       int len =3D 0;
+       u32 version_agcram, major, minor, internal;
+
+       /* Request data if existing is not actual */
+       if (!vd->last_update && (ret =3D cl_version_request(cl_hw)))
+               return ret;
+
+       /* PHY components specifics */
+       cl_snprintf(&buf, &len, &bufsz, "DRV VERSION: %s\n", vd->drv);
+       cl_snprintf(&buf, &len, &bufsz, "FW VERSION: %s\n", vd->fw);
+       cl_snprintf(&buf, &len, &bufsz, "DSP VERSION: 0x%-.8X\n", vd->dsp);
+       cl_snprintf(&buf, &len, &bufsz, "RFIC SW VERSION: %u\n", vd->rfic_s=
w);
+       cl_snprintf(&buf, &len, &bufsz, "RFIC HW VERSION: 0x%X\n", vd->rfic=
_hw);
+
+       version_agcram =3D vd->agcram;
+       major =3D (version_agcram >> 16) & 0xffff;
+       minor =3D (version_agcram >> 8) & 0xff;
+       internal =3D version_agcram & 0xff;
+       cl_snprintf(&buf, &len, &bufsz,
+                   "AGC RAM VERSION: B.%x.%x.%x\n",
+                   major, minor, internal);
+
+       cl_agc_params_print_profile(&buf, &len, &bufsz, agc_profile1,
+                                   "AGC PARAMS PROFILE:");
+       cl_agc_params_print_profile(&buf, &len, &bufsz, agc_profile2,
+                                   "AGC PARAMS PROFILE (Elastic):");
+       cl_snprintf(&buf, &len, &bufsz, "TX POWER VERSION: %u\n", cl_hw->tx=
_power_version);
+
+       if (IS_PHY_OLYMPUS(chip))
+               cl_snprintf(&buf, &len, &bufsz, "RFIC TYPE: OLYMPUS\n");
+       else
+               cl_snprintf(&buf, &len, &bufsz, "RFIC TYPE: ATHOS\n");
+
+       cl_snprintf(&buf, &len, &bufsz, "RF CRYSTAL: %uMHz\n",
+                   cl_hw->rf_crystal_mhz);
+
+       if (reply)
+               ret =3D cl_vendor_reply(cl_hw, buf, len);
+       else
+               pr_debug("%s\n", buf);
+
+       kfree(buf);
+
+       return ret;
+}
+
+int cl_version_update(struct cl_hw *cl_hw)
+{
+       int ret =3D 0;
+
+       /* Force logic to update versions */
+       cl_hw->version_db.last_update =3D 0;
+
+       ret =3D cl_version_read(cl_hw, false);
+
+       /* Share version info */
+       if (ret =3D=3D 0)
+               cl_version_sync_wiphy(cl_hw, cl_hw->hw->wiphy);
+
+       return ret;
+}
+
+void cl_version_sync_wiphy(struct cl_hw *cl_hw, struct wiphy *wiphy)
+{
+       strncpy(wiphy->fw_version, cl_hw->version_db.fw, sizeof(wiphy->fw_v=
ersion));
+       wiphy->fw_version[sizeof(wiphy->fw_version) - 1] =3D '\0';
+}
+
+int cl_version_cli(struct cl_hw *cl_hw)
+{
+       return cl_version_read(cl_hw, true);
+}
--
2.30.0

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