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From:   viktor.barna@celeno.com
To:     linux-wireless@vger.kernel.org
Cc:     Kalle Valo <kvalo@codeaurora.org>,
        "David S . Miller" <davem@davemloft.net>,
        Jakub Kicinski <kuba@kernel.org>,
        Aviad Brikman <aviad.brikman@celeno.com>,
        Eliav Farber <eliav.farber@gmail.com>,
        Oleksandr Savchenko <oleksandr.savchenko@celeno.com>,
        Shay Bar <shay.bar@celeno.com>,
        Viktor Barna <viktor.barna@celeno.com>
Subject: [RFC v1 154/256] cl8k: add reg/reg_ipc.h
Date:   Thu, 17 Jun 2021 16:00:41 +0000
Message-Id: <20210617160223.160998-155-viktor.barna@celeno.com>
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From: Viktor Barna <viktor.barna@celeno.com>

(Part of the split. Please, take a look at the cover letter for more
details).

Signed-off-by: Viktor Barna <viktor.barna@celeno.com>
---
 .../net/wireless/celeno/cl8k/reg/reg_ipc.h    | 157 ++++++++++++++++++
 1 file changed, 157 insertions(+)
 create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_ipc.h

diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_ipc.h b/drivers/net/w=
ireless/celeno/cl8k/reg/reg_ipc.h
new file mode 100644
index 000000000000..d825b8559aae
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/reg/reg_ipc.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_REG_IPC_H
+#define CL_REG_IPC_H
+
+#include <linux/types.h>
+#include "reg/reg_access.h"
+#include "chip.h"
+
+#define REG_IPC_BASE_ADDR 0x007C4000
+
+/*
+ * @brief XMAC_2_HOST_RAW_STATUS register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 xmac2host_raw_status      0x0
+ * </pre>
+ */
+#define IPC_XMAC_2_HOST_RAW_STATUS_ADDR        (REG_IPC_BASE_ADDR + 0x0000=
0004)
+#define IPC_XMAC_2_HOST_RAW_STATUS_OFFSET      0x00000004
+#define IPC_XMAC_2_HOST_RAW_STATUS_INDEX       0x00000001
+#define IPC_XMAC_2_HOST_RAW_STATUS_RESET       0x00000000
+
+static inline u32 ipc_xmac_2_host_raw_status_get(struct cl_chip *chip)
+{
+       return cl_reg_read_chip(chip, IPC_XMAC_2_HOST_RAW_STATUS_ADDR);
+}
+
+/*
+ * @brief XMAC_2_HOST_ACK register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 xmac2host_trigger_clr     0x0
+ * </pre>
+ */
+#define IPC_XMAC_2_HOST_ACK_ADDR        (REG_IPC_BASE_ADDR + 0x00000008)
+#define IPC_XMAC_2_HOST_ACK_OFFSET      0x00000008
+#define IPC_XMAC_2_HOST_ACK_INDEX       0x00000002
+#define IPC_XMAC_2_HOST_ACK_RESET       0x00000000
+
+static inline void ipc_xmac_2_host_ack_set(struct cl_chip *chip, u32 value=
)
+{
+       cl_reg_write_chip(chip, IPC_XMAC_2_HOST_ACK_ADDR, value);
+}
+
+/*
+ * @brief XMAC_2_HOST_ENABLE_SET register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 xmac2host_enable_set      0x0
+ * </pre>
+ */
+#define IPC_XMAC_2_HOST_ENABLE_SET_ADDR        (REG_IPC_BASE_ADDR + 0x0000=
000C)
+#define IPC_XMAC_2_HOST_ENABLE_SET_OFFSET      0x0000000C
+#define IPC_XMAC_2_HOST_ENABLE_SET_INDEX       0x00000003
+#define IPC_XMAC_2_HOST_ENABLE_SET_RESET       0x00000000
+
+static inline void ipc_xmac_2_host_enable_set_set(struct cl_chip *chip, u3=
2 value)
+{
+       cl_reg_write_chip(chip, IPC_XMAC_2_HOST_ENABLE_SET_ADDR, value);
+}
+
+/*
+ * @brief XMAC_2_HOST_ENABLE_CLEAR register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 xmac2host_enable_clear    0x0
+ * </pre>
+ */
+#define IPC_XMAC_2_HOST_ENABLE_CLEAR_ADDR        (REG_IPC_BASE_ADDR + 0x00=
000010)
+#define IPC_XMAC_2_HOST_ENABLE_CLEAR_OFFSET      0x00000010
+#define IPC_XMAC_2_HOST_ENABLE_CLEAR_INDEX       0x00000004
+#define IPC_XMAC_2_HOST_ENABLE_CLEAR_RESET       0x00000000
+
+static inline void ipc_xmac_2_host_enable_clear_set(struct cl_chip *chip, =
u32 value)
+{
+       cl_reg_write_chip(chip, IPC_XMAC_2_HOST_ENABLE_CLEAR_ADDR, value);
+}
+
+/*
+ * @brief XMAC_2_HOST_STATUS register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 xmac2host_status          0x0
+ * </pre>
+ */
+#define IPC_XMAC_2_HOST_STATUS_ADDR        (REG_IPC_BASE_ADDR + 0x00000014=
)
+#define IPC_XMAC_2_HOST_STATUS_OFFSET      0x00000014
+#define IPC_XMAC_2_HOST_STATUS_INDEX       0x00000005
+#define IPC_XMAC_2_HOST_STATUS_RESET       0x00000000
+
+static inline u32 ipc_xmac_2_host_status_get(struct cl_chip *chip)
+{
+       return cl_reg_read_chip(chip, IPC_XMAC_2_HOST_STATUS_ADDR);
+}
+
+/*
+ * @brief HOST_GLOBAL_INT_EN register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    00    master_int_enable         0
+ * </pre>
+ */
+#define IPC_HOST_GLOBAL_INT_EN_ADDR        (REG_IPC_BASE_ADDR + 0x00000030=
)
+#define IPC_HOST_GLOBAL_INT_EN_OFFSET      0x00000030
+#define IPC_HOST_GLOBAL_INT_EN_INDEX       0x0000000C
+#define IPC_HOST_GLOBAL_INT_EN_RESET       0x00000000
+
+static inline void ipc_host_global_int_en_set(struct cl_chip *chip, u32 va=
lue)
+{
+       cl_reg_write_chip(chip, IPC_HOST_GLOBAL_INT_EN_ADDR, value);
+}
+
+/*
+ * @brief HOST_2_LMAC_TRIGGER register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 host2lmac_trigger         0x0
+ * </pre>
+ */
+#define IPC_HOST_2_LMAC_TRIGGER_ADDR        (REG_IPC_BASE_ADDR + 0x0000008=
0)
+#define IPC_HOST_2_LMAC_TRIGGER_OFFSET      0x00000080
+#define IPC_HOST_2_LMAC_TRIGGER_INDEX       0x00000020
+#define IPC_HOST_2_LMAC_TRIGGER_RESET       0x00000000
+
+static inline void ipc_host_2_lmac_trigger_set(struct cl_chip *chip, u32 v=
alue)
+{
+       cl_reg_write_chip(chip, IPC_HOST_2_LMAC_TRIGGER_ADDR, value);
+}
+
+/*
+ * @brief HOST_2_SMAC_TRIGGER register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:00 host2smac_trigger         0x0
+ * </pre>
+ */
+#define IPC_HOST_2_SMAC_TRIGGER_ADDR        (REG_IPC_BASE_ADDR + 0x0000008=
8)
+#define IPC_HOST_2_SMAC_TRIGGER_OFFSET      0x00000088
+#define IPC_HOST_2_SMAC_TRIGGER_INDEX       0x00000022
+#define IPC_HOST_2_SMAC_TRIGGER_RESET       0x00000000
+
+static inline void ipc_host_2_smac_trigger_set(struct cl_chip *chip, u32 v=
alue)
+{
+       cl_reg_write_chip(chip, IPC_HOST_2_SMAC_TRIGGER_ADDR, value);
+}
+
+#endif /* CL_REG_IPC_H */
--
2.30.0

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