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Message-ID: <8a147d51-9dc0-5767-5d17-793845b9c5f7@dd-wrt.com>
Date:   Wed, 14 Jul 2021 07:38:39 +0200
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Subject: Re: [Bugreport] ath9k dynack not working/low performance on 5 & 10MHz
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To:     Koen Vandeputte <koen.vandeputte@citymesh.com>,
        Petrosilius <petrosilius@posteo.de>,
        linux-wireless@vger.kernel.org
References: <dd49d9f7-db40-4ab7-f24d-6ab4bbd0bb54@posteo.de>
 <fd620847-9786-07d2-23be-dba4cedc9089@citymesh.com>
 <2ffcf571-7068-c06f-3879-d02eacdc4895@posteo.de>
 <8a3718e1-e988-c24a-d94f-34ba0f5349f4@citymesh.com>
 <339f7aa7-b7ee-b7a8-2e87-a96634c00a32@posteo.de>
 <bba886f3-4ce1-94b0-ea44-89ddc8c84e2b@citymesh.com>
 <ca99a4cc-eb7d-dfca-1d26-5b504a57e31f@posteo.de>
 <a7e37fa2-5fe7-6a39-d72d-9e3723540331@citymesh.com>
From:   Sebastian Gottschall <s.gottschall@dd-wrt.com>
In-Reply-To: <a7e37fa2-5fe7-6a39-d72d-9e3723540331@citymesh.com>
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>
>
> Above log is with an iperf session running in the background. :-s
>
> Will look further into this ..
>
> Regards,
>
> Koen
some cents from me. the chipset has a hw delay/latency which doubles and 
quadroubles depending on the channel width. this special offset needs to 
be considered for ack
timing calculation. especially at very short distances you will run into 
a problem that if this calculation is wrong, the ack timing register 
contains a lower value than the hw delay/latency.
this will result in a effective negative ack value. maybe its worth to 
check if the values used for this latency offset are correct?
i found also a patch in my own code which i made many years ago (i 
cannot remember why) but maybe it helps
@@ -1128,11 +1110,10 @@

                 slottime = ah->slottime;
         }
+
         /* As defined by IEEE 802.11-2007 17.3.8.6 */
         slottime += 3 * ah->coverage_class;
         acktimeout = slottime + sifstime + ack_offset;
+       eifs += (6 * ah->coverage_class);
         ctstimeout = acktimeout;

         /*

Sebastian

>
>