From:   Sven Eckelmann <sven@narfation.org>
To:     ath11k@lists.infradead.org
Cc:     linux-wireless@vger.kernel.org, devicetree@vger.kernel.org,
        robh@kernel.org, Anilkumar Kolli <akolli@codeaurora.org>
Subject: Re: [PATH v3 2/2] ath11k: Use reserved host DDR addresses from DT for PCI devices
Date:   Fri, 19 Nov 2021 14:56:45 +0100
Message-ID: <40959183.USSs3XEnCI@sven-l14>
In-Reply-To: <1637244892-27267-2-git-send-email-akolli@codeaurora.org>
References: <1637244892-27267-1-git-send-email-akolli@codeaurora.org> <1637244892-27267-2-git-send-email-akolli@codeaurora.org>
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From: Sven Eckelmann <sven@narfation.org>
To: ath11k@lists.infradead.org
Cc: linux-wireless@vger.kernel.org, devicetree@vger.kernel.org, robh@kernel.org, Anilkumar Kolli <akolli@codeaurora.org>
Subject: Re: [PATH v3 2/2] ath11k: Use reserved host DDR addresses from DT for PCI devices
Date: Fri, 19 Nov 2021 14:56:45 +0100
Message-ID: <40959183.USSs3XEnCI@sven-l14>
In-Reply-To: <1637244892-27267-2-git-send-email-akolli@codeaurora.org>
References: <1637244892-27267-1-git-send-email-akolli@codeaurora.org> <1637244892-27267-2-git-send-email-akolli@codeaurora.org>

On Thursday, 18 November 2021 15:14:52 CET Anilkumar Kolli wrote:
> +                       if (of_property_read_u32_array(hremote_node, "reg", reg, 4)) {
> +                               ath11k_dbg(ab, ATH11K_DBG_QMI,
> +                                          "qmi fail to get reg from hremote\n");
> +                               return 0;
> +                       }
> +
> +                       start = reg[0] + reg[1];
> +                       size = reg[2] + reg[3];

That cannot be correct. Since when can upper 32 bit and lower 32 bit of an u64 
be combined with a simple "+" and no shifting? And why can you operate on the
reg without getting the address + size cell count?

Kind regards,
	Sven
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