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In-Reply-To: <973fe7f5ec2c474c8a88f8933c7dde83@realtek.com>
From: Ali Ghandour <gandour.ali@gmail.com>
Date: Tue, 12 Dec 2023 07:36:25 +0200
Message-ID: <CAOE0c94tf8y2hv0QHKEiuo5a7Ly=oJAw+g4Uh6BktHOMdbWY1Q@mail.gmail.com>
Subject: Re: Lenovo LOQ rtw_8852be
To: Ping-Ke Shih <pkshih@realtek.com>
Cc: "linux-wireless@vger.kernel.org" <linux-wireless@vger.kernel.org>
Content-Type: text/plain; charset="UTF-8"
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> Please try below workaround patch to ignore the setting. I have tried tha=
t, and
> in my side it still works without obvious problem. I will check internall=
y to
> check how much this can affect. If not, I would ignore this if certain pl=
atform
> like yours can't access PCI space over 0x100.

I was able to connect. Thanks a lot Ping-Ke!

[  609.484727] rtw89_8852be 0000:09:00.0: loaded firmware
rtw89/rtw8852b_fw-1.bin
[  609.484998] rtw89_8852be 0000:09:00.0: enabling device (0000 -> 0003)
[  609.486812] rtw89_8852be 0000:09:00.0: Firmware version 0.29.29.5
(da87cccd), cmd version 0, type 5
[  609.486815] rtw89_8852be 0000:09:00.0: Firmware version 0.29.29.5
(da87cccd), cmd version 0, type 3
[  609.767891] rtw89_8852be 0000:09:00.0: chip rfe_type is 1
[  609.796171] rtw89_8852be 0000:09:00.0: failed to set CLKREQ Delay
[  609.796175] rtw89_8852be 0000:09:00.0: failed to set CLKREQ_L1, ret=3D-2=
2
[  609.796177] rtw89_8852be 0000:09:00.0: failed to read ASPM Delay
[  609.796177] rtw89_8852be 0000:09:00.0: failed to read ASPM Delay
[  609.796178] rtw89_8852be 0000:09:00.0: failed to set ASPM L1, ret=3D-22
[  609.803786] rtw89_8852be 0000:09:00.0 wlp9s0: renamed from wlan0


On Mon, Dec 11, 2023 at 3:53=E2=80=AFAM Ping-Ke Shih <pkshih@realtek.com> w=
rote:
>
>
>
> > -----Original Message-----
> > From: Ali Ghandour <gandour.ali@gmail.com>
> > Sent: Sunday, December 10, 2023 2:24 PM
> > To: Ping-Ke Shih <pkshih@realtek.com>
> > Cc: linux-wireless@vger.kernel.org
> > Subject: Re: Lenovo LOQ rtw_8852be
> >
> > It ended up showing 4096.
>
> But still not work. PCI code is hard to me.
>
> Please try below workaround patch to ignore the setting. I have tried tha=
t, and
> in my side it still works without obvious problem. I will check internall=
y to
> check how much this can affect. If not, I would ignore this if certain pl=
atform
> like yours can't access PCI space over 0x100.
>
>
> @@ -2061,6 +2061,9 @@ static int rtw89_pci_auto_refclk_cal(struct rtw89_d=
ev *rtwdev, bool autook_en)
>         if (chip_id !=3D RTL8852B && chip_id !=3D RTL8851B)
>                 return 0;
>
> +       printk("no auto_refclk_cal\n");
> +       return 0;
> +
>         ret =3D rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_PHY_RATE, &=
val8);
>         if (ret) {
>                 rtw89_err(rtwdev, "[ERR]pci config read %X\n",
>
>
> Ping-Ke
>