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Wed, 31 Jan 2024 21:07:54 GMT Received: from [10.110.47.232] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 31 Jan 2024 13:07:53 -0800 Message-ID: <6b845336-6eaf-407c-86d2-b7676ed58aaf@quicinc.com> Date: Wed, 31 Jan 2024 13:07:53 -0800 Precedence: bulk X-Mailing-List: linux-wireless@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 09/13] wifi: ath12k: subscribe required word mask from rx tlv Content-Language: en-US To: Raj Kumar Bhagat , CC: , Karthikeyan Kathirvel References: <20240129065724.2310207-1-quic_rajkbhag@quicinc.com> <20240129065724.2310207-10-quic_rajkbhag@quicinc.com> From: Jeff Johnson In-Reply-To: <20240129065724.2310207-10-quic_rajkbhag@quicinc.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: V-tVOsM68O0Pe5JEcV2gJRVCDMJYDgAr X-Proofpoint-ORIG-GUID: V-tVOsM68O0Pe5JEcV2gJRVCDMJYDgAr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-31_10,2024-01-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxlogscore=842 malwarescore=0 clxscore=1015 adultscore=0 mlxscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401190000 definitions=main-2401310164 On 1/28/2024 10:57 PM, Raj Kumar Bhagat wrote: > From: Karthikeyan Kathirvel > > Most of the RX descriptors fields are currently not used in the > ath12k driver. Hence add support to selectively subscribe to the > required quad words (64 bits) within msdu_end and mpdu_start of > rx_desc. > > Add compact rx_desc structures and configure the bit mask for Rx TLVs > (msdu_end, mpdu_start, mpdu_end) via registers. With these registers > SW can configure to DMA the partial TLV struct to Rx buffer. > > Each TLV type has its own register to configure the mask value. > The mask value configured in register will indicate if a particular > QWORD has to be written to rx buffer or not i.e., if Nth bit is enabled > in the mask Nth QWORD will be written and it will not be written if the > bit is disabled in mask. While 0th bit indicates whether TLV tag will be > written or not. > > Advantages of Qword subscription of TLVs > - Avoid multiple cache-line misses as the all the required fields > of the TLV are within 128 bytes. > - Memory optimization as TLVs + DATA + SHINFO can fit in 2k buffer > even for 64 bit kernel. > > Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.1.1-00188-QCAHKSWPL_SILICONZ-1 > Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.0.1-00029-QCAHKSWPL_SILICONZ-1 > Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0.c5-00481-QCAHMTSWPL_V1.0_V2.0_SILICONZ-3 > > Signed-off-by: Karthikeyan Kathirvel > Co-developed-by: Raj Kumar Bhagat > Signed-off-by: Raj Kumar Bhagat Acked-by: Jeff Johnson