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Message-ID: <59bf33da-3b5d-b685-f9a8-0593b2d3d5e5@quicinc.com>
Date: Fri, 2 Feb 2024 19:58:51 +0530
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Subject: Re: [PATCH v3 09/13] wifi: ath12k: subscribe required word mask from
 rx tlv
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To: Kalle Valo <kvalo@kernel.org>
CC: <ath12k@lists.infradead.org>, <linux-wireless@vger.kernel.org>,
        Karthikeyan Kathirvel <quic_kathirve@quicinc.com>
References: <20240129065724.2310207-1-quic_rajkbhag@quicinc.com>
 <20240129065724.2310207-10-quic_rajkbhag@quicinc.com>
 <87eddvt5j2.fsf@kernel.org>
From: Raj Kumar Bhagat <quic_rajkbhag@quicinc.com>
In-Reply-To: <87eddvt5j2.fsf@kernel.org>
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On 2/2/2024 5:57 PM, Kalle Valo wrote:
> Raj Kumar Bhagat <quic_rajkbhag@quicinc.com> writes:
> 
>> From: Karthikeyan Kathirvel <quic_kathirve@quicinc.com>
>>
>> Most of the RX descriptors fields are currently not used in the
>> ath12k driver. Hence add support to selectively subscribe to the
>> required quad words (64 bits) within msdu_end and mpdu_start of
>> rx_desc.
>>
>> Add compact rx_desc structures and configure the bit mask for Rx TLVs
>> (msdu_end, mpdu_start, mpdu_end) via registers. With these registers
>> SW can configure to DMA the partial TLV struct to Rx buffer.
>>
>> Each TLV type has its own register to configure the mask value.
>> The mask value configured in register will indicate if a particular
>> QWORD has to be written to rx buffer or not i.e., if Nth bit is enabled
>> in the mask Nth QWORD will be written and it will not be written if the
>> bit is disabled in mask. While 0th bit indicates whether TLV tag will be
>> written or not.
>>
>> Advantages of Qword subscription of TLVs
>> - Avoid multiple cache-line misses as the all the required fields
>> of the TLV are within 128 bytes.
>> - Memory optimization as TLVs + DATA + SHINFO can fit in 2k buffer
>> even for 64 bit kernel.
>>
>> Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.1.1-00188-QCAHKSWPL_SILICONZ-1
>> Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.0.1-00029-QCAHKSWPL_SILICONZ-1
>> Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0.c5-00481-QCAHMTSWPL_V1.0_V2.0_SILICONZ-3
>>
>> Signed-off-by: Karthikeyan Kathirvel <quic_kathirve@quicinc.com>
>> Co-developed-by: Raj Kumar Bhagat <quic_rajkbhag@quicinc.com>
>> Signed-off-by: Raj Kumar Bhagat <quic_rajkbhag@quicinc.com>
> 
> [...]
> 
>> +static void
>> +ath12k_hw_qcn9274_compact_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len)
>> +{
>> +	u32 info = __le32_to_cpu(desc->u.qcn9274_compact.msdu_end.info10);
>> +
>> +	info = u32_replace_bits(info, len, RX_MSDU_END_INFO10_MSDU_LENGTH);
>> +	desc->u.qcn9274_compact.msdu_end.info10 = __cpu_to_le32(info);
>> +}
> 
> Don't we have le32_replace_bits()? That would simplify this function.
> 
> No need to resend because of this, but a followup patch cleaning this up
> would be nice.
> 

Thanks Kalle, for the suggestion. Would send follow-up patch for cleaning
this up.