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Date: Mon, 4 Mar 2024 15:57:42 +0800
From: Kevin Lo <kevlo@kevlo.org>
To: Jeff Johnson <quic_jjohnson@quicinc.com>
Cc: ath11k@lists.infradead.org, Kalle Valo <kvalo@kernel.org>,
	linux-wireless@vger.kernel.org
Subject: Re: [PATCH] wifi: ath11k: adjust a comment to reflect reality
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 <6bdcffce-e657-4990-bd60-5dd67abbb9c9@quicinc.com>
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On Fri, Mar 01, 2024 at 08:16:16AM -0800, Jeff Johnson wrote:
> 
> On 2/26/2024 6:45 PM, Kevin Lo wrote:
> > In ath11k_mhi_set_mhictrl_reset(), I observed on QCA6390/QCN9074/WCN6855,
> > MHISTATUS has SYSERR bit always been set after SOC_GLOBAL_RESET.
> > 
> > Signed-off-by: Kevin Lo <kevlo@kevlo.org>
> > ---
> > diff --git a/drivers/net/wireless/ath/ath11k/mhi.c b/drivers/net/wireless/ath/ath11k/mhi.c
> > index 3de7fa6f88d0..1198e80d9dff 100644
> > --- a/drivers/net/wireless/ath/ath11k/mhi.c
> > +++ b/drivers/net/wireless/ath/ath11k/mhi.c
> > @@ -158,8 +158,8 @@ void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab)
> >  
> >  	ath11k_dbg(ab, ATH11K_DBG_PCI, "mhistatus 0x%x\n", val);
> >  
> > -	/* Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS
> > -	 * has SYSERR bit set and thus need to set MHICTRL_RESET
> > +	/* After SOC_GLOBAL_RESET, MHISTATUS has SYSERR bit
> > +	 * always been set and thus need to set MHICTRL_RESET
> >  	 * to clear SYSERR.
> >  	 */
> >  	ath11k_pcic_write32(ab, MHICTRL, MHICTRL_RESET_MASK);
> 
> Unless you've verified this is always true for every supported chipset

Only PCIe devices trigger the call to ath11k_mhi_set_mhictrl_reset(),
and I've verified this on the QCA6390, QCN9074, and WCN6855 chips.

> I'd rather more accurately say something like:
> After SOC_GLOBAL_RESET, MHISTATUS may still have SYSERR bit set and thus...

Okay, I'll update the comments as per your suggestion, thanks.