2013-04-08 22:52:24

by Gregory CLEMENT

[permalink] [raw]
Subject: [PATCH v3 0/9] ARM: mvebu: Enable LPAE support for Armada XP SoCs

Hello,

The Armada XP SoCs have LPAE support. This is the third patch set
which allows to run kernel on this SoCs with LPAE support.

The biggest changes are the conversion of the device tree file to 64
bits in order to be able to use more than 4GB of memory (without this
the LPAE is pointless).

They are two kinds of change:
- most of the change are on the commit log, according to Arnd
comments.

- the other change was made on the patch "ARM: dts: mvebu: Convert
mvebu device tree files to 64 bits". I managed to not have to use
the 64 bits format for the Armada 370 device tree files.

This patch set won't be the last one, as to ease the merge work of
Jason, I will rebase this series onto his dts branch once he will have
pull the pending commits. Beside this rebase nothing will be changed,
that why I would like to start to get the acked-by from Rob Herring
and Arnd Bergmann for this series(both of them made comments so they
must have an opinion on this last version). I am also submitting the
patch "ARM: mvebu: Enable pj4b on LPAE compilations" to Russell King's
patch system as I didn't receive any complaint about it, and it is a
pretty trivial patch.

This new patch set have been tested on a Armada XP GP board with 8GB
of DRAM with LPAE selected. It have been tested on Armada XP DB board
with 3GB of DRAM with and without LPAE. And also on the Armada 370 DB
board (without LPAE) to check that no regression appeared.

This patch set is based on 3.9-rc6 and is still 3.10 material. The git
branch called lpae-v3 is available at:

https://github.com/MISL-EBU-System-SW/mainline-public.git.

Thanks,

Changelog:
v2 -> v3:

* Pass all the arm architecture word in uppercase in the commit titles.

* Add a commit message to "ARM: dts: mvebu: move all peripherals
inside soc" and move it at first patch of the series.

* Add a commit message to " ARM: dts: mvebu: move all peripherals
inside soc"

* Add a commit message to "ARM: dts: mvebu: introduce internal-regs
node"

* Add more explanation to "ARM: mvebu: Align the internal registers
virtual base to support LPAE"

* In patch "ARM: dts: mvebu: Convert all the mvebu files to use the
range property" thanks to the use of the overload capability of the
device tree format, armada-370 now includes the 32 bit skeleton and
all the armada 370 based dts can remain the same.

v1 -> v2:

* The patch to convert the mvebu device tree files to 64 bits was
split in 3 parts:

- "arm: dts: move all peripherals inside soc" from Thomas

- then "arm: dts: Convert all the mvebu files to use the range
property" which will allow to keep 32 bits addresses for the
internal registers whereas the memory of the system will be 64
bits

- and finally "arm: dts: Convert mvebu device tree files to 64
bits" which was the move to 64 bits itself.

* A new patch was added "arm: dts: introduce internal-regs node" based
on the work of Thomas for the mvebu-mbus driver. It introduce a
'internal-regs' subnode, under which all devices are moved. This is
not really needed for now, but will be for the mvebu-mbus
driver. This generates a lot of code movement since it's indenting
by one more tab all the devices. So it was a good opportunity to fix
all the bad indentation.

* New patch from Thomas "fix cpus section indentation" to finalize the
fixing of the bad indentation

* For DMA transfer, DMA_ZONE was selected instead of DMABOUNCE: all
the DMA transfer are restricted to the low 32 bits address space.

Gregory CLEMENT (4):
ARM: mvebu: Limit the DMA zone when LPAE is selected
ARM: dts: mvebu: Convert all the mvebu files to use the range
property
ARM: dts: mvebu: introduce internal-regs node
ARM: dts: mvebu: Convert mvebu device tree files to 64 bits

Lior Amsalem (3):
ARM: mvebu: Align the internal registers virtual base to support LPAE
ARM: mvebu: Enable pj4b on LPAE compilations
ARM: dts: Add a 64 bits version of the skeleton device tree

Thomas Petazzoni (2):
ARM: dts: mvebu: fix cpus section indentation
ARM: dts: mvebu: move all peripherals inside soc

arch/arm/boot/dts/armada-370-db.dts | 108 ++++-----
arch/arm/boot/dts/armada-370-mirabox.dts | 78 +++----
arch/arm/boot/dts/armada-370-rd.dts | 16 +-
arch/arm/boot/dts/armada-370-xp.dtsi | 253 +++++++++++-----------
arch/arm/boot/dts/armada-370.dtsi | 223 +++++++++----------
arch/arm/boot/dts/armada-xp-db.dts | 156 ++++++-------
arch/arm/boot/dts/armada-xp-gp.dts | 138 ++++++------
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 84 +++----
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 110 +++++-----
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 136 ++++++------
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 198 ++++++++---------
arch/arm/boot/dts/armada-xp.dtsi | 191 ++++++++--------
arch/arm/boot/dts/skeleton64.dtsi | 13 ++
arch/arm/include/debug/mvebu.S | 2 +-
arch/arm/mach-mvebu/Kconfig | 1 +
arch/arm/mach-mvebu/armada-370-xp.h | 2 +-
arch/arm/mm/proc-v7.S | 3 +-
17 files changed, 877 insertions(+), 835 deletions(-)
create mode 100644 arch/arm/boot/dts/skeleton64.dtsi

--
1.7.9.5


2013-04-08 22:52:27

by Gregory CLEMENT

[permalink] [raw]
Subject: [PATCH v3 2/9] ARM: mvebu: Limit the DMA zone when LPAE is selected

When LPAE is activated on Armada XP, all registers and IOs are still
32bit, the 40bit extension is on the CPU to DRAM path (windows) only.
That means that all the DMA transfer are restricted to the low 32 bits
address space. This is limitation is achieved by selecting ZONE_DMA.

Signed-off-by: Gregory CLEMENT <[email protected]>
---
arch/arm/mach-mvebu/Kconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 440b13e..db1bbc8 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -13,6 +13,7 @@ config ARCH_MVEBU
select MVEBU_CLK_CORE
select MVEBU_CLK_CPU
select MVEBU_CLK_GATING
+ select ZONE_DMA if ARM_LPAE

if ARCH_MVEBU

--
1.7.9.5

2013-04-08 22:52:43

by Gregory CLEMENT

[permalink] [raw]
Subject: [PATCH v3 9/9] ARM: dts: mvebu: Convert mvebu device tree files to 64 bits

In order to be able to use more than 4GB of RAM when the LPAE is
activated, the dts must be converted in 64 bits.

Only Armada XP is LPAE capable, but as it shares a common dtsi file
with Armada 370, then the common file include the skeleton64. Thanks
to the use of the overload capability of the device tree format,
armada-370 include the 32 bit skeleton and all the armada 370 based
dts can remain the same.

This was heavily based on the work of Lior Amsalem.

Signed-off-by: Gregory CLEMENT <[email protected]>
---
arch/arm/boot/dts/armada-370-xp.dtsi | 4 ++--
arch/arm/boot/dts/armada-370.dtsi | 2 ++
arch/arm/boot/dts/armada-xp-db.dts | 2 +-
arch/arm/boot/dts/armada-xp-gp.dts | 14 ++++++++------
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 2 +-
5 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 8b9adc6..6a3b418 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -16,7 +16,7 @@
* 370 and Armada XP SoC.
*/

-/include/ "skeleton.dtsi"
+/include/ "skeleton64.dtsi"

/ {
model = "Marvell Armada 370 and XP SoC";
@@ -33,7 +33,7 @@
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&mpic>;
- ranges = <0 0xd0000000 0x100000>;
+ ranges = <0 0 0xd0000000 0x100000>;

internal-regs {
compatible = "simple-bus";
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 9ae6053..7fc18e7 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -16,6 +16,7 @@
*/

/include/ "armada-370-xp.dtsi"
+/include/ "skeleton.dtsi"

/ {
model = "Marvell Armada 370 family SoC";
@@ -28,6 +29,7 @@
};

soc {
+ ranges = <0 0xd0000000 0x100000>;
internal-regs {
[email protected] {
compatible = "marvell,armada-370-xp-system-controller";
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index fbd0f04..a2dd24e 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -26,7 +26,7 @@

memory {
device_type = "memory";
- reg = <0x00000000 0x80000000>; /* 2 GB */
+ reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
};

soc {
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index b0298d7..b022906 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -26,14 +26,16 @@

memory {
device_type = "memory";
-
/*
- * 4 GB of plug-in RAM modules by default but only 3GB
- * are visible, the amount of memory available can be
- * changed by the bootloader according the size of the
- * module actually plugged
+ * 8 GB of plug-in RAM modules by default.The amount
+ * of memory available can be changed by the
+ * bootloader according the size of the module
+ * actually plugged. Only 7GB are usable because
+ * addresses from 0xC0000000 to 0xffffffff are used by
+ * the internal registers of the SoC.
*/
- reg = <0x00000000 0xC0000000>;
+ reg = <0x00000000 0x00000000 0x00000000 0xC0000000>,
+ <0x00000001 0x00000000 0x00000001 0x00000000>;
};

soc {
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index e2eaf4f..1f274e7 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -23,7 +23,7 @@

memory {
device_type = "memory";
- reg = <0x00000000 0xC0000000>; /* 3 GB */
+ reg = <0 0x00000000 0 0xC0000000>; /* 3 GB */
};

soc {
--
1.7.9.5

2013-04-08 22:52:31

by Gregory CLEMENT

[permalink] [raw]
Subject: [PATCH v3 5/9] ARM: dts: Add a 64 bits version of the skeleton device tree

From: Lior Amsalem <[email protected]>

In order to be able to use more than 4GB address-cells and size-cells
have to be set to 2

Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Lior Amsalem <[email protected]>
---
arch/arm/boot/dts/skeleton64.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
create mode 100644 arch/arm/boot/dts/skeleton64.dtsi

diff --git a/arch/arm/boot/dts/skeleton64.dtsi b/arch/arm/boot/dts/skeleton64.dtsi
new file mode 100644
index 0000000..1599415
--- /dev/null
+++ b/arch/arm/boot/dts/skeleton64.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Skeleton device tree in the 64 bits version; the bare minimum
+ * needed to boot; just include and add a compatible value. The
+ * bootloader will typically populate the memory node.
+ */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ chosen { };
+ aliases { };
+ memory { device_type = "memory"; reg = <0 0>; };
+};
--
1.7.9.5

2013-04-08 22:52:42

by Gregory CLEMENT

[permalink] [raw]
Subject: [PATCH v3 8/9] ARM: dts: mvebu: introduce internal-regs node

Introduce a 'internal-regs' subnode, under which all devices are
moved. This is not really needed for now, but will be for the
mvebu-mbus driver. This generates a lot of code movement since it's
indenting by one more tab all the devices. So it was a good
opportunity to fix all the bad indentation.

Signed-off-by: Gregory CLEMENT <[email protected]>
---
arch/arm/boot/dts/armada-370-db.dts | 108 +++++-----
arch/arm/boot/dts/armada-370-mirabox.dts | 78 ++++----
arch/arm/boot/dts/armada-370-rd.dts | 2 +
arch/arm/boot/dts/armada-370-xp.dtsi | 228 +++++++++++-----------
arch/arm/boot/dts/armada-370.dtsi | 219 +++++++++++----------
arch/arm/boot/dts/armada-xp-db.dts | 154 +++++++--------
arch/arm/boot/dts/armada-xp-gp.dts | 124 ++++++------
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 56 +++---
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 80 ++++----
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 80 ++++----
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 196 ++++++++++---------
arch/arm/boot/dts/armada-xp.dtsi | 182 +++++++++--------
12 files changed, 763 insertions(+), 744 deletions(-)

diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 183901c..6c30a9f 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -30,68 +30,70 @@
};

soc {
- [email protected] {
- clock-frequency = <200000000>;
- status = "okay";
- };
- [email protected] {
- nr-ports = <2>;
- status = "okay";
- };
-
- mdio {
- phy0: [email protected] {
- reg = <0>;
+ internal-regs {
+ [email protected] {
+ clock-frequency = <200000000>;
+ status = "okay";
+ };
+ [email protected] {
+ nr-ports = <2>;
+ status = "okay";
};

- phy1: [email protected] {
- reg = <1>;
+ mdio {
+ phy0: [email protected] {
+ reg = <0>;
+ };
+
+ phy1: [email protected] {
+ reg = <1>;
+ };
};
- };

- [email protected] {
- status = "okay";
- phy = <&phy0>;
- phy-mode = "rgmii-id";
- };
- [email protected] {
- status = "okay";
- phy = <&phy1>;
- phy-mode = "rgmii-id";
- };
+ [email protected] {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
+ [email protected] {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+ };

- [email protected] {
- pinctrl-0 = <&sdio_pins1>;
- pinctrl-names = "default";
- /*
- * This device is disabled by default, because
- * using the SD card connector requires
- * changing the default CON40 connector
- * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
- * different connector
- * "DB-88F6710_MPP_RGMII_SD_Jumper".
- */
- status = "disabled";
- /* No CD or WP GPIOs */
- };
+ [email protected] {
+ pinctrl-0 = <&sdio_pins1>;
+ pinctrl-names = "default";
+ /*
+ * This device is disabled by default, because
+ * using the SD card connector requires
+ * changing the default CON40 connector
+ * "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
+ * different connector
+ * "DB-88F6710_MPP_RGMII_SD_Jumper".
+ */
+ status = "disabled";
+ /* No CD or WP GPIOs */
+ };

- [email protected] {
- status = "okay";
- };
+ [email protected] {
+ status = "okay";
+ };

- [email protected] {
- status = "okay";
- };
+ [email protected] {
+ status = "okay";
+ };

- spi0: [email protected] {
- status = "okay";
+ spi0: [email protected] {
+ status = "okay";

- [email protected] {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "mx25l25635e";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <50000000>;
+ [email protected] {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mx25l25635e";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <50000000>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 77dfec7..d4cefc0 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -25,50 +25,52 @@
};

soc {
- [email protected] {
- clock-frequency = <200000000>;
- status = "okay";
- };
- [email protected] {
- clock-frequency = <600000000>;
- status = "okay";
- };
- mdio {
- phy0: [email protected] {
- reg = <0>;
+ internal-regs {
+ [email protected] {
+ clock-frequency = <200000000>;
+ status = "okay";
};
+ [email protected] {
+ clock-frequency = <600000000>;
+ status = "okay";
+ };
+ mdio {
+ phy0: [email protected] {
+ reg = <0>;
+ };

- phy1: [email protected] {
- reg = <1>;
+ phy1: [email protected] {
+ reg = <1>;
+ };
+ };
+ [email protected] {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
+ [email protected] {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
};
- };
- [email protected] {
- status = "okay";
- phy = <&phy0>;
- phy-mode = "rgmii-id";
- };
- [email protected] {
- status = "okay";
- phy = <&phy1>;
- phy-mode = "rgmii-id";
- };

- [email protected] {
- pinctrl-0 = <&sdio_pins3>;
- pinctrl-names = "default";
- status = "okay";
- /*
- * No CD or WP GPIOs: SDIO interface used for
- * Wifi/Bluetooth chip
- */
- };
+ [email protected] {
+ pinctrl-0 = <&sdio_pins3>;
+ pinctrl-names = "default";
+ status = "okay";
+ /*
+ * No CD or WP GPIOs: SDIO interface used for
+ * Wifi/Bluetooth chip
+ */
+ };

- [email protected] {
- status = "okay";
- };
+ [email protected] {
+ status = "okay";
+ };

- [email protected] {
- status = "okay";
+ [email protected] {
+ status = "okay";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index be209020..437dcd2 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -28,6 +28,7 @@
};

soc {
+ internal-regs {
[email protected] {
clock-frequency = <200000000>;
status = "okay";
@@ -72,5 +73,6 @@
[email protected] {
status = "okay";
};
+ };
};
};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 1874655..8b9adc6 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -28,7 +28,6 @@
};
};

-
soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -36,151 +35,156 @@
interrupt-parent = <&mpic>;
ranges = <0 0xd0000000 0x100000>;

- mpic: [email protected] {
+ internal-regs {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mpic: [email protected] {
compatible = "marvell,mpic";
#interrupt-cells = <1>;
#size-cells = <1>;
interrupt-controller;
- };
+ };

- [email protected] {
+ [email protected] {
compatible = "marvell,coherency-fabric";
- reg = <0x20200 0xb0>,
- <0x21810 0x1c>;
- };
+ reg = <0x20200 0xb0>, <0x21810 0x1c>;
+ };

- [email protected] {
+ [email protected] {
compatible = "snps,dw-apb-uart";
reg = <0x12000 0x100>;
reg-shift = <2>;
interrupts = <41>;
reg-io-width = <1>;
status = "disabled";
- };
- [email protected] {
+ };
+ [email protected] {
compatible = "snps,dw-apb-uart";
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <42>;
reg-io-width = <1>;
status = "disabled";
- };
-
- [email protected] {
- compatible = "marvell,armada-370-xp-timer";
- reg = <0x20300 0x30>,
- <0x21040 0x30>;
- interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
- clocks = <&coreclk 2>;
- };
-
- [email protected] {
- compatible = "marvell,armada-addr-decoding-controller";
- reg = <0x20000 0x258>;
- };
-
- [email protected] {
- compatible = "marvell,orion-sata";
- reg = <0xa0000 0x2400>;
- interrupts = <55>;
- clocks = <&gateclk 15>, <&gateclk 30>;
- clock-names = "0", "1";
- status = "disabled";
- };
+ };
+
+ [email protected] {
+ compatible = "marvell,armada-370-xp-timer";
+ reg = <0x20300 0x30>, <0x21040 0x30>;
+ interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
+ clocks = <&coreclk 2>;
+ };
+
+ [email protected] {
+ compatible = "marvell,armada-addr-decoding-controller";
+ reg = <0x20000 0x258>;
+ };
+
+ [email protected] {
+ compatible = "marvell,orion-sata";
+ reg = <0xa0000 0x2400>;
+ interrupts = <55>;
+ clocks = <&gateclk 15>, <&gateclk 30>;
+ clock-names = "0", "1";
+ status = "disabled";
+ };

- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,orion-mdio";
- reg = <0x72004 0x4>;
- };
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x72004 0x4>;
+ };

- [email protected] {
+ [email protected] {
compatible = "marvell,armada-370-neta";
reg = <0x70000 0x2500>;
interrupts = <8>;
clocks = <&gateclk 4>;
status = "disabled";
- };
+ };

- [email protected] {
+ [email protected] {
compatible = "marvell,armada-370-neta";
reg = <0x74000 0x2500>;
interrupts = <10>;
clocks = <&gateclk 3>;
status = "disabled";
- };
-
- i2c0: [email protected] {
- compatible = "marvell,mv64xxx-i2c";
- reg = <0x11000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <31>;
- timeout-ms = <1000>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- i2c1: [email protected] {
- compatible = "marvell,mv64xxx-i2c";
- reg = <0x11100 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <32>;
- timeout-ms = <1000>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
-
- [email protected] {
- compatible = "marvell,orion-rtc";
- reg = <0x10300 0x20>;
- interrupts = <50>;
- };
-
- [email protected] {
- compatible = "marvell,orion-sdio";
- reg = <0xd4000 0x200>;
- interrupts = <54>;
- clocks = <&gateclk 17>;
- status = "disabled";
- };
-
- [email protected] {
- compatible = "marvell,orion-ehci";
- reg = <0x50000 0x500>;
- interrupts = <45>;
- status = "disabled";
- };
-
- [email protected] {
- compatible = "marvell,orion-ehci";
- reg = <0x51000 0x500>;
- interrupts = <46>;
- status = "disabled";
- };
+ };
+
+ i2c0: [email protected] {
+ compatible = "marvell,mv64xxx-i2c";
+ reg = <0x11000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <31>;
+ timeout-ms = <1000>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ i2c1: [email protected] {
+ compatible = "marvell,mv64xxx-i2c";
+ reg = <0x11100 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <32>;
+ timeout-ms = <1000>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ [email protected] {
+ compatible = "marvell,orion-rtc";
+ reg = <0x10300 0x20>;
+ interrupts = <50>;
+ };
+
+ [email protected] {
+ compatible = "marvell,orion-sdio";
+ reg = <0xd4000 0x200>;
+ interrupts = <54>;
+ clocks = <&gateclk 17>;
+ status = "disabled";
+ };

- spi0: [email protected] {
- compatible = "marvell,orion-spi";
- reg = <0x10600 0x28>;
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- interrupts = <30>;
- clocks = <&coreclk 0>;
- status = "disabled";
- };
+ [email protected] {
+ compatible = "marvell,orion-ehci";
+ reg = <0x50000 0x500>;
+ interrupts = <45>;
+ status = "disabled";
+ };

- spi1: [email protected] {
- compatible = "marvell,orion-spi";
- reg = <0x10680 0x28>;
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <1>;
- interrupts = <92>;
- clocks = <&coreclk 0>;
- status = "disabled";
+ [email protected] {
+ compatible = "marvell,orion-ehci";
+ reg = <0x51000 0x500>;
+ interrupts = <46>;
+ status = "disabled";
+ };
+
+ spi0: [email protected] {
+ compatible = "marvell,orion-spi";
+ reg = <0x10600 0x28>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ interrupts = <30>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
+
+ spi1: [email protected] {
+ compatible = "marvell,orion-spi";
+ reg = <0x10680 0x28>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ interrupts = <92>;
+ clocks = <&coreclk 0>;
+ status = "disabled";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 04a8004..9ae6053 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -28,138 +28,137 @@
};

soc {
-
- mpic: [email protected] {
- reg = <0x20a00 0x1d0>,
- <0x21870 0x58>;
- };
-
- [email protected] {
+ internal-regs {
+ [email protected] {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x100>;
- };
+ };

- L2: l2-cache {
- compatible = "marvell,aurora-outer-cache";
- reg = <0xd0008000 0x1000>;
- cache-id-part = <0x100>;
- wt-override;
- };
+ L2: l2-cache {
+ compatible = "marvell,aurora-outer-cache";
+ reg = <0xd0008000 0x1000>;
+ cache-id-part = <0x100>;
+ wt-override;
+ };

- pinctrl {
- compatible = "marvell,mv88f6710-pinctrl";
- reg = <0x18000 0x38>;
+ mpic: [email protected] {
+ reg = <0x20a00 0x1d0>, <0x21870 0x58>;
+ };
+
+ pinctrl {
+ compatible = "marvell,mv88f6710-pinctrl";
+ reg = <0x18000 0x38>;

sdio_pins1: sdio-pins1 {
- marvell,pins = "mpp9", "mpp11", "mpp12",
- "mpp13", "mpp14", "mpp15";
- marvell,function = "sd0";
- };
+ marvell,pins = "mpp9", "mpp11", "mpp12",
+ "mpp13", "mpp14", "mpp15";
+ marvell,function = "sd0";
+ };

sdio_pins2: sdio-pins2 {
- marvell,pins = "mpp47", "mpp48", "mpp49",
- "mpp50", "mpp51", "mpp52";
- marvell,function = "sd0";
- };
+ marvell,pins = "mpp47", "mpp48", "mpp49",
+ "mpp50", "mpp51", "mpp52";
+ marvell,function = "sd0";
+ };

sdio_pins3: sdio-pins3 {
- marvell,pins = "mpp48", "mpp49", "mpp50",
- "mpp51", "mpp52", "mpp53";
- marvell,function = "sd0";
+ marvell,pins = "mpp48", "mpp49", "mpp50",
+ "mpp51", "mpp52", "mpp53";
+ marvell,function = "sd0";
+ };
};
- };
-
- gpio0: [email protected] {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
- ngpios = <32>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupts-cells = <2>;
- interrupts = <82>, <83>, <84>, <85>;
- };
-
- gpio1: [email protected] {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
- ngpios = <32>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupts-cells = <2>;
- interrupts = <87>, <88>, <89>, <90>;
- };
-
- gpio2: [email protected] {
- compatible = "marvell,orion-gpio";
- reg = <0x18180 0x40>;
- ngpios = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupts-cells = <2>;
- interrupts = <91>;
- };
-
- coreclk: [email protected] {
- compatible = "marvell,armada-370-core-clock";
- reg = <0x18230 0x08>;
- #clock-cells = <1>;
- };

- gateclk: [email protected] {
- compatible = "marvell,armada-370-gating-clock";
- reg = <0x18220 0x4>;
- clocks = <&coreclk 0>;
- #clock-cells = <1>;
- };
+ gpio0: [email protected] {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18100 0x40>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <82>, <83>, <84>, <85>;
+ };

- [email protected] {
- compatible = "marvell,orion-xor";
- reg = <0x60800 0x100
- 0x60A00 0x100>;
- status = "okay";
+ gpio1: [email protected] {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18140 0x40>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <87>, <88>, <89>, <90>;
+ };

- xor00 {
- interrupts = <51>;
- dmacap,memcpy;
- dmacap,xor;
+ gpio2: [email protected] {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18180 0x40>;
+ ngpios = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <91>;
};
- xor01 {
- interrupts = <52>;
- dmacap,memcpy;
- dmacap,xor;
- dmacap,memset;
+
+ coreclk: [email protected] {
+ compatible = "marvell,armada-370-core-clock";
+ reg = <0x18230 0x08>;
+ #clock-cells = <1>;
};
- };

- [email protected] {
- compatible = "marvell,orion-xor";
- reg = <0x60900 0x100
- 0x60b00 0x100>;
- status = "okay";
+ gateclk: [email protected] {
+ compatible = "marvell,armada-370-gating-clock";
+ reg = <0x18220 0x4>;
+ clocks = <&coreclk 0>;
+ #clock-cells = <1>;
+ };

- xor10 {
- interrupts = <94>;
- dmacap,memcpy;
- dmacap,xor;
+ [email protected] {
+ compatible = "marvell,orion-xor";
+ reg = <0x60800 0x100
+ 0x60A00 0x100>;
+ status = "okay";
+
+ xor00 {
+ interrupts = <51>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor01 {
+ interrupts = <52>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
};
- xor11 {
- interrupts = <95>;
- dmacap,memcpy;
- dmacap,xor;
- dmacap,memset;
+
+ [email protected] {
+ compatible = "marvell,orion-xor";
+ reg = <0x60900 0x100
+ 0x60b00 0x100>;
+ status = "okay";
+
+ xor10 {
+ interrupts = <94>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor11 {
+ interrupts = <95>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
};
- };

- [email protected] {
- clocks = <&coreclk 0>;
- };
+ [email protected] {
+ clocks = <&coreclk 0>;
+ };

- [email protected] {
- clocks = <&coreclk 0>;
+ [email protected] {
+ clocks = <&coreclk 0>;
+ };
};
-
};
};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 5e2b595..fbd0f04 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -30,95 +30,97 @@
};

soc {
- [email protected] {
- clock-frequency = <250000000>;
- status = "okay";
- };
- [email protected] {
- clock-frequency = <250000000>;
- status = "okay";
- };
- [email protected] {
- clock-frequency = <250000000>;
- status = "okay";
- };
- [email protected] {
- clock-frequency = <250000000>;
- status = "okay";
- };
-
- [email protected] {
- nr-ports = <2>;
- status = "okay";
- };
-
- mdio {
- phy0: [email protected] {
- reg = <0>;
+ internal-regs {
+ [email protected] {
+ clock-frequency = <250000000>;
+ status = "okay";
};
-
- phy1: [email protected] {
- reg = <1>;
+ [email protected] {
+ clock-frequency = <250000000>;
+ status = "okay";
+ };
+ [email protected] {
+ clock-frequency = <250000000>;
+ status = "okay";
+ };
+ [email protected] {
+ clock-frequency = <250000000>;
+ status = "okay";
};

- phy2: [email protected] {
- reg = <25>;
+ [email protected] {
+ nr-ports = <2>;
+ status = "okay";
};

- phy3: [email protected] {
- reg = <27>;
+ mdio {
+ phy0: [email protected] {
+ reg = <0>;
+ };
+
+ phy1: [email protected] {
+ reg = <1>;
+ };
+
+ phy2: [email protected] {
+ reg = <25>;
+ };
+
+ phy3: [email protected] {
+ reg = <27>;
+ };
};
- };

- [email protected] {
- status = "okay";
- phy = <&phy0>;
- phy-mode = "rgmii-id";
- };
- [email protected] {
- status = "okay";
- phy = <&phy1>;
- phy-mode = "rgmii-id";
- };
- [email protected] {
- status = "okay";
- phy = <&phy2>;
- phy-mode = "sgmii";
- };
- [email protected] {
- status = "okay";
- phy = <&phy3>;
- phy-mode = "sgmii";
- };
+ [email protected] {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
+ [email protected] {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+ };
+ [email protected] {
+ status = "okay";
+ phy = <&phy2>;
+ phy-mode = "sgmii";
+ };
+ [email protected] {
+ status = "okay";
+ phy = <&phy3>;
+ phy-mode = "sgmii";
+ };

- [email protected] {
- pinctrl-0 = <&sdio_pins>;
- pinctrl-names = "default";
- status = "okay";
- /* No CD or WP GPIOs */
- };
+ [email protected] {
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ /* No CD or WP GPIOs */
+ };

- [email protected] {
- status = "okay";
- };
+ [email protected] {
+ status = "okay";
+ };

- [email protected] {
- status = "okay";
- };
+ [email protected] {
+ status = "okay";
+ };

- [email protected] {
- status = "okay";
- };
+ [email protected] {
+ status = "okay";
+ };

- spi0: [email protected] {
- status = "okay";
+ spi0: [email protected] {
+ status = "okay";

- [email protected] {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "m25p64";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <20000000>;
+ [email protected] {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p64";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <20000000>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 12b98d3..b0298d7 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -37,76 +37,78 @@
};

soc {
- [email protected] {
- clock-frequency = <250000000>;
- status = "okay";
- };
- [email protected] {
- clock-frequency = <250000000>;
- status = "okay";
- };
- [email protected] {
- clock-frequency = <250000000>;
- status = "okay";
- };
- [email protected] {
- clock-frequency = <250000000>;
- status = "okay";
- };
-
- [email protected] {
- nr-ports = <2>;
- status = "okay";
- };
-
- mdio {
- phy0: [email protected] {
- reg = <16>;
+ internal-regs {
+ [email protected] {
+ clock-frequency = <250000000>;
+ status = "okay";
};
-
- phy1: [email protected] {
- reg = <17>;
+ [email protected] {
+ clock-frequency = <250000000>;
+ status = "okay";
+ };
+ [email protected] {
+ clock-frequency = <250000000>;
+ status = "okay";
+ };
+ [email protected] {
+ clock-frequency = <250000000>;
+ status = "okay";
};

- phy2: [email protected] {
- reg = <18>;
+ [email protected] {
+ nr-ports = <2>;
+ status = "okay";
};

- phy3: [email protected] {
- reg = <19>;
+ mdio {
+ phy0: [email protected] {
+ reg = <16>;
+ };
+
+ phy1: [email protected] {
+ reg = <17>;
+ };
+
+ phy2: [email protected] {
+ reg = <18>;
+ };
+
+ phy3: [email protected] {
+ reg = <19>;
+ };
};
- };

- [email protected] {
- status = "okay";
- phy = <&phy0>;
- phy-mode = "rgmii-id";
- };
- [email protected] {
- status = "okay";
- phy = <&phy1>;
- phy-mode = "rgmii-id";
- };
- [email protected] {
- status = "okay";
- phy = <&phy2>;
- phy-mode = "rgmii-id";
- };
- [email protected] {
- status = "okay";
- phy = <&phy3>;
- phy-mode = "rgmii-id";
- };
+ [email protected] {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
+ [email protected] {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+ };
+ [email protected] {
+ status = "okay";
+ phy = <&phy2>;
+ phy-mode = "rgmii-id";
+ };
+ [email protected] {
+ status = "okay";
+ phy = <&phy3>;
+ phy-mode = "rgmii-id";
+ };

- spi0: [email protected] {
- status = "okay";
+ spi0: [email protected] {
+ status = "okay";

- [email protected] {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "n25q128a13";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <108000000>;
+ [email protected] {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a13";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <108000000>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 757fd42..392f118 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -44,37 +44,39 @@
};

soc {
- pinctrl {
- compatible = "marvell,mv78230-pinctrl";
- reg = <0x18000 0x38>;
+ internal-regs {
+ pinctrl {
+ compatible = "marvell,mv78230-pinctrl";
+ reg = <0x18000 0x38>;

- sdio_pins: sdio-pins {
- marvell,pins = "mpp30", "mpp31", "mpp32",
- "mpp33", "mpp34", "mpp35";
- marvell,function = "sd0";
+ sdio_pins: sdio-pins {
+ marvell,pins = "mpp30", "mpp31", "mpp32",
+ "mpp33", "mpp34", "mpp35";
+ marvell,function = "sd0";
+ };
};
- };

- gpio0: [email protected] {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
- ngpios = <32>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupts-cells = <2>;
- interrupts = <82>, <83>, <84>, <85>;
- };
+ gpio0: [email protected] {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18100 0x40>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <82>, <83>, <84>, <85>;
+ };

- gpio1: [email protected] {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
- ngpios = <17>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupts-cells = <2>;
- interrupts = <87>, <88>, <89>;
+ gpio1: [email protected] {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18140 0x40>;
+ ngpios = <17>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <87>, <88>, <89>;
+ };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 2b572ab..8fb7fea 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -45,56 +45,58 @@
};

soc {
- pinctrl {
- compatible = "marvell,mv78260-pinctrl";
- reg = <0x18000 0x38>;
+ internal-regs {
+ pinctrl {
+ compatible = "marvell,mv78260-pinctrl";
+ reg = <0x18000 0x38>;

- sdio_pins: sdio-pins {
- marvell,pins = "mpp30", "mpp31", "mpp32",
- "mpp33", "mpp34", "mpp35";
- marvell,function = "sd0";
+ sdio_pins: sdio-pins {
+ marvell,pins = "mpp30", "mpp31", "mpp32",
+ "mpp33", "mpp34", "mpp35";
+ marvell,function = "sd0";
+ };
};
- };

- gpio0: [email protected] {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
- ngpios = <32>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupts-cells = <2>;
- interrupts = <82>, <83>, <84>, <85>;
- };
+ gpio0: [email protected] {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18100 0x40>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <82>, <83>, <84>, <85>;
+ };

- gpio1: [email protected] {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
- ngpios = <32>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupts-cells = <2>;
- interrupts = <87>, <88>, <89>, <90>;
- };
+ gpio1: [email protected] {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18140 0x40>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <87>, <88>, <89>, <90>;
+ };

- gpio2: [email protected] {
- compatible = "marvell,orion-gpio";
- reg = <0x18180 0x40>;
- ngpios = <3>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupts-cells = <2>;
- interrupts = <91>;
- };
+ gpio2: [email protected] {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18180 0x40>;
+ ngpios = <3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <91>;
+ };

- [email protected] {
+ [email protected] {
compatible = "marvell,armada-370-neta";
reg = <0x34000 0x2500>;
interrupts = <14>;
clocks = <&gateclk 1>;
status = "disabled";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 79a121f..fa665cb 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -60,56 +60,58 @@
};

soc {
- pinctrl {
- compatible = "marvell,mv78460-pinctrl";
- reg = <0x18000 0x38>;
+ internal-regs {
+ pinctrl {
+ compatible = "marvell,mv78460-pinctrl";
+ reg = <0x18000 0x38>;

- sdio_pins: sdio-pins {
- marvell,pins = "mpp30", "mpp31", "mpp32",
- "mpp33", "mpp34", "mpp35";
- marvell,function = "sd0";
+ sdio_pins: sdio-pins {
+ marvell,pins = "mpp30", "mpp31", "mpp32",
+ "mpp33", "mpp34", "mpp35";
+ marvell,function = "sd0";
+ };
};
- };

- gpio0: [email protected] {
- compatible = "marvell,orion-gpio";
- reg = <0x18100 0x40>;
- ngpios = <32>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupts-cells = <2>;
- interrupts = <82>, <83>, <84>, <85>;
- };
+ gpio0: [email protected] {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18100 0x40>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <82>, <83>, <84>, <85>;
+ };

- gpio1: [email protected] {
- compatible = "marvell,orion-gpio";
- reg = <0x18140 0x40>;
- ngpios = <32>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupts-cells = <2>;
- interrupts = <87>, <88>, <89>, <90>;
- };
+ gpio1: [email protected] {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18140 0x40>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <87>, <88>, <89>, <90>;
+ };

- gpio2: [email protected] {
- compatible = "marvell,orion-gpio";
- reg = <0x18180 0x40>;
- ngpios = <3>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupts-cells = <2>;
- interrupts = <91>;
- };
+ gpio2: [email protected] {
+ compatible = "marvell,orion-gpio";
+ reg = <0x18180 0x40>;
+ ngpios = <3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupts-cells = <2>;
+ interrupts = <91>;
+ };

- [email protected] {
+ [email protected] {
compatible = "marvell,armada-370-neta";
reg = <0x34000 0x2500>;
interrupts = <14>;
clocks = <&gateclk 1>;
status = "disabled";
+ };
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index a7bade4..e2eaf4f 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -27,117 +27,119 @@
};

soc {
- [email protected] {
- clock-frequency = <250000000>;
- status = "okay";
- };
- [email protected] {
- clock-frequency = <250000000>;
- status = "okay";
- };
- pinctrl {
- led_pins: led-pins-0 {
- marvell,pins = "mpp49", "mpp51", "mpp53";
- marvell,function = "gpio";
+ internal-regs {
+ [email protected] {
+ clock-frequency = <250000000>;
+ status = "okay";
};
- };
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins>;
-
- red_led {
- label = "red_led";
- gpios = <&gpio1 17 1>;
- default-state = "off";
+ [email protected] {
+ clock-frequency = <250000000>;
+ status = "okay";
};
-
- yellow_led {
- label = "yellow_led";
- gpios = <&gpio1 19 1>;
- default-state = "off";
+ pinctrl {
+ led_pins: led-pins-0 {
+ marvell,pins = "mpp49", "mpp51", "mpp53";
+ marvell,function = "gpio";
+ };
};
-
- green_led {
- label = "green_led";
- gpios = <&gpio1 21 1>;
- default-state = "off";
- linux,default-trigger = "heartbeat";
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+
+ red_led {
+ label = "red_led";
+ gpios = <&gpio1 17 1>;
+ default-state = "off";
+ };
+
+ yellow_led {
+ label = "yellow_led";
+ gpios = <&gpio1 19 1>;
+ default-state = "off";
+ };
+
+ green_led {
+ label = "green_led";
+ gpios = <&gpio1 21 1>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
};
- };

- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;

- [email protected] {
- label = "Init Button";
- linux,code = <116>;
- gpios = <&gpio1 28 0>;
+ [email protected] {
+ label = "Init Button";
+ linux,code = <116>;
+ gpios = <&gpio1 28 0>;
+ };
};
- };

- mdio {
- phy0: [email protected] {
- reg = <0>;
- };
+ mdio {
+ phy0: [email protected] {
+ reg = <0>;
+ };

- phy1: [email protected] {
- reg = <1>;
- };
+ phy1: [email protected] {
+ reg = <1>;
+ };

- phy2: [email protected] {
- reg = <2>;
- };
+ phy2: [email protected] {
+ reg = <2>;
+ };

- phy3: [email protected] {
- reg = <3>;
+ phy3: [email protected] {
+ reg = <3>;
+ };
};
- };
-
- [email protected] {
- status = "okay";
- phy = <&phy0>;
- phy-mode = "sgmii";
- };
- [email protected] {
- status = "okay";
- phy = <&phy1>;
- phy-mode = "sgmii";
- };
- [email protected] {
- status = "okay";
- phy = <&phy2>;
- phy-mode = "sgmii";
- };
- [email protected] {
- status = "okay";
- phy = <&phy3>;
- phy-mode = "sgmii";
- };
- [email protected] {
- status = "okay";
- clock-frequency = <400000>;
- };
- [email protected] {
- status = "okay";
- clock-frequency = <400000>;

- s35390a: [email protected] {
- compatible = "s35390a";
- reg = <0x30>;
+ [email protected] {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "sgmii";
+ };
+ [email protected] {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "sgmii";
+ };
+ [email protected] {
+ status = "okay";
+ phy = <&phy2>;
+ phy-mode = "sgmii";
+ };
+ [email protected] {
+ status = "okay";
+ phy = <&phy3>;
+ phy-mode = "sgmii";
+ };
+ [email protected] {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+ [email protected] {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ s35390a: [email protected] {
+ compatible = "s35390a";
+ reg = <0x30>;
+ };
+ };
+ [email protected] {
+ nr-ports = <2>;
+ status = "okay";
+ };
+ [email protected] {
+ status = "okay";
+ };
+ [email protected] {
+ status = "okay";
};
- };
- [email protected] {
- nr-ports = <2>;
- status = "okay";
- };
- [email protected] {
- status = "okay";
- };
- [email protected] {
- status = "okay";
};
};
};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 6ca6b7a..2b39dde 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,135 +22,133 @@
model = "Marvell Armada XP family SoC";
compatible = "marvell,armadaxp", "marvell,armada-370-xp";

-
soc {
- L2: l2-cache {
- compatible = "marvell,aurora-system-cache";
- reg = <0x08000 0x1000>;
- cache-id-part = <0x100>;
- wt-override;
- };
+ internal-regs {
+ L2: l2-cache {
+ compatible = "marvell,aurora-system-cache";
+ reg = <0x08000 0x1000>;
+ cache-id-part = <0x100>;
+ wt-override;
+ };

- mpic: [email protected] {
- reg = <0x20a00 0x2d0>,
- <0x21070 0x58>;
- };
+ mpic: [email protected] {
+ reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+ };

- [email protected] {
- compatible = "marvell,armada-370-xp-pmsu";
- reg = <0x22100 0x430>,
- <0x20800 0x20>;
- };
+ [email protected] {
+ compatible = "marvell,armada-370-xp-pmsu";
+ reg = <0x22100 0x430>, <0x20800 0x20>;
+ };

- [email protected] {
+ [email protected] {
compatible = "snps,dw-apb-uart";
reg = <0x12200 0x100>;
reg-shift = <2>;
interrupts = <43>;
reg-io-width = <1>;
status = "disabled";
- };
- [email protected] {
+ };
+ [email protected] {
compatible = "snps,dw-apb-uart";
reg = <0x12300 0x100>;
reg-shift = <2>;
interrupts = <44>;
reg-io-width = <1>;
status = "disabled";
- };
+ };

- [email protected] {
+ [email protected] {
marvell,timer-25Mhz;
- };
+ };

- coreclk: [email protected] {
- compatible = "marvell,armada-xp-core-clock";
- reg = <0x18230 0x08>;
- #clock-cells = <1>;
- };
+ coreclk: [email protected] {
+ compatible = "marvell,armada-xp-core-clock";
+ reg = <0x18230 0x08>;
+ #clock-cells = <1>;
+ };

- cpuclk: [email protected] {
- #clock-cells = <1>;
- compatible = "marvell,armada-xp-cpu-clock";
- reg = <0x18700 0xA0>;
- clocks = <&coreclk 1>;
- };
+ cpuclk: [email protected] {
+ #clock-cells = <1>;
+ compatible = "marvell,armada-xp-cpu-clock";
+ reg = <0x18700 0xA0>;
+ clocks = <&coreclk 1>;
+ };

- gateclk: [email protected] {
- compatible = "marvell,armada-xp-gating-clock";
- reg = <0x18220 0x4>;
- clocks = <&coreclk 0>;
- #clock-cells = <1>;
- };
+ gateclk: [email protected] {
+ compatible = "marvell,armada-xp-gating-clock";
+ reg = <0x18220 0x4>;
+ clocks = <&coreclk 0>;
+ #clock-cells = <1>;
+ };

- [email protected] {
+ [email protected] {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>;
- };
+ };

- [email protected] {
+ [email protected] {
compatible = "marvell,armada-370-neta";
reg = <0x30000 0x2500>;
interrupts = <12>;
clocks = <&gateclk 2>;
status = "disabled";
- };
-
- [email protected] {
- compatible = "marvell,orion-xor";
- reg = <0x60900 0x100
- 0x60b00 0x100>;
- clocks = <&gateclk 22>;
- status = "okay";
-
- xor10 {
- interrupts = <51>;
- dmacap,memcpy;
- dmacap,xor;
- };
- xor11 {
- interrupts = <52>;
- dmacap,memcpy;
- dmacap,xor;
- dmacap,memset;
};
- };
-
- [email protected] {
- compatible = "marvell,orion-xor";
- reg = <0xF0900 0x100
- 0xF0B00 0x100>;
- clocks = <&gateclk 28>;
- status = "okay";

- xor00 {
- interrupts = <94>;
- dmacap,memcpy;
- dmacap,xor;
+ [email protected] {
+ compatible = "marvell,orion-xor";
+ reg = <0x60900 0x100
+ 0x60b00 0x100>;
+ clocks = <&gateclk 22>;
+ status = "okay";
+
+ xor10 {
+ interrupts = <51>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor11 {
+ interrupts = <52>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
};
- xor01 {
- interrupts = <95>;
- dmacap,memcpy;
- dmacap,xor;
- dmacap,memset;
+
+ [email protected] {
+ compatible = "marvell,orion-xor";
+ reg = <0xF0900 0x100
+ 0xF0B00 0x100>;
+ clocks = <&gateclk 28>;
+ status = "okay";
+
+ xor00 {
+ interrupts = <94>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor01 {
+ interrupts = <95>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
};
- };

- [email protected] {
- clocks = <&gateclk 18>;
- };
+ [email protected] {
+ clocks = <&gateclk 18>;
+ };

- [email protected] {
- clocks = <&gateclk 19>;
- };
+ [email protected] {
+ clocks = <&gateclk 19>;
+ };

- [email protected] {
- compatible = "marvell,orion-ehci";
- reg = <0x52000 0x500>;
- interrupts = <47>;
- clocks = <&gateclk 20>;
- status = "disabled";
+ [email protected] {
+ compatible = "marvell,orion-ehci";
+ reg = <0x52000 0x500>;
+ interrupts = <47>;
+ clocks = <&gateclk 20>;
+ status = "disabled";
+ };
};
-
};
};
--
1.7.9.5

2013-04-08 22:52:38

by Gregory CLEMENT

[permalink] [raw]
Subject: [PATCH v3 6/9] ARM: dts: mvebu: move all peripherals inside soc

From: Thomas Petazzoni <[email protected]>

reorganize the .dts and .dtsi files so that all devices are under the
soc { } node (currently some devices such as the interrupt controller,
the L2 cache and a few others are outside).

Signed-off-by: Thomas Petazzoni <[email protected]>
---
arch/arm/boot/dts/armada-370-xp.dtsi | 26 +++++++++++++-------------
arch/arm/boot/dts/armada-370.dtsi | 23 ++++++++++++-----------
arch/arm/boot/dts/armada-xp.dtsi | 32 ++++++++++++++++----------------
3 files changed, 41 insertions(+), 40 deletions(-)

diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 5b70820..bd26c48 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -28,19 +28,6 @@
};
};

- mpic: [email protected] {
- compatible = "marvell,mpic";
- #interrupt-cells = <1>;
- #size-cells = <1>;
- interrupt-controller;
- };
-
- [email protected] {
- compatible = "marvell,coherency-fabric";
- reg = <0xd0020200 0xb0>,
- <0xd0021810 0x1c>;
- };
-
soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -48,6 +35,19 @@
interrupt-parent = <&mpic>;
ranges;

+ mpic: [email protected] {
+ compatible = "marvell,mpic";
+ #interrupt-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ };
+
+ [email protected] {
+ compatible = "marvell,coherency-fabric";
+ reg = <0xd0020200 0xb0>,
+ <0xd0021810 0x1c>;
+ };
+
[email protected] {
compatible = "snps,dw-apb-uart";
reg = <0xd0012000 0x100>;
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index a195deb..9bc092b 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -20,12 +20,6 @@
/ {
model = "Marvell Armada 370 family SoC";
compatible = "marvell,armada370", "marvell,armada-370-xp";
- L2: l2-cache {
- compatible = "marvell,aurora-outer-cache";
- reg = <0xd0008000 0x1000>;
- cache-id-part = <0x100>;
- wt-override;
- };

aliases {
gpio0 = &gpio0;
@@ -33,17 +27,24 @@
gpio2 = &gpio2;
};

- mpic: [email protected] {
- reg = <0xd0020a00 0x1d0>,
- <0xd0021870 0x58>;
- };
-
soc {
+ mpic: [email protected] {
+ reg = <0xd0020a00 0x1d0>,
+ <0xd0021870 0x58>;
+ };
+
[email protected] {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0xd0018200 0x100>;
};

+ L2: l2-cache {
+ compatible = "marvell,aurora-outer-cache";
+ reg = <0xd0008000 0x1000>;
+ cache-id-part = <0x100>;
+ wt-override;
+ };
+
pinctrl {
compatible = "marvell,mv88f6710-pinctrl";
reg = <0xd0018000 0x38>;
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index ca00d83..e644cc5 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,25 +22,25 @@
model = "Marvell Armada XP family SoC";
compatible = "marvell,armadaxp", "marvell,armada-370-xp";

- L2: l2-cache {
- compatible = "marvell,aurora-system-cache";
- reg = <0xd0008000 0x1000>;
- cache-id-part = <0x100>;
- wt-override;
- };
+ soc {
+ L2: l2-cache {
+ compatible = "marvell,aurora-system-cache";
+ reg = <0xd0008000 0x1000>;
+ cache-id-part = <0x100>;
+ wt-override;
+ };

- mpic: [email protected] {
- reg = <0xd0020a00 0x2d0>,
- <0xd0021070 0x58>;
- };
+ mpic: [email protected] {
+ reg = <0xd0020a00 0x2d0>,
+ <0xd0021070 0x58>;
+ };

- [email protected] {
- compatible = "marvell,armada-370-xp-pmsu";
- reg = <0xd0022100 0x430>,
- <0xd0020800 0x20>;
- };
+ [email protected] {
+ compatible = "marvell,armada-370-xp-pmsu";
+ reg = <0xd0022100 0x430>,
+ <0xd0020800 0x20>;
+ };

- soc {
[email protected] {
compatible = "snps,dw-apb-uart";
reg = <0xd0012200 0x100>;
--
1.7.9.5

2013-04-08 22:52:36

by Gregory CLEMENT

[permalink] [raw]
Subject: [PATCH v3 7/9] ARM: dts: mvebu: Convert all the mvebu files to use the range property

This conversion will allow to keep 32 bits addresses for the internal
registers whereas the memory of the system will be 64 bits.
Later it will also ease the move of the mvebu-mbus driver to the
device tree support.

Signed-off-by: Gregory CLEMENT <[email protected]>
---
arch/arm/boot/dts/armada-370-db.dts | 16 ++---
arch/arm/boot/dts/armada-370-mirabox.dts | 14 ++--
arch/arm/boot/dts/armada-370-rd.dts | 14 ++--
arch/arm/boot/dts/armada-370-xp.dtsi | 83 +++++++++++-----------
arch/arm/boot/dts/armada-370.dtsi | 49 ++++++-------
arch/arm/boot/dts/armada-xp-db.dts | 28 ++++----
arch/arm/boot/dts/armada-xp-gp.dts | 20 +++---
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 10 +--
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 18 ++---
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 18 ++---
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 22 +++---
arch/arm/boot/dts/armada-xp.dtsi | 65 ++++++++---------
12 files changed, 180 insertions(+), 177 deletions(-)

diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index e34b280..183901c 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -30,11 +30,11 @@
};

soc {
- [email protected] {
+ [email protected] {
clock-frequency = <200000000>;
status = "okay";
};
- [email protected] {
+ [email protected] {
nr-ports = <2>;
status = "okay";
};
@@ -49,18 +49,18 @@
};
};

- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};

- [email protected] {
+ [email protected] {
pinctrl-0 = <&sdio_pins1>;
pinctrl-names = "default";
/*
@@ -75,15 +75,15 @@
/* No CD or WP GPIOs */
};

- [email protected] {
+ [email protected] {
status = "okay";
};

- [email protected] {
+ [email protected] {
status = "okay";
};

- spi0: [email protected] {
+ spi0: [email protected] {
status = "okay";

[email protected] {
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 3234875..77dfec7 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -25,11 +25,11 @@
};

soc {
- [email protected] {
+ [email protected] {
clock-frequency = <200000000>;
status = "okay";
};
- [email protected] {
+ [email protected] {
clock-frequency = <600000000>;
status = "okay";
};
@@ -42,18 +42,18 @@
reg = <1>;
};
};
- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};

- [email protected] {
+ [email protected] {
pinctrl-0 = <&sdio_pins3>;
pinctrl-names = "default";
status = "okay";
@@ -63,11 +63,11 @@
*/
};

- [email protected] {
+ [email protected] {
status = "okay";
};

- [email protected] {
+ [email protected] {
status = "okay";
};
};
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 070bba4..be209020 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -28,11 +28,11 @@
};

soc {
- [email protected] {
+ [email protected] {
clock-frequency = <200000000>;
status = "okay";
};
- [email protected] {
+ [email protected] {
nr-ports = <2>;
status = "okay";
};
@@ -47,29 +47,29 @@
};
};

- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy0>;
phy-mode = "sgmii";
};
- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};

- [email protected] {
+ [email protected] {
pinctrl-0 = <&sdio_pins1>;
pinctrl-names = "default";
status = "okay";
/* No CD or WP GPIOs */
};

- [email protected] {
+ [email protected] {
status = "okay";
};

- [email protected] {
+ [email protected] {
status = "okay";
};
};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index bd26c48..1874655 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -28,59 +28,60 @@
};
};

+
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&mpic>;
- ranges;
+ ranges = <0 0xd0000000 0x100000>;

- mpic: [email protected] {
- compatible = "marvell,mpic";
- #interrupt-cells = <1>;
- #size-cells = <1>;
- interrupt-controller;
+ mpic: [email protected] {
+ compatible = "marvell,mpic";
+ #interrupt-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
};

- [email protected] {
- compatible = "marvell,coherency-fabric";
- reg = <0xd0020200 0xb0>,
- <0xd0021810 0x1c>;
+ [email protected] {
+ compatible = "marvell,coherency-fabric";
+ reg = <0x20200 0xb0>,
+ <0x21810 0x1c>;
};

- [email protected] {
+ [email protected] {
compatible = "snps,dw-apb-uart";
- reg = <0xd0012000 0x100>;
+ reg = <0x12000 0x100>;
reg-shift = <2>;
interrupts = <41>;
reg-io-width = <1>;
status = "disabled";
};
- [email protected] {
+ [email protected] {
compatible = "snps,dw-apb-uart";
- reg = <0xd0012100 0x100>;
+ reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <42>;
reg-io-width = <1>;
status = "disabled";
};

- [email protected] {
+ [email protected] {
compatible = "marvell,armada-370-xp-timer";
- reg = <0xd0020300 0x30>,
- <0xd0021040 0x30>;
+ reg = <0x20300 0x30>,
+ <0x21040 0x30>;
interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
clocks = <&coreclk 2>;
};

- [email protected] {
+ [email protected] {
compatible = "marvell,armada-addr-decoding-controller";
- reg = <0xd0020000 0x258>;
+ reg = <0x20000 0x258>;
};

- [email protected] {
+ [email protected] {
compatible = "marvell,orion-sata";
- reg = <0xd00a0000 0x2400>;
+ reg = <0xa0000 0x2400>;
interrupts = <55>;
clocks = <&gateclk 15>, <&gateclk 30>;
clock-names = "0", "1";
@@ -91,28 +92,28 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
- reg = <0xd0072004 0x4>;
+ reg = <0x72004 0x4>;
};

- [email protected] {
+ [email protected] {
compatible = "marvell,armada-370-neta";
- reg = <0xd0070000 0x2500>;
+ reg = <0x70000 0x2500>;
interrupts = <8>;
clocks = <&gateclk 4>;
status = "disabled";
};

- [email protected] {
+ [email protected] {
compatible = "marvell,armada-370-neta";
- reg = <0xd0074000 0x2500>;
+ reg = <0x74000 0x2500>;
interrupts = <10>;
clocks = <&gateclk 3>;
status = "disabled";
};

- i2c0: [email protected] {
+ i2c0: [email protected] {
compatible = "marvell,mv64xxx-i2c";
- reg = <0xd0011000 0x20>;
+ reg = <0x11000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <31>;
@@ -121,9 +122,9 @@
status = "disabled";
};

- i2c1: [email protected] {
+ i2c1: [email protected] {
compatible = "marvell,mv64xxx-i2c";
- reg = <0xd0011100 0x20>;
+ reg = <0x11100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <32>;
@@ -134,35 +135,35 @@

[email protected] {
compatible = "marvell,orion-rtc";
- reg = <0xd0010300 0x20>;
+ reg = <0x10300 0x20>;
interrupts = <50>;
};

- [email protected] {
+ [email protected] {
compatible = "marvell,orion-sdio";
- reg = <0xd00d4000 0x200>;
+ reg = <0xd4000 0x200>;
interrupts = <54>;
clocks = <&gateclk 17>;
status = "disabled";
};

- [email protected] {
+ [email protected] {
compatible = "marvell,orion-ehci";
- reg = <0xd0050000 0x500>;
+ reg = <0x50000 0x500>;
interrupts = <45>;
status = "disabled";
};

- [email protected] {
+ [email protected] {
compatible = "marvell,orion-ehci";
- reg = <0xd0051000 0x500>;
+ reg = <0x51000 0x500>;
interrupts = <46>;
status = "disabled";
};

- spi0: [email protected] {
+ spi0: [email protected] {
compatible = "marvell,orion-spi";
- reg = <0xd0010600 0x28>;
+ reg = <0x10600 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
@@ -171,9 +172,9 @@
status = "disabled";
};

- spi1: [email protected] {
+ spi1: [email protected] {
compatible = "marvell,orion-spi";
- reg = <0xd0010680 0x28>;
+ reg = <0x10680 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 9bc092b..04a8004 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -28,14 +28,15 @@
};

soc {
- mpic: [email protected] {
- reg = <0xd0020a00 0x1d0>,
- <0xd0021870 0x58>;
+
+ mpic: [email protected] {
+ reg = <0x20a00 0x1d0>,
+ <0x21870 0x58>;
};

- [email protected] {
+ [email protected] {
compatible = "marvell,armada-370-xp-system-controller";
- reg = <0xd0018200 0x100>;
+ reg = <0x18200 0x100>;
};

L2: l2-cache {
@@ -47,7 +48,7 @@

pinctrl {
compatible = "marvell,mv88f6710-pinctrl";
- reg = <0xd0018000 0x38>;
+ reg = <0x18000 0x38>;

sdio_pins1: sdio-pins1 {
marvell,pins = "mpp9", "mpp11", "mpp12",
@@ -68,9 +69,9 @@
};
};

- gpio0: [email protected] {
+ gpio0: [email protected] {
compatible = "marvell,orion-gpio";
- reg = <0xd0018100 0x40>;
+ reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
@@ -79,9 +80,9 @@
interrupts = <82>, <83>, <84>, <85>;
};

- gpio1: [email protected] {
+ gpio1: [email protected] {
compatible = "marvell,orion-gpio";
- reg = <0xd0018140 0x40>;
+ reg = <0x18140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
@@ -90,9 +91,9 @@
interrupts = <87>, <88>, <89>, <90>;
};

- gpio2: [email protected] {
+ gpio2: [email protected] {
compatible = "marvell,orion-gpio";
- reg = <0xd0018180 0x40>;
+ reg = <0x18180 0x40>;
ngpios = <2>;
gpio-controller;
#gpio-cells = <2>;
@@ -101,23 +102,23 @@
interrupts = <91>;
};

- coreclk: [email protected] {
+ coreclk: [email protected] {
compatible = "marvell,armada-370-core-clock";
- reg = <0xd0018230 0x08>;
+ reg = <0x18230 0x08>;
#clock-cells = <1>;
};

- gateclk: [email protected] {
+ gateclk: [email protected] {
compatible = "marvell,armada-370-gating-clock";
- reg = <0xd0018220 0x4>;
+ reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};

- [email protected] {
+ [email protected] {
compatible = "marvell,orion-xor";
- reg = <0xd0060800 0x100
- 0xd0060A00 0x100>;
+ reg = <0x60800 0x100
+ 0x60A00 0x100>;
status = "okay";

xor00 {
@@ -133,10 +134,10 @@
};
};

- [email protected] {
+ [email protected] {
compatible = "marvell,orion-xor";
- reg = <0xd0060900 0x100
- 0xd0060b00 0x100>;
+ reg = <0x60900 0x100
+ 0x60b00 0x100>;
status = "okay";

xor10 {
@@ -152,11 +153,11 @@
};
};

- [email protected] {
+ [email protected] {
clocks = <&coreclk 0>;
};

- [email protected] {
+ [email protected] {
clocks = <&coreclk 0>;
};

diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index e83505e..5e2b595 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -30,24 +30,24 @@
};

soc {
- [email protected] {
+ [email protected] {
clock-frequency = <250000000>;
status = "okay";
};
- [email protected] {
+ [email protected] {
clock-frequency = <250000000>;
status = "okay";
};
- [email protected] {
+ [email protected] {
clock-frequency = <250000000>;
status = "okay";
};
- [email protected] {
+ [email protected] {
clock-frequency = <250000000>;
status = "okay";
};

- [email protected] {
+ [email protected] {
nr-ports = <2>;
status = "okay";
};
@@ -70,47 +70,47 @@
};
};

- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy2>;
phy-mode = "sgmii";
};
- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy3>;
phy-mode = "sgmii";
};

- [email protected] {
+ [email protected] {
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
status = "okay";
/* No CD or WP GPIOs */
};

- [email protected] {
+ [email protected] {
status = "okay";
};

- [email protected] {
+ [email protected] {
status = "okay";
};

- [email protected] {
+ [email protected] {
status = "okay";
};

- spi0: [email protected] {
+ spi0: [email protected] {
status = "okay";

[email protected] {
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 1c8afe2..12b98d3 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -37,24 +37,24 @@
};

soc {
- [email protected] {
+ [email protected] {
clock-frequency = <250000000>;
status = "okay";
};
- [email protected] {
+ [email protected] {
clock-frequency = <250000000>;
status = "okay";
};
- [email protected] {
+ [email protected] {
clock-frequency = <250000000>;
status = "okay";
};
- [email protected] {
+ [email protected] {
clock-frequency = <250000000>;
status = "okay";
};

- [email protected] {
+ [email protected] {
nr-ports = <2>;
status = "okay";
};
@@ -77,28 +77,28 @@
};
};

- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy2>;
phy-mode = "rgmii-id";
};
- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy3>;
phy-mode = "rgmii-id";
};

- spi0: [email protected] {
+ spi0: [email protected] {
status = "okay";

[email protected] {
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 50180eb..757fd42 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -46,7 +46,7 @@
soc {
pinctrl {
compatible = "marvell,mv78230-pinctrl";
- reg = <0xd0018000 0x38>;
+ reg = <0x18000 0x38>;

sdio_pins: sdio-pins {
marvell,pins = "mpp30", "mpp31", "mpp32",
@@ -55,9 +55,9 @@
};
};

- gpio0: [email protected] {
+ gpio0: [email protected] {
compatible = "marvell,orion-gpio";
- reg = <0xd0018100 0x40>;
+ reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
@@ -66,9 +66,9 @@
interrupts = <82>, <83>, <84>, <85>;
};

- gpio1: [email protected] {
+ gpio1: [email protected] {
compatible = "marvell,orion-gpio";
- reg = <0xd0018140 0x40>;
+ reg = <0x18140 0x40>;
ngpios = <17>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 3c433d5..2b572ab 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -47,7 +47,7 @@
soc {
pinctrl {
compatible = "marvell,mv78260-pinctrl";
- reg = <0xd0018000 0x38>;
+ reg = <0x18000 0x38>;

sdio_pins: sdio-pins {
marvell,pins = "mpp30", "mpp31", "mpp32",
@@ -56,9 +56,9 @@
};
};

- gpio0: [email protected] {
+ gpio0: [email protected] {
compatible = "marvell,orion-gpio";
- reg = <0xd0018100 0x40>;
+ reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
@@ -67,9 +67,9 @@
interrupts = <82>, <83>, <84>, <85>;
};

- gpio1: [email protected] {
+ gpio1: [email protected] {
compatible = "marvell,orion-gpio";
- reg = <0xd0018140 0x40>;
+ reg = <0x18140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
@@ -78,9 +78,9 @@
interrupts = <87>, <88>, <89>, <90>;
};

- gpio2: [email protected] {
+ gpio2: [email protected] {
compatible = "marvell,orion-gpio";
- reg = <0xd0018180 0x40>;
+ reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
@@ -89,9 +89,9 @@
interrupts = <91>;
};

- [email protected] {
+ [email protected] {
compatible = "marvell,armada-370-neta";
- reg = <0xd0034000 0x2500>;
+ reg = <0x34000 0x2500>;
interrupts = <14>;
clocks = <&gateclk 1>;
status = "disabled";
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 4c38e942..79a121f 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -62,7 +62,7 @@
soc {
pinctrl {
compatible = "marvell,mv78460-pinctrl";
- reg = <0xd0018000 0x38>;
+ reg = <0x18000 0x38>;

sdio_pins: sdio-pins {
marvell,pins = "mpp30", "mpp31", "mpp32",
@@ -71,9 +71,9 @@
};
};

- gpio0: [email protected] {
+ gpio0: [email protected] {
compatible = "marvell,orion-gpio";
- reg = <0xd0018100 0x40>;
+ reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
@@ -82,9 +82,9 @@
interrupts = <82>, <83>, <84>, <85>;
};

- gpio1: [email protected] {
+ gpio1: [email protected] {
compatible = "marvell,orion-gpio";
- reg = <0xd0018140 0x40>;
+ reg = <0x18140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
@@ -93,9 +93,9 @@
interrupts = <87>, <88>, <89>, <90>;
};

- gpio2: [email protected] {
+ gpio2: [email protected] {
compatible = "marvell,orion-gpio";
- reg = <0xd0018180 0x40>;
+ reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
@@ -104,9 +104,9 @@
interrupts = <91>;
};

- [email protected] {
+ [email protected] {
compatible = "marvell,armada-370-neta";
- reg = <0xd0034000 0x2500>;
+ reg = <0x34000 0x2500>;
interrupts = <14>;
clocks = <&gateclk 1>;
status = "disabled";
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 3818a82..a7bade4 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -27,11 +27,11 @@
};

soc {
- [email protected] {
+ [email protected] {
clock-frequency = <250000000>;
status = "okay";
};
- [email protected] {
+ [email protected] {
clock-frequency = <250000000>;
status = "okay";
};
@@ -96,31 +96,31 @@
};
};

- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy0>;
phy-mode = "sgmii";
};
- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy1>;
phy-mode = "sgmii";
};
- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy2>;
phy-mode = "sgmii";
};
- [email protected] {
+ [email protected] {
status = "okay";
phy = <&phy3>;
phy-mode = "sgmii";
};
- [email protected] {
+ [email protected] {
status = "okay";
clock-frequency = <400000>;
};
- [email protected] {
+ [email protected] {
status = "okay";
clock-frequency = <400000>;

@@ -129,14 +129,14 @@
reg = <0x30>;
};
};
- [email protected] {
+ [email protected] {
nr-ports = <2>;
status = "okay";
};
- [email protected] {
+ [email protected] {
status = "okay";
};
- [email protected] {
+ [email protected] {
status = "okay";
};
};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index e644cc5..6ca6b7a 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,83 +22,84 @@
model = "Marvell Armada XP family SoC";
compatible = "marvell,armadaxp", "marvell,armada-370-xp";

+
soc {
L2: l2-cache {
compatible = "marvell,aurora-system-cache";
- reg = <0xd0008000 0x1000>;
+ reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
wt-override;
};

- mpic: [email protected] {
- reg = <0xd0020a00 0x2d0>,
- <0xd0021070 0x58>;
+ mpic: [email protected] {
+ reg = <0x20a00 0x2d0>,
+ <0x21070 0x58>;
};

- [email protected] {
+ [email protected] {
compatible = "marvell,armada-370-xp-pmsu";
- reg = <0xd0022100 0x430>,
- <0xd0020800 0x20>;
+ reg = <0x22100 0x430>,
+ <0x20800 0x20>;
};

- [email protected] {
+ [email protected] {
compatible = "snps,dw-apb-uart";
- reg = <0xd0012200 0x100>;
+ reg = <0x12200 0x100>;
reg-shift = <2>;
interrupts = <43>;
reg-io-width = <1>;
status = "disabled";
};
- [email protected] {
+ [email protected] {
compatible = "snps,dw-apb-uart";
- reg = <0xd0012300 0x100>;
+ reg = <0x12300 0x100>;
reg-shift = <2>;
interrupts = <44>;
reg-io-width = <1>;
status = "disabled";
};

- [email protected] {
+ [email protected] {
marvell,timer-25Mhz;
};

- coreclk: [email protected] {
+ coreclk: [email protected] {
compatible = "marvell,armada-xp-core-clock";
- reg = <0xd0018230 0x08>;
+ reg = <0x18230 0x08>;
#clock-cells = <1>;
};

- cpuclk: [email protected] {
+ cpuclk: [email protected] {
#clock-cells = <1>;
compatible = "marvell,armada-xp-cpu-clock";
- reg = <0xd0018700 0xA0>;
+ reg = <0x18700 0xA0>;
clocks = <&coreclk 1>;
};

- gateclk: [email protected] {
+ gateclk: [email protected] {
compatible = "marvell,armada-xp-gating-clock";
- reg = <0xd0018220 0x4>;
+ reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};

- [email protected] {
+ [email protected] {
compatible = "marvell,armada-370-xp-system-controller";
- reg = <0xd0018200 0x500>;
+ reg = <0x18200 0x500>;
};

- [email protected] {
+ [email protected] {
compatible = "marvell,armada-370-neta";
- reg = <0xd0030000 0x2500>;
+ reg = <0x30000 0x2500>;
interrupts = <12>;
clocks = <&gateclk 2>;
status = "disabled";
};

- [email protected] {
+ [email protected] {
compatible = "marvell,orion-xor";
- reg = <0xd0060900 0x100
- 0xd0060b00 0x100>;
+ reg = <0x60900 0x100
+ 0x60b00 0x100>;
clocks = <&gateclk 22>;
status = "okay";

@@ -115,10 +116,10 @@
};
};

- [email protected] {
+ [email protected] {
compatible = "marvell,orion-xor";
- reg = <0xd00F0900 0x100
- 0xd00F0B00 0x100>;
+ reg = <0xF0900 0x100
+ 0xF0B00 0x100>;
clocks = <&gateclk 28>;
status = "okay";

@@ -135,17 +136,17 @@
};
};

- [email protected]d0050000 {
+ [email protected] {
clocks = <&gateclk 18>;
};

- [email protected] {
+ [email protected] {
clocks = <&gateclk 19>;
};

- [email protected] {
+ [email protected] {
compatible = "marvell,orion-ehci";
- reg = <0xd0052000 0x500>;
+ reg = <0x52000 0x500>;
interrupts = <47>;
clocks = <&gateclk 20>;
status = "disabled";
--
1.7.9.5

2013-04-08 22:52:29

by Gregory CLEMENT

[permalink] [raw]
Subject: [PATCH v3 4/9] ARM: mvebu: Enable pj4b on LPAE compilations

From: Lior Amsalem <[email protected]>

pj4b cpus are LPAE capable so enable them on LPAE compilations

Signed-off-by: Lior Amsalem <[email protected]>
Tested-by: Franklin <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
---
arch/arm/mm/proc-v7.S | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index f584d3f..d75dc67 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -402,6 +402,8 @@ __v7_ca9mp_proc_info:
__v7_proc __v7_ca9mp_setup
.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info

+#endif /* CONFIG_ARM_LPAE */
+
/*
* Marvell PJ4B processor.
*/
@@ -411,7 +413,6 @@ __v7_pj4b_proc_info:
.long 0xfffffff0
__v7_proc __v7_pj4b_setup
.size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
-#endif /* CONFIG_ARM_LPAE */

/*
* ARM Ltd. Cortex A7 processor.
--
1.7.9.5

2013-04-08 22:54:26

by Gregory CLEMENT

[permalink] [raw]
Subject: [PATCH v3 3/9] ARM: mvebu: Align the internal registers virtual base to support LPAE

From: Lior Amsalem <[email protected]>

In order to be able to support the LPAE, the internal registers
virtual base must be aligned to 2MB. In LPAE section size is 2MB, in
earlyprintk we map the internal registers and it must be section
aligned.

Signed-off-by: Lior Amsalem <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
---
arch/arm/include/debug/mvebu.S | 2 +-
arch/arm/mach-mvebu/armada-370-xp.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S
index 865c6d0..df191af 100644
--- a/arch/arm/include/debug/mvebu.S
+++ b/arch/arm/include/debug/mvebu.S
@@ -12,7 +12,7 @@
*/

#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE 0xfeb00000
+#define ARMADA_370_XP_REGS_VIRT_BASE 0xfec00000

.macro addruart, rp, rv, tmp
ldr \rp, =ARMADA_370_XP_REGS_PHYS_BASE
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index c6a7d74..c49c08e 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -16,7 +16,7 @@
#define __MACH_ARMADA_370_XP_H

#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfeb00000)
+#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfec00000)
#define ARMADA_370_XP_REGS_SIZE SZ_1M

#ifdef CONFIG_SMP
--
1.7.9.5

2013-04-08 22:54:47

by Gregory CLEMENT

[permalink] [raw]
Subject: [PATCH v3 1/9] ARM: dts: mvebu: fix cpus section indentation

From: Thomas Petazzoni <[email protected]>

Align the cpu node indentation with the rest of the file

[gc]: added a commit description
Signed-off-by: Thomas Petazzoni <[email protected]>
---
arch/arm/boot/dts/armada-xp-mv78230.dtsi | 28 ++++++++--------
arch/arm/boot/dts/armada-xp-mv78260.dtsi | 28 ++++++++--------
arch/arm/boot/dts/armada-xp-mv78460.dtsi | 54 +++++++++++++++---------------
3 files changed, 55 insertions(+), 55 deletions(-)

diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index f56c405..50180eb 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -25,22 +25,22 @@
};

cpus {
- #address-cells = <1>;
- #size-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;

- [email protected] {
- device_type = "cpu";
- compatible = "marvell,sheeva-v7";
- reg = <0>;
- clocks = <&cpuclk 0>;
- };
+ [email protected] {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <0>;
+ clocks = <&cpuclk 0>;
+ };

- [email protected] {
- device_type = "cpu";
- compatible = "marvell,sheeva-v7";
- reg = <1>;
- clocks = <&cpuclk 1>;
- };
+ [email protected] {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <1>;
+ clocks = <&cpuclk 1>;
+ };
};

soc {
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index f8f2b78..3c433d5 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -26,22 +26,22 @@
};

cpus {
- #address-cells = <1>;
- #size-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;

- [email protected] {
- device_type = "cpu";
- compatible = "marvell,sheeva-v7";
- reg = <0>;
- clocks = <&cpuclk 0>;
- };
+ [email protected] {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <0>;
+ clocks = <&cpuclk 0>;
+ };

- [email protected] {
- device_type = "cpu";
- compatible = "marvell,sheeva-v7";
- reg = <1>;
- clocks = <&cpuclk 1>;
- };
+ [email protected] {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <1>;
+ clocks = <&cpuclk 1>;
+ };
};

soc {
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 936c25d..4c38e942 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -27,36 +27,36 @@


cpus {
- #address-cells = <1>;
- #size-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;

- [email protected] {
- device_type = "cpu";
- compatible = "marvell,sheeva-v7";
- reg = <0>;
- clocks = <&cpuclk 0>;
- };
+ [email protected] {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <0>;
+ clocks = <&cpuclk 0>;
+ };

- [email protected] {
- device_type = "cpu";
- compatible = "marvell,sheeva-v7";
- reg = <1>;
- clocks = <&cpuclk 1>;
- };
+ [email protected] {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <1>;
+ clocks = <&cpuclk 1>;
+ };

- [email protected] {
- device_type = "cpu";
- compatible = "marvell,sheeva-v7";
- reg = <2>;
- clocks = <&cpuclk 2>;
- };
+ [email protected] {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <2>;
+ clocks = <&cpuclk 2>;
+ };

- [email protected] {
- device_type = "cpu";
- compatible = "marvell,sheeva-v7";
- reg = <3>;
- clocks = <&cpuclk 3>;
- };
+ [email protected] {
+ device_type = "cpu";
+ compatible = "marvell,sheeva-v7";
+ reg = <3>;
+ clocks = <&cpuclk 3>;
+ };
};

soc {
@@ -112,4 +112,4 @@
status = "disabled";
};
};
- };
+};
--
1.7.9.5

2013-04-11 18:07:55

by Jason Cooper

[permalink] [raw]
Subject: Re: [PATCH v3 2/9] ARM: mvebu: Limit the DMA zone when LPAE is selected

On Tue, Apr 09, 2013 at 12:52:10AM +0200, Gregory CLEMENT wrote:
> When LPAE is activated on Armada XP, all registers and IOs are still
> 32bit, the 40bit extension is on the CPU to DRAM path (windows) only.
> That means that all the DMA transfer are restricted to the low 32 bits
> address space. This is limitation is achieved by selecting ZONE_DMA.
>
> Signed-off-by: Gregory CLEMENT <[email protected]>
> ---
> arch/arm/mach-mvebu/Kconfig | 1 +
> 1 file changed, 1 insertion(+)

Applied to mvebu/soc

thx,

Jason.

2013-04-11 18:08:28

by Jason Cooper

[permalink] [raw]
Subject: Re: [PATCH v3 3/9] ARM: mvebu: Align the internal registers virtual base to support LPAE

On Tue, Apr 09, 2013 at 12:52:11AM +0200, Gregory CLEMENT wrote:
> From: Lior Amsalem <[email protected]>
>
> In order to be able to support the LPAE, the internal registers
> virtual base must be aligned to 2MB. In LPAE section size is 2MB, in
> earlyprintk we map the internal registers and it must be section
> aligned.
>
> Signed-off-by: Lior Amsalem <[email protected]>
> Signed-off-by: Gregory CLEMENT <[email protected]>
> ---
> arch/arm/include/debug/mvebu.S | 2 +-
> arch/arm/mach-mvebu/armada-370-xp.h | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)

Applied to mvebu/soc

thx,

Jason.

2013-04-11 18:08:56

by Jason Cooper

[permalink] [raw]
Subject: Re: [PATCH v3 4/9] ARM: mvebu: Enable pj4b on LPAE compilations

On Tue, Apr 09, 2013 at 12:52:12AM +0200, Gregory CLEMENT wrote:
> From: Lior Amsalem <[email protected]>
>
> pj4b cpus are LPAE capable so enable them on LPAE compilations
>
> Signed-off-by: Lior Amsalem <[email protected]>
> Tested-by: Franklin <[email protected]>
> Signed-off-by: Gregory CLEMENT <[email protected]>
> ---
> arch/arm/mm/proc-v7.S | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)

Applied to mvebu/soc

thx,

Jason.

2013-04-11 20:41:49

by Gregory CLEMENT

[permalink] [raw]
Subject: Re: [PATCH v3 4/9] ARM: mvebu: Enable pj4b on LPAE compilations

Hi Jason,

On 04/11/2013 08:08 PM, Jason Cooper wrote:
> On Tue, Apr 09, 2013 at 12:52:12AM +0200, Gregory CLEMENT wrote:
>> From: Lior Amsalem <[email protected]>
>>
>> pj4b cpus are LPAE capable so enable them on LPAE compilations
>>
>> Signed-off-by: Lior Amsalem <[email protected]>
>> Tested-by: Franklin <[email protected]>
>> Signed-off-by: Gregory CLEMENT <[email protected]>
>> ---
>> arch/arm/mm/proc-v7.S | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> Applied to mvebu/soc
>
> thx,
>
> Jason.
>

First thanks for pulling all these patches.

However, this one should go through Russell's git tree. Or at least
you need his acked-by. I have already submit this patch on Russell
patch system. Unfortunately Russell told that he will be away for
around one week.

This patch is needed to have LPAE support, but all the other patches
don't depend on it. That means that if you applied all the other
patches it won't break anything even if at the end this patch is not
merged. But I really hope that Russell will be able to apply this
patch to his git tree.

Thanks

--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

2013-04-11 20:48:36

by Gregory CLEMENT

[permalink] [raw]
Subject: Re: [PATCH v3 5/9] ARM: dts: Add a 64 bits version of the skeleton device tree

Hi Jason,

On 04/11/2013 08:12 PM, Jason Cooper wrote:
> On Tue, Apr 09, 2013 at 12:52:13AM +0200, Gregory CLEMENT wrote:
>> From: Lior Amsalem <[email protected]>
>>
>> In order to be able to use more than 4GB address-cells and size-cells
>> have to be set to 2
>>
>> Signed-off-by: Gregory CLEMENT <[email protected]>
>> Signed-off-by: Lior Amsalem <[email protected]>
>> ---
>> arch/arm/boot/dts/skeleton64.dtsi | 13 +++++++++++++
>> 1 file changed, 13 insertions(+)
>> create mode 100644 arch/arm/boot/dts/skeleton64.dtsi
>
> Applied to mvebu/dt
>
> Gregory,
>
> Once I can pull in Thomas' pci work, you'll just need to rebase patches
> 1, and 6 - 9 against mvebu/dt.
>

Yes sure! When did you plan to pull the dts part of Thomas' pci work?
Is there still anything left to prevent to pull this part?

Thanks,
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

2013-04-12 00:05:05

by Jason Cooper

[permalink] [raw]
Subject: Re: [PATCH v3 4/9] ARM: mvebu: Enable pj4b on LPAE compilations

On Thu, Apr 11, 2013 at 10:41:34PM +0200, Gregory CLEMENT wrote:
> Hi Jason,
>
> On 04/11/2013 08:08 PM, Jason Cooper wrote:
> > On Tue, Apr 09, 2013 at 12:52:12AM +0200, Gregory CLEMENT wrote:
> >> From: Lior Amsalem <[email protected]>
> >>
> >> pj4b cpus are LPAE capable so enable them on LPAE compilations
> >>
> >> Signed-off-by: Lior Amsalem <[email protected]>
> >> Tested-by: Franklin <[email protected]>
> >> Signed-off-by: Gregory CLEMENT <[email protected]>
> >> ---
> >> arch/arm/mm/proc-v7.S | 3 ++-
> >> 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > Applied to mvebu/soc
> >
...
>
> However, this one should go through Russell's git tree. Or at least
> you need his acked-by. I have already submit this patch on Russell
> patch system. Unfortunately Russell told that he will be away for
> around one week.
>
> This patch is needed to have LPAE support, but all the other patches
> don't depend on it. That means that if you applied all the other
> patches it won't break anything even if at the end this patch is not
> merged. But I really hope that Russell will be able to apply this
> patch to his git tree.

ok, thanks for catching this before I sent the PR. I'll drop it.

thx,

Jason.

2013-04-12 00:09:59

by Jason Cooper

[permalink] [raw]
Subject: Re: [PATCH v3 5/9] ARM: dts: Add a 64 bits version of the skeleton device tree

On Tue, Apr 09, 2013 at 12:52:13AM +0200, Gregory CLEMENT wrote:
> From: Lior Amsalem <[email protected]>
>
> In order to be able to use more than 4GB address-cells and size-cells
> have to be set to 2
>
> Signed-off-by: Gregory CLEMENT <[email protected]>
> Signed-off-by: Lior Amsalem <[email protected]>
> ---
> arch/arm/boot/dts/skeleton64.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
> create mode 100644 arch/arm/boot/dts/skeleton64.dtsi

Applied to mvebu/dt

Gregory,

Once I can pull in Thomas' pci work, you'll just need to rebase patches
1, and 6 - 9 against mvebu/dt.

thx,

Jason.

2013-04-12 00:15:06

by Jason Cooper

[permalink] [raw]
Subject: Re: [PATCH v3 5/9] ARM: dts: Add a 64 bits version of the skeleton device tree

On Thu, Apr 11, 2013 at 10:48:27PM +0200, Gregory CLEMENT wrote:
> Hi Jason,
>
> On 04/11/2013 08:12 PM, Jason Cooper wrote:
> > On Tue, Apr 09, 2013 at 12:52:13AM +0200, Gregory CLEMENT wrote:
> >> From: Lior Amsalem <[email protected]>
> >>
> >> In order to be able to use more than 4GB address-cells and size-cells
> >> have to be set to 2
> >>
> >> Signed-off-by: Gregory CLEMENT <[email protected]>
> >> Signed-off-by: Lior Amsalem <[email protected]>
> >> ---
> >> arch/arm/boot/dts/skeleton64.dtsi | 13 +++++++++++++
> >> 1 file changed, 13 insertions(+)
> >> create mode 100644 arch/arm/boot/dts/skeleton64.dtsi
> >
> > Applied to mvebu/dt
> >
> > Gregory,
> >
> > Once I can pull in Thomas' pci work, you'll just need to rebase patches
> > 1, and 6 - 9 against mvebu/dt.
> >
>
> Yes sure! When did you plan to pull the dts part of Thomas' pci work?
> Is there still anything left to prevent to pull this part?

Good call, I'm just waiting for the last Ack Thomas said he needs on the
first of/pci patch. My head has been fuzzy with hay fever for the past
three days. Obviously, I can pull in the dts portion.

thx,

Jason.