by Zanoni, Paulo R

[permalink] [raw]

Subject: Re: [PATCH v2 07/10] drm/i915/gen9: Make skl_pipe_wm_get_hw_state() reusable

Em Sex, 2016-10-14 às 17:31 -0400, Lyude escreveu:
> There's not much of a reason this should have the locations to read
> out
> the hardware state hardcoded, so allow the caller to specify the
> location and add this function to intel_drv.h. As well, we're going
> to
> need this function to be reusable for the next patch.
>
> Changes since v1:
> - Fix accidental behavior change in the code that Paulo pointed out

Reviewed-by: Paulo Zanoni <[email protected]>

I just submitted v4 of patch 5 solving the conflicts I created. With
that + this review, we can merge this series. If you give me an ack on
patch 5 I can just go and merge these, so we can move to Maarten's
series and then later to Mahesh's series.

>
> Signed-off-by: Lyude <[email protected]>
> Cc: Maarten Lankhorst <[email protected]>
> Cc: Ville Syrjälä <[email protected]>
> Cc: Matt Roper <[email protected]
> Cc: Paulo Zanoni <[email protected]>
> ---
> drivers/gpu/drm/i915/intel_drv.h |  2 ++
> drivers/gpu/drm/i915/intel_pm.c  | 28 ++++++++++++++++++----------
> 2 files changed, 20 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index a85ce2c..7036310 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1756,6 +1756,8 @@ void ilk_wm_get_hw_state(struct drm_device
> *dev);
> void skl_wm_get_hw_state(struct drm_device *dev);
> void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
>   struct skl_ddb_allocation *ddb /* out */);
> +void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
> +       struct skl_pipe_wm *out);
> bool intel_can_enable_sagv(struct drm_atomic_state *state);
> int intel_enable_sagv(struct drm_i915_private *dev_priv);
> int intel_disable_sagv(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 2fe851e..6eaeb87 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4288,15 +4288,13 @@ static inline void
> skl_wm_level_from_reg_val(uint32_t val,
> PLANE_WM_LINES_MASK;
> }
>
> -static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
> +void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
> +       struct skl_pipe_wm *out)
> {
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - struct intel_crtc_state *cstate = to_intel_crtc_state(crtc-
> >state);
> struct intel_plane *intel_plane;
> - struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
> struct skl_plane_wm *wm;
> enum pipe pipe = intel_crtc->pipe;
> int level, id, max_level;
> @@ -4306,7 +4304,7 @@ static void skl_pipe_wm_get_hw_state(struct
> drm_crtc *crtc)
>
> for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
> id = skl_wm_plane_id(intel_plane);
> - wm = &cstate->wm.skl.optimal.planes[id];
> + wm = &out->planes[id];
>
> for (level = 0; level <= max_level; level++) {
> if (id != PLANE_CURSOR)
> @@ -4328,20 +4326,30 @@ static void skl_pipe_wm_get_hw_state(struct
> drm_crtc *crtc)
> if (!intel_crtc->active)
> return;
>
> - hw->dirty_pipes |= drm_crtc_mask(crtc);
> - active->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
> - intel_crtc->wm.active.skl = *active;
> + out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
> }
>
> void skl_wm_get_hw_state(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> + struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
> struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
> struct drm_crtc *crtc;
> + struct intel_crtc *intel_crtc;
> + struct intel_crtc_state *cstate;
>
> skl_ddb_get_hw_state(dev_priv, ddb);
> - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
> - skl_pipe_wm_get_hw_state(crtc);
> + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
> {
> + intel_crtc = to_intel_crtc(crtc);
> + cstate = to_intel_crtc_state(crtc->state);
> +
> + skl_pipe_wm_get_hw_state(crtc, &cstate-
> >wm.skl.optimal);
> +
> + if (intel_crtc->active) {
> + hw->dirty_pipes |= drm_crtc_mask(crtc);
> + intel_crtc->wm.active.skl = cstate-
> >wm.skl.optimal;
> + }
> + }
>
> if (dev_priv->active_crtcs) {
> /* Fully recompute DDB on first atomic commit */