Hi all,
The Allwinner A83T is an octacore A7 divided in two clusters of 4 A7,
each cluster having its own regulator and clock.
Let's add the OPPs for each cluster so that we can use cpufreq on this SoC.
The operating points were found in Allwinner BSP and fex files and have
been tested on a TBS A711 with cpuburn and cpufreq-ljt-stress-test.
Note that there are a few OPPs that are missing:
1608000000Hz with 920000mV
1800000000Hz with 1000000mV
2016000000Hz with 1080000mV
These OPPs are pretty unstable but it might be due to the SoC quickly
overheating (till the board completely shuts down).
It seems[1] impossible to reach those frequencies with none or passive
cooling, so better leave them out by default.
It's still possible to add those OPPs on a per-board basis though.
[1] http://linux-sunxi.org/User:Tkaiser#First_steps_with_Banana_Pi_M3
Thanks,
Quentin
Quentin Schulz (3):
ARM: dts: sun8i: a83t: add cpu0 and cpu100 labels
ARM: dts: sun8i: a711: set regulator for each cluster of CPUs
ARM: dts: sun8i: a83t: add stable OPP tables and CPUfreq
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 9 ++-
arch/arm/boot/dts/sun8i-a83t.dtsi | 122 ++++++++++++++++++++++-
2 files changed, 129 insertions(+), 2 deletions(-)
base-commit: 827ad482fda17d0de5df5116fda827cd3671e62e
--
git-series 0.9.1
The Allwinner A83T is a SoC with two clusters of 4 A7, each cluster
having its own regulator and clock.
The regulators are board-specific, thus we need labels for cpu0 and
cpu100 so that we can use references to these nodes from the board
header file.
Signed-off-by: Quentin Schulz <[email protected]>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 46ae4fa..016d22f 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -60,7 +60,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
@@ -84,7 +84,7 @@
reg = <3>;
};
- cpu@100 {
+ cpu100: cpu@100 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0x100>;
--
git-series 0.9.1
The Allwinner A83T is an octacore A7 divided in two clusters of 4 A7,
each cluster having its own regulator and clock.
The operating points were found in Allwinner BSP and fex files.
Note that there are a few OPPs that are missing:
1608000000Hz with 920000mV
1800000000Hz with 1000000mV
2016000000Hz with 1080000mV
These OPPs are pretty unstable but it might be due to the SoC quickly
overheating (till the board completely shuts down).
It seems impossible to reach those frequencies with none or passive
cooling, so better leave them out by default.
It's still possible to add those OPPs on a per-board basis though.
Signed-off-by: Quentin Schulz <[email protected]>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 118 +++++++++++++++++++++++++++++++-
1 file changed, 118 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 016d22f..05d5dd7 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -56,55 +56,173 @@
#address-cells = <1>;
#size-cells = <1>;
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-864000000 {
+ opp-hz = /bits/ 64 <864000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-912000000 {
+ opp-hz = /bits/ 64 <912000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1128000000 {
+ opp-hz = /bits/ 64 <1128000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };
+
+ cpu1_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-864000000 {
+ opp-hz = /bits/ 64 <864000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-912000000 {
+ opp-hz = /bits/ 64 <912000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1128000000 {
+ opp-hz = /bits/ 64 <1128000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <840000>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
+ clocks = <&ccu CLK_C0CPUX>;
+ clock-names = "cpu";
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
reg = <0>;
};
cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
reg = <1>;
};
cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
reg = <2>;
};
cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
reg = <3>;
};
cpu100: cpu@100 {
+ clocks = <&ccu CLK_C1CPUX>;
+ clock-names = "cpu";
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu1_opp_table>;
reg = <0x100>;
};
cpu@101 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu1_opp_table>;
reg = <0x101>;
};
cpu@102 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu1_opp_table>;
reg = <0x102>;
};
cpu@103 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ operating-points-v2 = <&cpu1_opp_table>;
reg = <0x103>;
};
};
--
git-series 0.9.1
Hello,
On Wed, 28 Feb 2018 14:11:21 +0100, Quentin Schulz wrote:
> @@ -136,6 +144,7 @@
> * An USB-2 hub is connected here, which also means we don't need to
> * enable the OHCI controller.
> */
> +
> &ehci0 {
> status = "okay";
> };
Spurious change.
Thomas
--
Thomas Petazzoni, CTO, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
The Allwinner A83T is a SoC with two clusters of 4 A7 which have a
different clock and regulator.
Set the CPU regulator.
Signed-off-by: Quentin Schulz <[email protected]>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index 1de362f..d65162c 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -128,6 +128,14 @@
};
};
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu100 {
+ cpu-supply = <®_dcdc3>;
+};
+
&de {
status = "okay";
};
@@ -136,6 +144,7 @@
* An USB-2 hub is connected here, which also means we don't need to
* enable the OHCI controller.
*/
+
&ehci0 {
status = "okay";
};
--
git-series 0.9.1
On Wed, Feb 28, 2018 at 02:11:19PM +0100, Quentin Schulz wrote:
> Hi all,
>
> The Allwinner A83T is an octacore A7 divided in two clusters of 4 A7,
> each cluster having its own regulator and clock.
>
> Let's add the OPPs for each cluster so that we can use cpufreq on this SoC.
>
> The operating points were found in Allwinner BSP and fex files and have
> been tested on a TBS A711 with cpuburn and cpufreq-ljt-stress-test.
>
> Note that there are a few OPPs that are missing:
>
> 1608000000Hz with 920000mV
> 1800000000Hz with 1000000mV
> 2016000000Hz with 1080000mV
>
> These OPPs are pretty unstable but it might be due to the SoC quickly
> overheating (till the board completely shuts down).
> It seems[1] impossible to reach those frequencies with none or passive
> cooling, so better leave them out by default.
>
> It's still possible to add those OPPs on a per-board basis though.
>
> [1] http://linux-sunxi.org/User:Tkaiser#First_steps_with_Banana_Pi_M3
Applied all three. The patch 3/3 wasn't ordered properly, so I fixed
it, and I removed the newline pointed out by Thomas.
Thanks!
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com