This series adds support for the PCIe controller and PHY found in the Qualcomm
platform QCS404.
Bjorn Andersson (7):
clk: gcc-qcs404: Add PCIe resets
dt-bindings: phy: Add binding for Qualcomm PCIe2 PHY
phy: qcom: Add Qualcomm PCIe2 PHY driver
PCI: qcom: Use clk_bulk API for 2.4.0 controllers
dt-bindings: PCI: qcom: Add QCS404 to the binding
PCI: qcom: Add QCS404 PCIe controller support
arm64: dts: qcom: qcs404: Add PCIe related nodes
.../devicetree/bindings/pci/qcom,pcie.txt | 25 +-
.../bindings/phy/qcom-pcie2-phy.txt | 40 +++
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 25 ++
arch/arm64/boot/dts/qcom/qcs404.dtsi | 67 ++++
drivers/clk/qcom/gcc-qcs404.c | 7 +
drivers/pci/controller/dwc/pcie-qcom.c | 108 +++---
drivers/phy/qualcomm/Kconfig | 8 +
drivers/phy/qualcomm/Makefile | 1 +
drivers/phy/qualcomm/phy-qcom-pcie2.c | 331 ++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-qcs404.h | 7 +
10 files changed, 558 insertions(+), 61 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
create mode 100644 drivers/phy/qualcomm/phy-qcom-pcie2.c
--
2.18.0
The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, add these to
the platform dtsi and enable them for the EVB with the perst gpio
and analog supplies defined.
Signed-off-by: Bjorn Andersson <[email protected]>
---
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 25 +++++++++
arch/arm64/boot/dts/qcom/qcs404.dtsi | 67 ++++++++++++++++++++++++
2 files changed, 92 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 50b3589c7f15..579ddaf4f5fa 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -21,6 +21,22 @@
};
};
+&pcie {
+ status = "ok";
+
+ perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&perst_state>;
+};
+
+&pcie_phy {
+ status = "ok";
+
+ vdda-vp-supply = <&vreg_l3_1p05>;
+ vdda-vph-supply = <&vreg_l5_1p8>;
+};
+
&remoteproc_adsp {
status = "ok";
};
@@ -137,6 +153,15 @@
};
&tlmm {
+ perst_state: perst {
+ pins = "gpio43";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+
sdc1_on: sdc1-on {
clk {
pins = "sdc1_clk";
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 76699435c8bd..7b219865ba7e 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -3,6 +3,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
interrupt-parent = <&intc>;
@@ -377,6 +378,7 @@
compatible = "qcom,gcc-qcs404";
reg = <0x01800000 0x80000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
assigned-clock-rates = <19200000>;
@@ -405,6 +407,21 @@
#interrupt-cells = <4>;
};
+ pcie_phy: phy@7786000 {
+ compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
+ reg = <0x07786000 0xb8>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+ resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
+ <&gcc GCC_PCIE_0_PIPE_ARES>;
+ reset-names = "phy", "pipe";
+
+ clock-output-names = "pcie_0_pipe_clk";
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
sdcc1: sdcc@7804000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
@@ -771,6 +788,56 @@
status = "disabled";
};
};
+
+ pcie: pci@10000000 {
+ compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
+ reg = <0x10000000 0xf1d
+ 0x10000f20 0xa8
+ 0x07780000 0x2000
+ 0x10001000 0x2000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x81000000 0 0 0x10003000 0 0x00010000 /* I/O */
+ 0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
+
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
+ clock-names = "iface", "aux", "master_bus", "slave_bus";
+
+ resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
+ <&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE_0_BCR>,
+ <&gcc GCC_PCIE_0_AHB_ARES>;
+ reset-names = "axi_m",
+ "axi_s",
+ "axi_m_sticky",
+ "pipe_sticky",
+ "pwr",
+ "ahb";
+
+ phys = <&pcie_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
};
timer {
--
2.18.0
The Qualcomm QCS404 platform contains a PCIe controller, add this to the
Qualcomm PCI binding document. The controller is the same version as the
one used in IPQ4019, but the PHY part is described separately, hence the
difference in clocks and resets.
Signed-off-by: Bjorn Andersson <[email protected]>
---
.../devicetree/bindings/pci/qcom,pcie.txt | 25 +++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 1fd703bd73e0..ada80b01bf0c 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -10,6 +10,7 @@
- "qcom,pcie-msm8996" for msm8996 or apq8096
- "qcom,pcie-ipq4019" for ipq4019
- "qcom,pcie-ipq8074" for ipq8074
+ - "qcom,pcie-qcs404" for qcs404
- reg:
Usage: required
@@ -116,6 +117,15 @@
- "ahb" AHB clock
- "aux" Auxiliary clock
+- clock-names:
+ Usage: required for qcs404
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "iface" AHB clock
+ - "aux" Auxiliary clock
+ - "master_bus" AXI Master clock
+ - "slave_bus" AXI Slave clock
+
- resets:
Usage: required
Value type: <prop-encoded-array>
@@ -167,6 +177,17 @@
- "ahb" AHB Reset
- "axi_m_sticky" AXI Master Sticky reset
+- reset-names:
+ Usage: required for qcs404
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "axi_m" AXI Master reset
+ - "axi_s" AXI Slave reset
+ - "axi_m_sticky" AXI Master Sticky reset
+ - "pipe_sticky" PIPE sticky reset
+ - "pwr" PWR reset
+ - "ahb" AHB reset
+
- power-domains:
Usage: required for apq8084 and msm8996/apq8096
Value type: <prop-encoded-array>
@@ -195,12 +216,12 @@
Definition: A phandle to the PCIe endpoint power supply
- phys:
- Usage: required for apq8084
+ Usage: required for apq8084 and qcs404
Value type: <phandle>
Definition: List of phandle(s) as listed in phy-names property
- phy-names:
- Usage: required for apq8084
+ Usage: required for apq8084 and qcs404
Value type: <stringlist>
Definition: Should contain "pciephy"
--
2.18.0
The Qualcomm PCIe2 PHY is based on design from Synopsys and found in
several different platforms where the QMP PHY isn't used.
Signed-off-by: Bjorn Andersson <[email protected]>
---
drivers/phy/qualcomm/Kconfig | 8 +
drivers/phy/qualcomm/Makefile | 1 +
drivers/phy/qualcomm/phy-qcom-pcie2.c | 331 ++++++++++++++++++++++++++
3 files changed, 340 insertions(+)
create mode 100644 drivers/phy/qualcomm/phy-qcom-pcie2.c
diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
index 32f7d34eb784..0edb5316972f 100644
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -24,6 +24,14 @@ config PHY_QCOM_IPQ806X_SATA
depends on OF
select GENERIC_PHY
+config PHY_QCOM_PCIE2
+ tristate "Qualcomm PCIe PHY Driver"
+ depends on OF && COMMON_CLK && (ARCH_QCOM || COMPILE_TEST)
+ select GENERIC_PHY
+ help
+ Enable this to support the Qualcomm PCIe PHY, used with the Synopsys
+ based PCIe controller.
+
config PHY_QCOM_QMP
tristate "Qualcomm QMP PHY Driver"
depends on OF && COMMON_CLK && (ARCH_QCOM || COMPILE_TEST)
diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
index c56efd3af205..283251d6a5d9 100644
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
+obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
diff --git a/drivers/phy/qualcomm/phy-qcom-pcie2.c b/drivers/phy/qualcomm/phy-qcom-pcie2.c
new file mode 100644
index 000000000000..2fa891c18b6f
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-pcie2.c
@@ -0,0 +1,331 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019, Linaro Ltd.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/phy/phy.h>
+
+#define PCIE20_PARF_PHY_STTS 0x3c
+#define PCIE2_PHY_RESET_CTRL 0x44
+#define PCIE20_PARF_PHY_REFCLK_CTRL2 0xa0
+#define PCIE20_PARF_PHY_REFCLK_CTRL3 0xa4
+#define PCIE20_PARF_PCS_SWING_CTRL1 0x88
+#define PCIE20_PARF_PCS_SWING_CTRL2 0x8c
+#define PCIE20_PARF_PCS_DEEMPH1 0x74
+#define PCIE20_PARF_PCS_DEEMPH2 0x78
+#define PCIE20_PARF_PCS_DEEMPH3 0x7c
+#define PCIE20_PARF_CONFIGBITS 0x84
+#define PCIE20_PARF_PHY_CTRL3 0x94
+#define PCIE20_PARF_PCS_CTRL 0x80
+
+#define TX_AMP_VAL 120
+#define PHY_RX0_EQ_GEN1_VAL 0
+#define PHY_RX0_EQ_GEN2_VAL 4
+#define TX_DEEMPH_GEN1_VAL 24
+#define TX_DEEMPH_GEN2_3_5DB_VAL 26
+#define TX_DEEMPH_GEN2_6DB_VAL 36
+#define PHY_TX0_TERM_OFFST_VAL 0
+
+struct qcom_phy {
+ struct device *dev;
+ void __iomem *base;
+
+ struct regulator_bulk_data vregs[2];
+
+ struct reset_control *phy_reset;
+ struct reset_control *pipe_reset;
+ struct clk *pipe_clk;
+};
+
+static int qcom_pcie2_phy_init(struct phy *phy)
+{
+ struct qcom_phy *qphy = phy_get_drvdata(phy);
+ int ret;
+
+ ret = reset_control_deassert(qphy->phy_reset);
+ if (ret) {
+ dev_err(qphy->dev, "cannot deassert pipe reset\n");
+ return ret;
+ }
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
+ if (ret)
+ reset_control_assert(qphy->phy_reset);
+
+ return ret;
+}
+
+static int qcom_pcie2_phy_power_on(struct phy *phy)
+{
+ struct qcom_phy *qphy = phy_get_drvdata(phy);
+ int ret;
+ u32 val;
+
+ /* Program REF_CLK source */
+ val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
+ val &= ~BIT(1);
+ writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
+
+ usleep_range(1000, 2000);
+
+ /* Don't use PAD for refclock */
+ val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
+ val &= ~BIT(0);
+ writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
+
+ /* Program SSP ENABLE */
+ val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
+ val |= BIT(0);
+ writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
+
+ usleep_range(1000, 2000);
+
+ /* Assert Phy SW Reset */
+ val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
+ val |= BIT(0);
+ writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
+
+ /* Program Tx Amplitude */
+ val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
+ val &= ~0x7f;
+ val |= TX_AMP_VAL;
+ writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
+
+ val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
+ val &= ~0x7f;
+ val |= TX_AMP_VAL;
+ writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
+
+ /* Program De-Emphasis */
+ val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH1);
+ val &= ~0x3f;
+ val |= TX_DEEMPH_GEN2_6DB_VAL;
+ writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH1);
+
+ val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH2);
+ val &= ~0x3f;
+ val |= TX_DEEMPH_GEN2_3_5DB_VAL;
+ writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH2);
+
+ val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH3);
+ val &= ~0x3f;
+ val |= TX_DEEMPH_GEN1_VAL;
+ writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH3);
+
+ /* Program Rx_Eq */
+ val = readl(qphy->base + PCIE20_PARF_CONFIGBITS);
+ val &= ~0x7;
+ val |= PHY_RX0_EQ_GEN2_VAL;
+ writel(val, qphy->base + PCIE20_PARF_CONFIGBITS);
+
+ /* Program Tx0_term_offset */
+ val = readl(qphy->base + PCIE20_PARF_PHY_CTRL3);
+ val &= ~0x1f;
+ val |= PHY_TX0_TERM_OFFST_VAL;
+ writel(val, qphy->base + PCIE20_PARF_PHY_CTRL3);
+
+ /* disable Tx2Rx Loopback */
+ val = readl(qphy->base + PCIE20_PARF_PCS_CTRL);
+ val &= ~BIT(1);
+ writel(val, qphy->base + PCIE20_PARF_PCS_CTRL);
+
+ /* De-assert Phy SW Reset */
+ val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
+ val &= ~BIT(0);
+ writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
+
+ usleep_range(1000, 2000);
+
+ ret = reset_control_deassert(qphy->pipe_reset);
+ if (ret) {
+ dev_err(qphy->dev, "cannot deassert pipe reset\n");
+ goto out;
+ }
+
+ clk_set_rate(qphy->pipe_clk, 250000000);
+
+ ret = clk_prepare_enable(qphy->pipe_clk);
+ if (ret) {
+ dev_err(qphy->dev, "failed to enable pipe clock\n");
+ goto out;
+ }
+
+ ret = readl_poll_timeout(qphy->base + PCIE20_PARF_PHY_STTS, val,
+ !(val & BIT(0)), 1000, 10);
+ if (ret)
+ dev_err(qphy->dev, "phy initialization failed\n");
+
+out:
+ return ret;
+}
+
+static int qcom_pcie2_phy_power_off(struct phy *phy)
+{
+ struct qcom_phy *qphy = phy_get_drvdata(phy);
+ u32 val;
+
+ val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
+ val |= BIT(0);
+ writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
+
+ clk_disable_unprepare(qphy->pipe_clk);
+ reset_control_assert(qphy->pipe_reset);
+
+ return 0;
+}
+
+static int qcom_pcie2_phy_exit(struct phy *phy)
+{
+ struct qcom_phy *qphy = phy_get_drvdata(phy);
+
+ regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
+ reset_control_assert(qphy->phy_reset);
+
+ return 0;
+}
+
+static const struct phy_ops qcom_pcie2_ops = {
+ .init = qcom_pcie2_phy_init,
+ .power_on = qcom_pcie2_phy_power_on,
+ .power_off = qcom_pcie2_phy_power_off,
+ .exit = qcom_pcie2_phy_exit,
+ .owner = THIS_MODULE,
+};
+
+/*
+ * Register a fixed rate pipe clock.
+ *
+ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
+ * controls it. The <s>_pipe_clk coming out of the GCC is requested
+ * by the PHY driver for its operations.
+ * We register the <s>_pipe_clksrc here. The gcc driver takes care
+ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
+ * Below picture shows this relationship.
+ *
+ * +---------------+
+ * | PHY block |<<---------------------------------------+
+ * | | |
+ * | +-------+ | +-----+ |
+ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
+ * clk | +-------+ | +-----+
+ * +---------------+
+ */
+static int phy_pipe_clk_register(struct qcom_phy *qphy)
+{
+ struct device_node *np = qphy->dev->of_node;
+ struct clk_fixed_rate *fixed;
+ struct clk_init_data init = { };
+ int ret;
+
+ ret = of_property_read_string(np, "clock-output-names", &init.name);
+ if (ret) {
+ dev_err(qphy->dev, "%s: No clock-output-names\n", np->name);
+ return ret;
+ }
+
+ fixed = devm_kzalloc(qphy->dev, sizeof(*fixed), GFP_KERNEL);
+ if (!fixed)
+ return -ENOMEM;
+
+ init.ops = &clk_fixed_rate_ops;
+
+ /* controllers using QMP phys use 250MHz pipe clock interface */
+ fixed->fixed_rate = 250000000;
+ fixed->hw.init = &init;
+
+ return devm_clk_hw_register(qphy->dev, &fixed->hw);
+}
+
+static int qcom_pcie2_phy_probe(struct platform_device *pdev)
+{
+ struct phy_provider *phy_provider;
+ struct qcom_phy *qphy;
+ struct resource *res;
+ struct device *dev = &pdev->dev;
+ struct phy *phy;
+ int ret;
+
+ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
+ if (!qphy)
+ return -ENOMEM;
+
+ qphy->dev = dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ qphy->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(qphy->base))
+ return PTR_ERR(qphy->base);
+
+ ret = phy_pipe_clk_register(qphy);
+ if (ret) {
+ dev_err(dev, "failed to register pipe_clk\n");
+ return ret;
+ }
+
+ qphy->vregs[0].supply = "vdda-vp";
+ qphy->vregs[1].supply = "vdda-vph";
+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(qphy->vregs), qphy->vregs);
+ if (ret < 0)
+ return ret;
+
+ qphy->pipe_clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(qphy->pipe_clk)) {
+ dev_err(dev, "failed to acquire pipe clock\n");
+ return PTR_ERR(qphy->pipe_clk);
+ }
+
+ qphy->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
+ if (IS_ERR(qphy->phy_reset)) {
+ dev_err(dev, "failed to acquire phy reset\n");
+ return PTR_ERR(qphy->phy_reset);
+ }
+
+ qphy->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
+ if (IS_ERR(qphy->pipe_reset)) {
+ dev_err(dev, "failed to acquire pipe reset\n");
+ return PTR_ERR(qphy->pipe_reset);
+ }
+
+ phy = devm_phy_create(dev, dev->of_node, &qcom_pcie2_ops);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "failed to create phy\n");
+ return PTR_ERR(phy);
+ }
+
+ phy_set_drvdata(phy, qphy);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(phy_provider))
+ dev_err(dev, "failed to register phy provider\n");
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id qcom_pcie2_phy_match_table[] = {
+ { .compatible = "qcom,pcie2-phy" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, qcom_pcie2_phy_match_table);
+
+static struct platform_driver qcom_pcie2_phy_driver = {
+ .probe = qcom_pcie2_phy_probe,
+ .driver = {
+ .name = "qcom-pcie2-phy",
+ .of_match_table = qcom_pcie2_phy_match_table,
+ },
+};
+
+module_platform_driver(qcom_pcie2_phy_driver);
+
+MODULE_DESCRIPTION("Qualcomm PCIe PHY driver");
+MODULE_LICENSE("GPL v2");
--
2.18.0
The Qualcomm PCIe2 PHY is a Synopsys based PCIe PHY found in a number of
Qualcomm platforms, add a binding to describe this.
Signed-off-by: Bjorn Andersson <[email protected]>
---
.../bindings/phy/qcom-pcie2-phy.txt | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
new file mode 100644
index 000000000000..7da02f9d78c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
@@ -0,0 +1,40 @@
+Qualcomm PCIe2 PHY controller
+=============================
+
+The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
+platforms.
+
+Required properties:
+ - compatible: compatible list, should be:
+ "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
+
+ - reg: offset and length of the PHY register set.
+ - #phy-cells: must be 0.
+
+ - clocks: a clock-specifier pair for the "pipe" clock
+
+ - vdda-vp-supply: phandle to low voltage regulator
+ - vdda-vph-supply: phandle to high voltage regulator
+
+ - resets: reset-specifier pairs for the "phy" and "pipe" resets
+ - reset-names: list of resets, should contain:
+ "phy" and "pipe"
+
+ - clock-output-names: name of the outgoing clock signal from the PHY PLL
+
+Example:
+ phy@7786000 {
+ compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
+ reg = <0x07786000 0xb8>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+ resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
+ <&gcc GCC_PCIE_0_PIPE_ARES>;
+ reset-names = "phy", "pipe";
+
+ vdda-vp-supply = <&vreg_l3_1p05>;
+ vdda-vph-supply = <&vreg_l5_1p8>;
+
+ clock-output-names = "pcie_0_pipe_clk";
+ #phy-cells = <0>;
+ };
--
2.18.0
The QCS404 platform contains a PCIe controller of version 2.4.0 and a
Qualcomm PCIe2 PHY. The driver already supports version 2.4.0, for the
IPQ4019, but this support touches clocks and resets related to the PHY
as well, and there's no upstream driver for the PHY.
On QCS404 we must initialize the PHY, so a separate PHY driver is
implemented to take care of this and the controller driver is updated to
not require the PHY related resources. This is done by relying on the
fact that operations in both the clock and reset framework are nops when
passed NULL, so we can isolate this change to only the get_resource
function.
For QCS404 we also need to enable the AHB (iface) clock, in order to
access the register space of the controller, but as this is not part of
the IPQ4019 DT binding this is only added for new users of the 2.4.0
controller.
Signed-off-by: Bjorn Andersson <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom.c | 64 +++++++++++++++-----------
1 file changed, 38 insertions(+), 26 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 9d366fad2b7f..6d4215ddcb42 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -113,7 +113,7 @@ struct qcom_pcie_resources_2_3_2 {
};
struct qcom_pcie_resources_2_4_0 {
- struct clk_bulk_data clks[3];
+ struct clk_bulk_data clks[4];
int num_clks;
struct reset_control *axi_m_reset;
struct reset_control *axi_s_reset;
@@ -637,13 +637,16 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
+ bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
int ret;
res->clks[0].id = "aux";
res->clks[1].id = "master_bus";
res->clks[2].id = "slave_bus";
+ res->clks[3].id = "iface";
- res->num_clks = 3;
+ /* qcom,pcie-ipq4019 is defined without "iface" */
+ res->num_clks = is_ipq ? 3 : 4;
ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
if (ret < 0)
@@ -657,27 +660,33 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
if (IS_ERR(res->axi_s_reset))
return PTR_ERR(res->axi_s_reset);
- res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
- if (IS_ERR(res->pipe_reset))
- return PTR_ERR(res->pipe_reset);
-
- res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
- "axi_m_vmid");
- if (IS_ERR(res->axi_m_vmid_reset))
- return PTR_ERR(res->axi_m_vmid_reset);
-
- res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
- "axi_s_xpu");
- if (IS_ERR(res->axi_s_xpu_reset))
- return PTR_ERR(res->axi_s_xpu_reset);
-
- res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
- if (IS_ERR(res->parf_reset))
- return PTR_ERR(res->parf_reset);
-
- res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
- if (IS_ERR(res->phy_reset))
- return PTR_ERR(res->phy_reset);
+ if (is_ipq) {
+ /*
+ * These resources relates to the PHY, but are controlled here
+ * for IPQ4019
+ */
+ res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
+ if (IS_ERR(res->pipe_reset))
+ return PTR_ERR(res->pipe_reset);
+
+ res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
+ "axi_m_vmid");
+ if (IS_ERR(res->axi_m_vmid_reset))
+ return PTR_ERR(res->axi_m_vmid_reset);
+
+ res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
+ "axi_s_xpu");
+ if (IS_ERR(res->axi_s_xpu_reset))
+ return PTR_ERR(res->axi_s_xpu_reset);
+
+ res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
+ if (IS_ERR(res->parf_reset))
+ return PTR_ERR(res->parf_reset);
+
+ res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
+ if (IS_ERR(res->phy_reset))
+ return PTR_ERR(res->phy_reset);
+ }
res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev,
"axi_m_sticky");
@@ -697,9 +706,11 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
if (IS_ERR(res->ahb_reset))
return PTR_ERR(res->ahb_reset);
- res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
- if (IS_ERR(res->phy_ahb_reset))
- return PTR_ERR(res->phy_ahb_reset);
+ if (is_ipq) {
+ res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
+ if (IS_ERR(res->phy_ahb_reset))
+ return PTR_ERR(res->phy_ahb_reset);
+ }
return 0;
}
@@ -1284,6 +1295,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
{ .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
{ .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
+ { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
{ }
};
--
2.18.0
Enabling PCIe requires several of the PCIe related resets from GCC, so
add them all.
Signed-off-by: Bjorn Andersson <[email protected]>
---
Stephen, I suggest that we merge this patch through Andy's devicetree branch,
together with the DT patch in the end of this series.
drivers/clk/qcom/gcc-qcs404.c | 7 +++++++
include/dt-bindings/clock/qcom,gcc-qcs404.h | 7 +++++++
2 files changed, 14 insertions(+)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 64da032bb9ed..cfb8789ff706 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -2675,6 +2675,13 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = {
[GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
[GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
+ [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = {0x3e040, 6},
+ [GCC_PCIE_0_AHB_ARES] = {0x3e040, 5},
+ [GCC_PCIE_0_AXI_SLAVE_ARES] = {0x3e040, 4},
+ [GCC_PCIE_0_AXI_MASTER_ARES] = {0x3e040, 3},
+ [GCC_PCIE_0_CORE_STICKY_ARES] = {0x3e040, 2},
+ [GCC_PCIE_0_SLEEP_ARES] = {0x3e040, 1},
+ [GCC_PCIE_0_PIPE_ARES] = {0x3e040, 0},
[GCC_EMAC_BCR] = { 0x4e000 },
};
diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
index 6ceb55ed72c6..00ab0d77b38a 100644
--- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -161,5 +161,12 @@
#define GCC_PCIE_0_LINK_DOWN_BCR 11
#define GCC_PCIEPHY_0_PHY_BCR 12
#define GCC_EMAC_BCR 13
+#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14
+#define GCC_PCIE_0_AHB_ARES 15
+#define GCC_PCIE_0_AXI_SLAVE_ARES 16
+#define GCC_PCIE_0_AXI_MASTER_ARES 17
+#define GCC_PCIE_0_CORE_STICKY_ARES 18
+#define GCC_PCIE_0_SLEEP_ARES 19
+#define GCC_PCIE_0_PIPE_ARES 20
#endif
--
2.18.0
Before introducing the QCS404 platform, which uses the same PCIe
controller as IPQ4019, migrate this to use the bulk clock API, in order
to make the error paths slighly cleaner.
Signed-off-by: Bjorn Andersson <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom.c | 48 +++++++-------------------
1 file changed, 13 insertions(+), 35 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index a7f703556790..9d366fad2b7f 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -113,9 +113,8 @@ struct qcom_pcie_resources_2_3_2 {
};
struct qcom_pcie_resources_2_4_0 {
- struct clk *aux_clk;
- struct clk *master_clk;
- struct clk *slave_clk;
+ struct clk_bulk_data clks[3];
+ int num_clks;
struct reset_control *axi_m_reset;
struct reset_control *axi_s_reset;
struct reset_control *pipe_reset;
@@ -638,18 +637,17 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
+ int ret;
- res->aux_clk = devm_clk_get(dev, "aux");
- if (IS_ERR(res->aux_clk))
- return PTR_ERR(res->aux_clk);
+ res->clks[0].id = "aux";
+ res->clks[1].id = "master_bus";
+ res->clks[2].id = "slave_bus";
- res->master_clk = devm_clk_get(dev, "master_bus");
- if (IS_ERR(res->master_clk))
- return PTR_ERR(res->master_clk);
+ res->num_clks = 3;
- res->slave_clk = devm_clk_get(dev, "slave_bus");
- if (IS_ERR(res->slave_clk))
- return PTR_ERR(res->slave_clk);
+ ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
+ if (ret < 0)
+ return ret;
res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m");
if (IS_ERR(res->axi_m_reset))
@@ -719,9 +717,7 @@ static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
reset_control_assert(res->axi_m_sticky_reset);
reset_control_assert(res->pwr_reset);
reset_control_assert(res->ahb_reset);
- clk_disable_unprepare(res->aux_clk);
- clk_disable_unprepare(res->master_clk);
- clk_disable_unprepare(res->slave_clk);
+ clk_bulk_disable_unprepare(res->num_clks, res->clks);
}
static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
@@ -850,23 +846,9 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
usleep_range(10000, 12000);
- ret = clk_prepare_enable(res->aux_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable iface clock\n");
+ ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
+ if (ret)
goto err_clk_aux;
- }
-
- ret = clk_prepare_enable(res->master_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable core clock\n");
- goto err_clk_axi_m;
- }
-
- ret = clk_prepare_enable(res->slave_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable phy clock\n");
- goto err_clk_axi_s;
- }
/* enable PCIe clocks and resets */
val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
@@ -891,10 +873,6 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
return 0;
-err_clk_axi_s:
- clk_disable_unprepare(res->master_clk);
-err_clk_axi_m:
- clk_disable_unprepare(res->aux_clk);
err_clk_aux:
reset_control_assert(res->ahb_reset);
err_rst_ahb:
--
2.18.0
Quoting Bjorn Andersson (2019-01-25 15:45:09)
> @@ -771,6 +788,56 @@
> status = "disabled";
> };
> };
> +
> + pcie: pci@10000000 {
> + compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
> + reg = <0x10000000 0xf1d
Nitpick: Can you format these like <0x10000000 0xf1d>, <0x10000f20 0xa8>, etc?
> + 0x10000f20 0xa8
> + 0x07780000 0x2000
> + 0x10001000 0x2000>;
> + reg-names = "dbi", "elbi", "parf", "config";
> + device_type = "pci";
> + linux,pci-domain = <0>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x81000000 0 0 0x10003000 0 0x00010000 /* I/O */
Same for this one? It's nice to know what the size of the cells are.
> + 0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
> +
Quoting Bjorn Andersson (2019-01-25 15:45:03)
> Enabling PCIe requires several of the PCIe related resets from GCC, so
> add them all.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
Acked-by: Stephen Boyd <[email protected]>
On 25-01-19, 15:45, Bjorn Andersson wrote:
> The Qualcomm PCIe2 PHY is a Synopsys based PCIe PHY found in a number of
> Qualcomm platforms, add a binding to describe this.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> .../bindings/phy/qcom-pcie2-phy.txt | 40 +++++++++++++++++++
> 1 file changed, 40 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
> new file mode 100644
> index 000000000000..7da02f9d78c7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
> @@ -0,0 +1,40 @@
> +Qualcomm PCIe2 PHY controller
> +=============================
> +
> +The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
> +platforms.
> +
> +Required properties:
> + - compatible: compatible list, should be:
> + "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
> +
> + - reg: offset and length of the PHY register set.
> + - #phy-cells: must be 0.
> +
> + - clocks: a clock-specifier pair for the "pipe" clock
> +
> + - vdda-vp-supply: phandle to low voltage regulator
> + - vdda-vph-supply: phandle to high voltage regulator
> +
> + - resets: reset-specifier pairs for the "phy" and "pipe" resets
> + - reset-names: list of resets, should contain:
> + "phy" and "pipe"
> +
> + - clock-output-names: name of the outgoing clock signal from the PHY PLL
Should we specify the clk name here?
> +
> +Example:
> + phy@7786000 {
> + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
> + reg = <0x07786000 0xb8>;
> +
> + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
> + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
> + <&gcc GCC_PCIE_0_PIPE_ARES>;
> + reset-names = "phy", "pipe";
> +
> + vdda-vp-supply = <&vreg_l3_1p05>;
> + vdda-vph-supply = <&vreg_l5_1p8>;
> +
> + clock-output-names = "pcie_0_pipe_clk";
> + #phy-cells = <0>;
> + };
> --
> 2.18.0
--
~Vinod
On 25-01-19, 15:45, Bjorn Andersson wrote:
> The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, add these to
> the platform dtsi and enable them for the EVB with the perst gpio
> and analog supplies defined.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 25 +++++++++
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 67 ++++++++++++++++++++++++
> 2 files changed, 92 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
> index 50b3589c7f15..579ddaf4f5fa 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
> @@ -21,6 +21,22 @@
> };
> };
>
> +&pcie {
> + status = "ok";
> +
> + perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&perst_state>;
> +};
> +
> +&pcie_phy {
> + status = "ok";
> +
> + vdda-vp-supply = <&vreg_l3_1p05>;
> + vdda-vph-supply = <&vreg_l5_1p8>;
> +};
I would prefer the patches be split to qcs404 adding PCIe nodes and then
add the board node for EVB...
> +
> &remoteproc_adsp {
> status = "ok";
> };
> @@ -137,6 +153,15 @@
> };
>
> &tlmm {
> + perst_state: perst {
> + pins = "gpio43";
> + function = "gpio";
> +
> + drive-strength = <2>;
> + bias-disable;
> + output-low;
> + };
> +
> sdc1_on: sdc1-on {
> clk {
> pins = "sdc1_clk";
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index 76699435c8bd..7b219865ba7e 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -3,6 +3,7 @@
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,gcc-qcs404.h>
> +#include <dt-bindings/gpio/gpio.h>
>
> / {
> interrupt-parent = <&intc>;
> @@ -377,6 +378,7 @@
> compatible = "qcom,gcc-qcs404";
> reg = <0x01800000 0x80000>;
> #clock-cells = <1>;
> + #reset-cells = <1>;
>
> assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
> assigned-clock-rates = <19200000>;
> @@ -405,6 +407,21 @@
> #interrupt-cells = <4>;
> };
>
> + pcie_phy: phy@7786000 {
> + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
> + reg = <0x07786000 0xb8>;
> +
> + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
> + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
> + <&gcc GCC_PCIE_0_PIPE_ARES>;
> + reset-names = "phy", "pipe";
> +
> + clock-output-names = "pcie_0_pipe_clk";
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> sdcc1: sdcc@7804000 {
> compatible = "qcom,sdhci-msm-v5";
> reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
> @@ -771,6 +788,56 @@
> status = "disabled";
> };
> };
> +
> + pcie: pci@10000000 {
> + compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
> + reg = <0x10000000 0xf1d
> + 0x10000f20 0xa8
> + 0x07780000 0x2000
> + 0x10001000 0x2000>;
> + reg-names = "dbi", "elbi", "parf", "config";
> + device_type = "pci";
> + linux,pci-domain = <0>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x81000000 0 0 0x10003000 0 0x00010000 /* I/O */
> + 0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
> +
> + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> + <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_0_AUX_CLK>,
> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
> + clock-names = "iface", "aux", "master_bus", "slave_bus";
> +
> + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
> + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
> + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
> + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
> + <&gcc GCC_PCIE_0_BCR>,
> + <&gcc GCC_PCIE_0_AHB_ARES>;
> + reset-names = "axi_m",
> + "axi_s",
> + "axi_m_sticky",
> + "pipe_sticky",
> + "pwr",
> + "ahb";
> +
> + phys = <&pcie_phy>;
> + phy-names = "pciephy";
> +
> + status = "disabled";
> + };
> };
>
> timer {
> --
> 2.18.0
--
~Vinod
On Fri, Jan 25, 2019 at 03:45:03PM -0800, Bjorn Andersson wrote:
> Enabling PCIe requires several of the PCIe related resets from GCC, so
> add them all.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
>
> Stephen, I suggest that we merge this patch through Andy's devicetree branch,
> together with the DT patch in the end of this series.
>
> drivers/clk/qcom/gcc-qcs404.c | 7 +++++++
> include/dt-bindings/clock/qcom,gcc-qcs404.h | 7 +++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
> index 64da032bb9ed..cfb8789ff706 100644
> --- a/drivers/clk/qcom/gcc-qcs404.c
> +++ b/drivers/clk/qcom/gcc-qcs404.c
> @@ -2675,6 +2675,13 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = {
> [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
> [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
> [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
> + [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = {0x3e040, 6},
> + [GCC_PCIE_0_AHB_ARES] = {0x3e040, 5},
> + [GCC_PCIE_0_AXI_SLAVE_ARES] = {0x3e040, 4},
> + [GCC_PCIE_0_AXI_MASTER_ARES] = {0x3e040, 3},
> + [GCC_PCIE_0_CORE_STICKY_ARES] = {0x3e040, 2},
> + [GCC_PCIE_0_SLEEP_ARES] = {0x3e040, 1},
> + [GCC_PCIE_0_PIPE_ARES] = {0x3e040, 0},
Hello Bjorn,
please add spaces before and after the braces, to match the
syntax of the existing lines.
With that,
Reviewed-by: Niklas Cassel <[email protected]>
Kind regards,
Niklas
> [GCC_EMAC_BCR] = { 0x4e000 },
> };
>
> diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
> index 6ceb55ed72c6..00ab0d77b38a 100644
> --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
> +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
> @@ -161,5 +161,12 @@
> #define GCC_PCIE_0_LINK_DOWN_BCR 11
> #define GCC_PCIEPHY_0_PHY_BCR 12
> #define GCC_EMAC_BCR 13
> +#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14
> +#define GCC_PCIE_0_AHB_ARES 15
> +#define GCC_PCIE_0_AXI_SLAVE_ARES 16
> +#define GCC_PCIE_0_AXI_MASTER_ARES 17
> +#define GCC_PCIE_0_CORE_STICKY_ARES 18
> +#define GCC_PCIE_0_SLEEP_ARES 19
> +#define GCC_PCIE_0_PIPE_ARES 20
>
> #endif
> --
> 2.18.0
>
On Fri, Jan 25, 2019 at 03:45:05PM -0800, Bjorn Andersson wrote:
> The Qualcomm PCIe2 PHY is based on design from Synopsys and found in
> several different platforms where the QMP PHY isn't used.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> drivers/phy/qualcomm/Kconfig | 8 +
> drivers/phy/qualcomm/Makefile | 1 +
> drivers/phy/qualcomm/phy-qcom-pcie2.c | 331 ++++++++++++++++++++++++++
> 3 files changed, 340 insertions(+)
> create mode 100644 drivers/phy/qualcomm/phy-qcom-pcie2.c
>
> diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
> index 32f7d34eb784..0edb5316972f 100644
> --- a/drivers/phy/qualcomm/Kconfig
> +++ b/drivers/phy/qualcomm/Kconfig
> @@ -24,6 +24,14 @@ config PHY_QCOM_IPQ806X_SATA
> depends on OF
> select GENERIC_PHY
>
> +config PHY_QCOM_PCIE2
> + tristate "Qualcomm PCIe PHY Driver"
Perhaps "Qualcomm PCIe2 PHY Driver" or "Qualcomm PCIe Gen2 PHY Driver"
as that is more descriptive.
> + depends on OF && COMMON_CLK && (ARCH_QCOM || COMPILE_TEST)
> + select GENERIC_PHY
> + help
> + Enable this to support the Qualcomm PCIe PHY, used with the Synopsys
> + based PCIe controller.
> +
> config PHY_QCOM_QMP
> tristate "Qualcomm QMP PHY Driver"
> depends on OF && COMMON_CLK && (ARCH_QCOM || COMPILE_TEST)
> diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
> index c56efd3af205..283251d6a5d9 100644
> --- a/drivers/phy/qualcomm/Makefile
> +++ b/drivers/phy/qualcomm/Makefile
> @@ -2,6 +2,7 @@
> obj-$(CONFIG_PHY_ATH79_USB) += phy-ath79-usb.o
> obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
> obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
> +obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o
> obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
> obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
> obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
> diff --git a/drivers/phy/qualcomm/phy-qcom-pcie2.c b/drivers/phy/qualcomm/phy-qcom-pcie2.c
> new file mode 100644
> index 000000000000..2fa891c18b6f
> --- /dev/null
> +++ b/drivers/phy/qualcomm/phy-qcom-pcie2.c
> @@ -0,0 +1,331 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2019, Linaro Ltd.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clk.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +
> +#include <dt-bindings/phy/phy.h>
> +
> +#define PCIE20_PARF_PHY_STTS 0x3c
> +#define PCIE2_PHY_RESET_CTRL 0x44
> +#define PCIE20_PARF_PHY_REFCLK_CTRL2 0xa0
> +#define PCIE20_PARF_PHY_REFCLK_CTRL3 0xa4
> +#define PCIE20_PARF_PCS_SWING_CTRL1 0x88
> +#define PCIE20_PARF_PCS_SWING_CTRL2 0x8c
> +#define PCIE20_PARF_PCS_DEEMPH1 0x74
> +#define PCIE20_PARF_PCS_DEEMPH2 0x78
> +#define PCIE20_PARF_PCS_DEEMPH3 0x7c
> +#define PCIE20_PARF_CONFIGBITS 0x84
> +#define PCIE20_PARF_PHY_CTRL3 0x94
> +#define PCIE20_PARF_PCS_CTRL 0x80
> +
> +#define TX_AMP_VAL 120
> +#define PHY_RX0_EQ_GEN1_VAL 0
> +#define PHY_RX0_EQ_GEN2_VAL 4
> +#define TX_DEEMPH_GEN1_VAL 24
> +#define TX_DEEMPH_GEN2_3_5DB_VAL 26
> +#define TX_DEEMPH_GEN2_6DB_VAL 36
> +#define PHY_TX0_TERM_OFFST_VAL 0
> +
> +struct qcom_phy {
> + struct device *dev;
> + void __iomem *base;
> +
> + struct regulator_bulk_data vregs[2];
> +
> + struct reset_control *phy_reset;
> + struct reset_control *pipe_reset;
> + struct clk *pipe_clk;
> +};
> +
> +static int qcom_pcie2_phy_init(struct phy *phy)
> +{
> + struct qcom_phy *qphy = phy_get_drvdata(phy);
> + int ret;
> +
> + ret = reset_control_deassert(qphy->phy_reset);
> + if (ret) {
> + dev_err(qphy->dev, "cannot deassert pipe reset\n");
> + return ret;
> + }
> +
> + ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
> + if (ret)
> + reset_control_assert(qphy->phy_reset);
> +
> + return ret;
> +}
> +
> +static int qcom_pcie2_phy_power_on(struct phy *phy)
> +{
> + struct qcom_phy *qphy = phy_get_drvdata(phy);
> + int ret;
> + u32 val;
> +
> + /* Program REF_CLK source */
> + val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
> + val &= ~BIT(1);
> + writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
> +
> + usleep_range(1000, 2000);
> +
> + /* Don't use PAD for refclock */
> + val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
> + val &= ~BIT(0);
> + writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
> +
> + /* Program SSP ENABLE */
> + val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
> + val |= BIT(0);
> + writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
> +
> + usleep_range(1000, 2000);
> +
> + /* Assert Phy SW Reset */
> + val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
> + val |= BIT(0);
> + writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
> +
> + /* Program Tx Amplitude */
> + val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
> + val &= ~0x7f;
> + val |= TX_AMP_VAL;
> + writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
> +
> + val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
> + val &= ~0x7f;
> + val |= TX_AMP_VAL;
> + writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
> +
> + /* Program De-Emphasis */
> + val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH1);
> + val &= ~0x3f;
> + val |= TX_DEEMPH_GEN2_6DB_VAL;
> + writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH1);
> +
> + val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH2);
> + val &= ~0x3f;
> + val |= TX_DEEMPH_GEN2_3_5DB_VAL;
> + writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH2);
> +
> + val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH3);
> + val &= ~0x3f;
> + val |= TX_DEEMPH_GEN1_VAL;
> + writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH3);
> +
> + /* Program Rx_Eq */
> + val = readl(qphy->base + PCIE20_PARF_CONFIGBITS);
> + val &= ~0x7;
> + val |= PHY_RX0_EQ_GEN2_VAL;
> + writel(val, qphy->base + PCIE20_PARF_CONFIGBITS);
> +
> + /* Program Tx0_term_offset */
> + val = readl(qphy->base + PCIE20_PARF_PHY_CTRL3);
> + val &= ~0x1f;
> + val |= PHY_TX0_TERM_OFFST_VAL;
> + writel(val, qphy->base + PCIE20_PARF_PHY_CTRL3);
> +
> + /* disable Tx2Rx Loopback */
> + val = readl(qphy->base + PCIE20_PARF_PCS_CTRL);
> + val &= ~BIT(1);
> + writel(val, qphy->base + PCIE20_PARF_PCS_CTRL);
> +
> + /* De-assert Phy SW Reset */
> + val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
> + val &= ~BIT(0);
> + writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
> +
> + usleep_range(1000, 2000);
> +
> + ret = reset_control_deassert(qphy->pipe_reset);
> + if (ret) {
> + dev_err(qphy->dev, "cannot deassert pipe reset\n");
> + goto out;
> + }
> +
> + clk_set_rate(qphy->pipe_clk, 250000000);
> +
> + ret = clk_prepare_enable(qphy->pipe_clk);
> + if (ret) {
> + dev_err(qphy->dev, "failed to enable pipe clock\n");
> + goto out;
> + }
> +
> + ret = readl_poll_timeout(qphy->base + PCIE20_PARF_PHY_STTS, val,
> + !(val & BIT(0)), 1000, 10);
> + if (ret)
> + dev_err(qphy->dev, "phy initialization failed\n");
> +
> +out:
> + return ret;
> +}
> +
> +static int qcom_pcie2_phy_power_off(struct phy *phy)
> +{
> + struct qcom_phy *qphy = phy_get_drvdata(phy);
> + u32 val;
> +
> + val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
> + val |= BIT(0);
> + writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
> +
> + clk_disable_unprepare(qphy->pipe_clk);
> + reset_control_assert(qphy->pipe_reset);
> +
> + return 0;
> +}
> +
> +static int qcom_pcie2_phy_exit(struct phy *phy)
> +{
> + struct qcom_phy *qphy = phy_get_drvdata(phy);
> +
> + regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
> + reset_control_assert(qphy->phy_reset);
> +
> + return 0;
> +}
<> +
> +static const struct phy_ops qcom_pcie2_ops = {
> + .init = qcom_pcie2_phy_init,
> + .power_on = qcom_pcie2_phy_power_on,
> + .power_off = qcom_pcie2_phy_power_off,
> + .exit = qcom_pcie2_phy_exit,
> + .owner = THIS_MODULE,
> +};
> +
> +/*
> + * Register a fixed rate pipe clock.
> + *
> + * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
> + * controls it. The <s>_pipe_clk coming out of the GCC is requested
> + * by the PHY driver for its operations.
> + * We register the <s>_pipe_clksrc here. The gcc driver takes care
> + * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
> + * Below picture shows this relationship.
> + *
> + * +---------------+
> + * | PHY block |<<---------------------------------------+
> + * | | |
> + * | +-------+ | +-----+ |
> + * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
> + * clk | +-------+ | +-----+
> + * +---------------+
> + */
> +static int phy_pipe_clk_register(struct qcom_phy *qphy)
Perhaps rename this function to
phy_pipe_clksrc_register()
since it is that clock that we register here.
With those two minor nits:
Reviewed-by: Niklas Cassel <[email protected]>
> +{
> + struct device_node *np = qphy->dev->of_node;
> + struct clk_fixed_rate *fixed;
> + struct clk_init_data init = { };
> + int ret;
> +
> + ret = of_property_read_string(np, "clock-output-names", &init.name);
> + if (ret) {
> + dev_err(qphy->dev, "%s: No clock-output-names\n", np->name);
> + return ret;
> + }
> +
> + fixed = devm_kzalloc(qphy->dev, sizeof(*fixed), GFP_KERNEL);
> + if (!fixed)
> + return -ENOMEM;
> +
> + init.ops = &clk_fixed_rate_ops;
> +
> + /* controllers using QMP phys use 250MHz pipe clock interface */
> + fixed->fixed_rate = 250000000;
> + fixed->hw.init = &init;
> +
> + return devm_clk_hw_register(qphy->dev, &fixed->hw);
> +}
> +
> +static int qcom_pcie2_phy_probe(struct platform_device *pdev)
> +{
> + struct phy_provider *phy_provider;
> + struct qcom_phy *qphy;
> + struct resource *res;
> + struct device *dev = &pdev->dev;
> + struct phy *phy;
> + int ret;
> +
> + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
> + if (!qphy)
> + return -ENOMEM;
> +
> + qphy->dev = dev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + qphy->base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(qphy->base))
> + return PTR_ERR(qphy->base);
> +
> + ret = phy_pipe_clk_register(qphy);
> + if (ret) {
> + dev_err(dev, "failed to register pipe_clk\n");
> + return ret;
> + }
> +
> + qphy->vregs[0].supply = "vdda-vp";
> + qphy->vregs[1].supply = "vdda-vph";
> + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(qphy->vregs), qphy->vregs);
> + if (ret < 0)
> + return ret;
> +
> + qphy->pipe_clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(qphy->pipe_clk)) {
> + dev_err(dev, "failed to acquire pipe clock\n");
> + return PTR_ERR(qphy->pipe_clk);
> + }
> +
> + qphy->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
> + if (IS_ERR(qphy->phy_reset)) {
> + dev_err(dev, "failed to acquire phy reset\n");
> + return PTR_ERR(qphy->phy_reset);
> + }
> +
> + qphy->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
> + if (IS_ERR(qphy->pipe_reset)) {
> + dev_err(dev, "failed to acquire pipe reset\n");
> + return PTR_ERR(qphy->pipe_reset);
> + }
> +
> + phy = devm_phy_create(dev, dev->of_node, &qcom_pcie2_ops);
> + if (IS_ERR(phy)) {
> + dev_err(dev, "failed to create phy\n");
> + return PTR_ERR(phy);
> + }
> +
> + phy_set_drvdata(phy, qphy);
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (IS_ERR(phy_provider))
> + dev_err(dev, "failed to register phy provider\n");
> +
> + return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static const struct of_device_id qcom_pcie2_phy_match_table[] = {
> + { .compatible = "qcom,pcie2-phy" },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, qcom_pcie2_phy_match_table);
> +
> +static struct platform_driver qcom_pcie2_phy_driver = {
> + .probe = qcom_pcie2_phy_probe,
> + .driver = {
> + .name = "qcom-pcie2-phy",
> + .of_match_table = qcom_pcie2_phy_match_table,
> + },
> +};
> +
> +module_platform_driver(qcom_pcie2_phy_driver);
> +
> +MODULE_DESCRIPTION("Qualcomm PCIe PHY driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.18.0
>
On Fri, Jan 25, 2019 at 03:45:06PM -0800, Bjorn Andersson wrote:
> Before introducing the QCS404 platform, which uses the same PCIe
> controller as IPQ4019, migrate this to use the bulk clock API, in order
> to make the error paths slighly cleaner.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 48 +++++++-------------------
> 1 file changed, 13 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index a7f703556790..9d366fad2b7f 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -113,9 +113,8 @@ struct qcom_pcie_resources_2_3_2 {
> };
>
> struct qcom_pcie_resources_2_4_0 {
> - struct clk *aux_clk;
> - struct clk *master_clk;
> - struct clk *slave_clk;
> + struct clk_bulk_data clks[3];
> + int num_clks;
> struct reset_control *axi_m_reset;
> struct reset_control *axi_s_reset;
> struct reset_control *pipe_reset;
> @@ -638,18 +637,17 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
> struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
> struct dw_pcie *pci = pcie->pci;
> struct device *dev = pci->dev;
> + int ret;
>
> - res->aux_clk = devm_clk_get(dev, "aux");
> - if (IS_ERR(res->aux_clk))
> - return PTR_ERR(res->aux_clk);
> + res->clks[0].id = "aux";
> + res->clks[1].id = "master_bus";
> + res->clks[2].id = "slave_bus";
>
> - res->master_clk = devm_clk_get(dev, "master_bus");
> - if (IS_ERR(res->master_clk))
> - return PTR_ERR(res->master_clk);
> + res->num_clks = 3;
>
> - res->slave_clk = devm_clk_get(dev, "slave_bus");
> - if (IS_ERR(res->slave_clk))
> - return PTR_ERR(res->slave_clk);
> + ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
> + if (ret < 0)
> + return ret;
>
> res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m");
> if (IS_ERR(res->axi_m_reset))
> @@ -719,9 +717,7 @@ static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
> reset_control_assert(res->axi_m_sticky_reset);
> reset_control_assert(res->pwr_reset);
> reset_control_assert(res->ahb_reset);
> - clk_disable_unprepare(res->aux_clk);
> - clk_disable_unprepare(res->master_clk);
> - clk_disable_unprepare(res->slave_clk);
> + clk_bulk_disable_unprepare(res->num_clks, res->clks);
> }
>
> static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
> @@ -850,23 +846,9 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
>
> usleep_range(10000, 12000);
>
> - ret = clk_prepare_enable(res->aux_clk);
> - if (ret) {
> - dev_err(dev, "cannot prepare/enable iface clock\n");
> + ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
> + if (ret)
> goto err_clk_aux;
> - }
> -
> - ret = clk_prepare_enable(res->master_clk);
> - if (ret) {
> - dev_err(dev, "cannot prepare/enable core clock\n");
> - goto err_clk_axi_m;
> - }
> -
> - ret = clk_prepare_enable(res->slave_clk);
> - if (ret) {
> - dev_err(dev, "cannot prepare/enable phy clock\n");
> - goto err_clk_axi_s;
> - }
>
> /* enable PCIe clocks and resets */
> val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
> @@ -891,10 +873,6 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
>
> return 0;
>
> -err_clk_axi_s:
> - clk_disable_unprepare(res->master_clk);
> -err_clk_axi_m:
> - clk_disable_unprepare(res->aux_clk);
> err_clk_aux:
> reset_control_assert(res->ahb_reset);
> err_rst_ahb:
> --
> 2.18.0
>
Reviewed-by: Niklas Cassel <[email protected]>
On Fri, Jan 25, 2019 at 03:45:09PM -0800, Bjorn Andersson wrote:
> The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, add these to
> the platform dtsi and enable them for the EVB with the perst gpio
> and analog supplies defined.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 25 +++++++++
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 67 ++++++++++++++++++++++++
> 2 files changed, 92 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
> index 50b3589c7f15..579ddaf4f5fa 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
> @@ -21,6 +21,22 @@
> };
> };
>
> +&pcie {
> + status = "ok";
> +
> + perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&perst_state>;
> +};
> +
> +&pcie_phy {
> + status = "ok";
> +
> + vdda-vp-supply = <&vreg_l3_1p05>;
> + vdda-vph-supply = <&vreg_l5_1p8>;
> +};
> +
> &remoteproc_adsp {
> status = "ok";
> };
> @@ -137,6 +153,15 @@
> };
>
> &tlmm {
> + perst_state: perst {
> + pins = "gpio43";
> + function = "gpio";
> +
> + drive-strength = <2>;
> + bias-disable;
> + output-low;
> + };
> +
> sdc1_on: sdc1-on {
> clk {
> pins = "sdc1_clk";
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index 76699435c8bd..7b219865ba7e 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -3,6 +3,7 @@
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,gcc-qcs404.h>
> +#include <dt-bindings/gpio/gpio.h>
>
> / {
> interrupt-parent = <&intc>;
> @@ -377,6 +378,7 @@
> compatible = "qcom,gcc-qcs404";
> reg = <0x01800000 0x80000>;
> #clock-cells = <1>;
> + #reset-cells = <1>;
>
> assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
> assigned-clock-rates = <19200000>;
> @@ -405,6 +407,21 @@
> #interrupt-cells = <4>;
> };
>
> + pcie_phy: phy@7786000 {
> + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
> + reg = <0x07786000 0xb8>;
> +
> + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
> + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
> + <&gcc GCC_PCIE_0_PIPE_ARES>;
> + reset-names = "phy", "pipe";
> +
> + clock-output-names = "pcie_0_pipe_clk";
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> sdcc1: sdcc@7804000 {
> compatible = "qcom,sdhci-msm-v5";
> reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
> @@ -771,6 +788,56 @@
> status = "disabled";
> };
> };
> +
> + pcie: pci@10000000 {
> + compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
> + reg = <0x10000000 0xf1d
> + 0x10000f20 0xa8
> + 0x07780000 0x2000
> + 0x10001000 0x2000>;
> + reg-names = "dbi", "elbi", "parf", "config";
> + device_type = "pci";
> + linux,pci-domain = <0>;
Since we only have single PCIe controller,
I don't think we need to specify a pci-domain.
With that:
Reviewed-by: Niklas Cassel <[email protected]>
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x81000000 0 0 0x10003000 0 0x00010000 /* I/O */
> + 0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
> +
> + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> + <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_0_AUX_CLK>,
> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
> + clock-names = "iface", "aux", "master_bus", "slave_bus";
> +
> + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
> + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
> + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
> + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
> + <&gcc GCC_PCIE_0_BCR>,
> + <&gcc GCC_PCIE_0_AHB_ARES>;
> + reset-names = "axi_m",
> + "axi_s",
> + "axi_m_sticky",
> + "pipe_sticky",
> + "pwr",
> + "ahb";
> +
> + phys = <&pcie_phy>;
> + phy-names = "pciephy";
> +
> + status = "disabled";
> + };
> };
>
> timer {
> --
> 2.18.0
>
On Fri, Jan 25, 2019 at 03:45:08PM -0800, Bjorn Andersson wrote:
> The QCS404 platform contains a PCIe controller of version 2.4.0 and a
> Qualcomm PCIe2 PHY. The driver already supports version 2.4.0, for the
> IPQ4019, but this support touches clocks and resets related to the PHY
> as well, and there's no upstream driver for the PHY.
>
> On QCS404 we must initialize the PHY, so a separate PHY driver is
> implemented to take care of this and the controller driver is updated to
> not require the PHY related resources. This is done by relying on the
> fact that operations in both the clock and reset framework are nops when
> passed NULL, so we can isolate this change to only the get_resource
> function.
>
> For QCS404 we also need to enable the AHB (iface) clock, in order to
> access the register space of the controller, but as this is not part of
> the IPQ4019 DT binding this is only added for new users of the 2.4.0
> controller.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 64 +++++++++++++++-----------
> 1 file changed, 38 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 9d366fad2b7f..6d4215ddcb42 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -113,7 +113,7 @@ struct qcom_pcie_resources_2_3_2 {
> };
>
> struct qcom_pcie_resources_2_4_0 {
> - struct clk_bulk_data clks[3];
> + struct clk_bulk_data clks[4];
> int num_clks;
> struct reset_control *axi_m_reset;
> struct reset_control *axi_s_reset;
> @@ -637,13 +637,16 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
> struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
> struct dw_pcie *pci = pcie->pci;
> struct device *dev = pci->dev;
> + bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
> int ret;
>
> res->clks[0].id = "aux";
> res->clks[1].id = "master_bus";
> res->clks[2].id = "slave_bus";
> + res->clks[3].id = "iface";
>
> - res->num_clks = 3;
> + /* qcom,pcie-ipq4019 is defined without "iface" */
> + res->num_clks = is_ipq ? 3 : 4;
>
> ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
> if (ret < 0)
> @@ -657,27 +660,33 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
> if (IS_ERR(res->axi_s_reset))
> return PTR_ERR(res->axi_s_reset);
>
> - res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
> - if (IS_ERR(res->pipe_reset))
> - return PTR_ERR(res->pipe_reset);
> -
> - res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
> - "axi_m_vmid");
> - if (IS_ERR(res->axi_m_vmid_reset))
> - return PTR_ERR(res->axi_m_vmid_reset);
> -
> - res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
> - "axi_s_xpu");
> - if (IS_ERR(res->axi_s_xpu_reset))
> - return PTR_ERR(res->axi_s_xpu_reset);
> -
> - res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
> - if (IS_ERR(res->parf_reset))
> - return PTR_ERR(res->parf_reset);
> -
> - res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
> - if (IS_ERR(res->phy_reset))
> - return PTR_ERR(res->phy_reset);
> + if (is_ipq) {
> + /*
> + * These resources relates to the PHY, but are controlled here
> + * for IPQ4019
> + */
This comment makes be believe that all these resouces are related to the
PHY.
"pipe" and "phy" are related to the PHY, but I doubt that the rest of them
relates to the PHY.
If QCS404 lacks these other reset signals, which is very possible, since
it's a completely different SoC, perhaps the comment should also mention
that.
With that:
Reviewed-by: Niklas Cassel <[email protected]>
> + res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
> + if (IS_ERR(res->pipe_reset))
> + return PTR_ERR(res->pipe_reset);
> +
> + res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
> + "axi_m_vmid");
> + if (IS_ERR(res->axi_m_vmid_reset))
> + return PTR_ERR(res->axi_m_vmid_reset);
> +
> + res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
> + "axi_s_xpu");
> + if (IS_ERR(res->axi_s_xpu_reset))
> + return PTR_ERR(res->axi_s_xpu_reset);
> +
> + res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
> + if (IS_ERR(res->parf_reset))
> + return PTR_ERR(res->parf_reset);
> +
> + res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
> + if (IS_ERR(res->phy_reset))
> + return PTR_ERR(res->phy_reset);
> + }
>
> res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev,
> "axi_m_sticky");
> @@ -697,9 +706,11 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
> if (IS_ERR(res->ahb_reset))
> return PTR_ERR(res->ahb_reset);
>
> - res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
> - if (IS_ERR(res->phy_ahb_reset))
> - return PTR_ERR(res->phy_ahb_reset);
> + if (is_ipq) {
> + res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
> + if (IS_ERR(res->phy_ahb_reset))
> + return PTR_ERR(res->phy_ahb_reset);
> + }
>
> return 0;
> }
> @@ -1284,6 +1295,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
> { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
> { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
> + { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
> { }
> };
>
> --
> 2.18.0
>