Add macro for the GPIO clocks of the i.MX8MM.
Signed-off-by: Anson Huang <[email protected]>
---
include/dt-bindings/clock/imx8mm-clock.h | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
index 1b4353e..fe47798 100644
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -239,6 +239,12 @@
#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222
-#define IMX8MM_CLK_END 223
+#define IMX8MM_CLK_GPIO1_ROOT 223
+#define IMX8MM_CLK_GPIO2_ROOT 224
+#define IMX8MM_CLK_GPIO3_ROOT 225
+#define IMX8MM_CLK_GPIO4_ROOT 226
+#define IMX8MM_CLK_GPIO5_ROOT 227
+
+#define IMX8MM_CLK_END 228
#endif
--
2.7.4
i.MX8MM has clock gate for each GPIO bank, add them
into clock tree for GPIO driver to manage.
Signed-off-by: Anson Huang <[email protected]>
---
drivers/clk/imx/clk-imx8mm.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 1ef8438..733ca20 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -590,6 +590,11 @@ static int __init imx8mm_clocks_init(struct device_node *ccm_node)
clks[IMX8MM_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
clks[IMX8MM_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
clks[IMX8MM_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
+ clks[IMX8MM_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0);
+ clks[IMX8MM_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0);
+ clks[IMX8MM_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);
+ clks[IMX8MM_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);
+ clks[IMX8MM_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);
clks[IMX8MM_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0);
clks[IMX8MM_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
clks[IMX8MM_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
--
2.7.4
i.MX8MM has clock gate for each GPIO bank, add clock info
to GPIO node for clock management.
Signed-off-by: Anson Huang <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 6b407a94..f32d4e9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -206,6 +206,7 @@
reg = <0x30200000 0x10000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -217,6 +218,7 @@
reg = <0x30210000 0x10000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -228,6 +230,7 @@
reg = <0x30220000 0x10000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -239,6 +242,7 @@
reg = <0x30230000 0x10000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -250,6 +254,7 @@
reg = <0x30240000 0x10000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
--
2.7.4
> From: Anson Huang
> Sent: Monday, May 6, 2019 5:18 PM
> Subject: [PATCH 1/3] dt-bindings: clock: imx8mm: Add GPIO clocks
>
> Add macro for the GPIO clocks of the i.MX8MM.
>
> Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Regards
Dong Aisheng
> From: Anson Huang
> Sent: Monday, May 6, 2019 5:18 PM
> Subject: [PATCH 2/3] clk: imx8mm: add GPIO clocks to clock tree
>
> i.MX8MM has clock gate for each GPIO bank, add them into clock tree for
> GPIO driver to manage.
>
> Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Regards
Dong Aisheng
> ---
> drivers/clk/imx/clk-imx8mm.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index 1ef8438..733ca20 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -590,6 +590,11 @@ static int __init imx8mm_clocks_init(struct
> device_node *ccm_node)
> clks[IMX8MM_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk",
> "ecspi2", base + 0x4080, 0);
> clks[IMX8MM_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk",
> "ecspi3", base + 0x4090, 0);
> clks[IMX8MM_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk",
> "enet_axi", base + 0x40a0, 0);
> + clks[IMX8MM_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk",
> "ipg_root", base + 0x40b0, 0);
> + clks[IMX8MM_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk",
> "ipg_root", base + 0x40c0, 0);
> + clks[IMX8MM_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk",
> "ipg_root", base + 0x40d0, 0);
> + clks[IMX8MM_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk",
> "ipg_root", base + 0x40e0, 0);
> + clks[IMX8MM_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk",
> +"ipg_root", base + 0x40f0, 0);
> clks[IMX8MM_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1",
> base + 0x4100, 0);
> clks[IMX8MM_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1",
> base + 0x4170, 0);
> clks[IMX8MM_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2",
> base + 0x4180, 0);
> --
> 2.7.4
> From: Anson Huang
> Sent: Monday, May 6, 2019 5:18 PM
> Subject: [PATCH 3/3] arm64: dts: imx8mm: add clock for GPIO node
>
> i.MX8MM has clock gate for each GPIO bank, add clock info to GPIO node for
> clock management.
>
> Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Regards
Dong Aisheng
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 6b407a94..f32d4e9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -206,6 +206,7 @@
> reg = <0x30200000 0x10000>;
> interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> @@ -217,6 +218,7 @@
> reg = <0x30210000 0x10000>;
> interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> @@ -228,6 +230,7 @@
> reg = <0x30220000 0x10000>;
> interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> @@ -239,6 +242,7 @@
> reg = <0x30230000 0x10000>;
> interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> @@ -250,6 +254,7 @@
> reg = <0x30240000 0x10000>;
> interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
> gpio-controller;
> #gpio-cells = <2>;
> interrupt-controller;
> --
> 2.7.4