2020-08-20 00:48:59

by Jiaxun Yang

Subject: [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache

Victim Cache is defined by Loongson as per-core unified
private Cache.
Add this into cacheinfo and make cache levels selfincrement
instead of hardcode levels.

Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++--------
1 file changed, 26 insertions(+), 8 deletions(-)

diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c
index 47312c529410..83548331ee94 100644
--- a/arch/mips/kernel/cacheinfo.c
+++ b/arch/mips/kernel/cacheinfo.c
@@ -35,6 +35,11 @@ static int __init_cache_level(unsigned int cpu)

leaves += (c->icache.waysize) ? 2 : 1;

+ if (c->vcache.waysize) {
+ levels++;
+ leaves++;
+ }
+
if (c->scache.waysize) {
levels++;
leaves++;
@@ -74,25 +79,38 @@ static int __populate_cache_leaves(unsigned int cpu)
struct cpuinfo_mips *c = &current_cpu_data;
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
struct cacheinfo *this_leaf = this_cpu_ci->info_list;
+ int level = 1;

if (c->icache.waysize) {
- /* L1 caches are per core */
+ /* D/I caches are per core */
fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
- populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA);
+ populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA);
fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
- populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST);
+ populate_cache(icache, this_leaf, level, CACHE_TYPE_INST);
+ level++;
} else {
- populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED);
+ populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
+ }
+
+ if (c->vcache.waysize) {
+ /* Vcache is per core as well */
+ fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
+ populate_cache(vcache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
}

if (c->scache.waysize) {
- /* L2 cache is per cluster */
+ /* Scache is per cluster */
fill_cpumask_cluster(cpu, &this_leaf->shared_cpu_map);
- populate_cache(scache, this_leaf, 2, CACHE_TYPE_UNIFIED);
+ populate_cache(scache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
}

- if (c->tcache.waysize)
- populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED);
+ if (c->tcache.waysize) {
+ populate_cache(tcache, this_leaf, level, CACHE_TYPE_UNIFIED);
+ level++;
+ }

this_cpu_ci->cpu_map_populated = true;

--
2.28.0

2020-08-21 17:06:40

by Thomas Bogendoerfer

Subject: Re: [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache

On Thu, Aug 20, 2020 at 08:42:49AM +0800, Jiaxun Yang wrote:
> Victim Cache is defined by Loongson as per-core unified
> private Cache.
> Add this into cacheinfo and make cache levels selfincrement
> instead of hardcode levels.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++--------
> 1 file changed, 26 insertions(+), 8 deletions(-)
>
> diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c
> index 47312c529410..83548331ee94 100644
> --- a/arch/mips/kernel/cacheinfo.c
> +++ b/arch/mips/kernel/cacheinfo.c
> @@ -35,6 +35,11 @@ static int __init_cache_level(unsigned int cpu)
>
> leaves += (c->icache.waysize) ? 2 : 1;
>
> + if (c->vcache.waysize) {
> + levels++;
> + leaves++;
> + }
> +
> if (c->scache.waysize) {
> levels++;
> leaves++;
> @@ -74,25 +79,38 @@ static int __populate_cache_leaves(unsigned int cpu)
> struct cpuinfo_mips *c = &current_cpu_data;
> struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
> struct cacheinfo *this_leaf = this_cpu_ci->info_list;
> + int level = 1;
>
> if (c->icache.waysize) {
> - /* L1 caches are per core */
> + /* D/I caches are per core */
> fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
> - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA);
> + populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA);
> fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
> - populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST);
> + populate_cache(icache, this_leaf, level, CACHE_TYPE_INST);
> + level++;
> } else {
> - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED);
> + populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED);
> + level++;
> + }
> +
> + if (c->vcache.waysize) {

why can't we insert vcache as level 4 and leave the rest of the file
alone ?

Thomas.

--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]

2020-11-03 05:42:40

by Jiaxun Yang

Subject: Re: [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache

在 2020/8/22 0:55, Thomas Bogendoerfer 写道:
> On Thu, Aug 20, 2020 at 08:42:49AM +0800, Jiaxun Yang wrote:
>> Victim Cache is defined by Loongson as per-core unified
>> private Cache.
>> Add this into cacheinfo and make cache levels selfincrement
>> instead of hardcode levels.
>>
>> Signed-off-by: Jiaxun Yang <[email protected]>
>> ---
>> arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++--------
>> 1 file changed, 26 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c
>> index 47312c529410..83548331ee94 100644
>> --- a/arch/mips/kernel/cacheinfo.c
>> +++ b/arch/mips/kernel/cacheinfo.c
>> @@ -35,6 +35,11 @@ static int __init_cache_level(unsigned int cpu)
>>
>> leaves += (c->icache.waysize) ? 2 : 1;
>>
>> + if (c->vcache.waysize) {
>> + levels++;
>> + leaves++;
>> + }
>> +
>> if (c->scache.waysize) {
>> levels++;
>> leaves++;
>> @@ -74,25 +79,38 @@ static int __populate_cache_leaves(unsigned int cpu)
>> struct cpuinfo_mips *c = &current_cpu_data;
>> struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
>> struct cacheinfo *this_leaf = this_cpu_ci->info_list;
>> + int level = 1;
>>
>> if (c->icache.waysize) {
>> - /* L1 caches are per core */
>> + /* D/I caches are per core */
>> fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
>> - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA);
>> + populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA);
>> fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
>> - populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST);
>> + populate_cache(icache, this_leaf, level, CACHE_TYPE_INST);
>> + level++;
>> } else {
>> - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED);
>> + populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED);
>> + level++;
>> + }
>> +
>> + if (c->vcache.waysize) {
> why can't we insert vcache as level 4 and leave the rest of the file
> alone ?

Hi Thomas,

Oops I forgot this patch.

Because  VCache is physicaly placed between Scache and I/D Cache as per
core chahe, it will confuse userspace program otherwise.

Also I do think the level should be continues.

Thanks

- Jiaxun

>
> Thomas.
>

2020-11-25 08:17:59

by Tiezhu Yang

Subject: Re: [PATCH RESEND 1/2] MIPS: cacheinfo: Add missing VCache

On 11/03/2020 01:40 PM, Jiaxun Yang wrote:
>
>
> 在 2020/8/22 0:55, Thomas Bogendoerfer 写道:
>> On Thu, Aug 20, 2020 at 08:42:49AM +0800, Jiaxun Yang wrote:
>>> Victim Cache is defined by Loongson as per-core unified
>>> private Cache.
>>> Add this into cacheinfo and make cache levels selfincrement
>>> instead of hardcode levels.
>>>
>>> Signed-off-by: Jiaxun Yang <[email protected]>
>>> ---
>>> arch/mips/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++++--------
>>> 1 file changed, 26 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/arch/mips/kernel/cacheinfo.c
>>> b/arch/mips/kernel/cacheinfo.c
>>> index 47312c529410..83548331ee94 100644
>>> --- a/arch/mips/kernel/cacheinfo.c
>>> +++ b/arch/mips/kernel/cacheinfo.c
>>> @@ -35,6 +35,11 @@ static int __init_cache_level(unsigned int cpu)
>>> leaves += (c->icache.waysize) ? 2 : 1;
>>> + if (c->vcache.waysize) {
>>> + levels++;
>>> + leaves++;
>>> + }
>>> +
>>> if (c->scache.waysize) {
>>> levels++;
>>> leaves++;
>>> @@ -74,25 +79,38 @@ static int __populate_cache_leaves(unsigned int
>>> cpu)
>>> struct cpuinfo_mips *c = &current_cpu_data;
>>> struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
>>> struct cacheinfo *this_leaf = this_cpu_ci->info_list;
>>> + int level = 1;
>>> if (c->icache.waysize) {
>>> - /* L1 caches are per core */
>>> + /* D/I caches are per core */
>>> fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
>>> - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA);
>>> + populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA);
>>> fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
>>> - populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST);
>>> + populate_cache(icache, this_leaf, level, CACHE_TYPE_INST);
>>> + level++;
>>> } else {
>>> - populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED);
>>> + populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED);
>>> + level++;
>>> + }
>>> +
>>> + if (c->vcache.waysize) {
>> why can't we insert vcache as level 4 and leave the rest of the file
>> alone ?
>
> Hi Thomas,
>
> Oops I forgot this patch.
>
> Because VCache is physicaly placed between Scache and I/D Cache as per
> core chahe, it will confuse userspace program otherwise.
>
> Also I do think the level should be continues.

With this patch, we can see the vcache info as L2 cache
and scache info as L3 cache on the Loongson 3A3000
and 3A4000 platform.

Tested-by: Tiezhu Yang <[email protected]>

>
> Thanks
>
> - Jiaxun
>
>>
>> Thomas.
>>