2020-11-23 09:05:14

by Amelie Delaunay

Subject: [PATCH 0/3] STM32MP15 OTG params updates

This patchset brings some updates on STM32MP15 OTG HS and FS.
It sets ahbcfg parameter for both HS and FS as the value reported by the
hardware is not recommended.
It also disables Link Power Management on OTG HS because with some Host
controllers (at least seen with some USB 3.2 Gen2 controllers), OTG doesn't
succeed to exit L1 state.
It also enables FS/LS PHY clock selection when the Core is in FS Host mode,
to have 6MHz PHY clock when the connected device is LS, and 48Mhz PHY clock
otherwise.

Amelie Delaunay (3):
usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FS
usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTG
usb: dwc2: disable Link Power Management on STM32MP15 HS OTG

drivers/usb/dwc2/params.c | 8 ++++++++
1 file changed, 8 insertions(+)

--
2.17.1

2020-11-23 09:05:40

by Amelie Delaunay

Subject: [PATCH 3/3] usb: dwc2: disable Link Power Management on STM32MP15 HS OTG

Link Power Management (LPM) on STM32MP15 OTG HS encounters instabilities
with some Host controllers. OTG core fails to exit L1 state in 200us:
"dwc2 49000000.usb-otg: Failed to exit L1 sleep state in 200us."
Then the device is still not enumerated.

To avoid this issue, disable Link Power Management on STM32MP15 HS OTG.

Signed-off-by: Amelie Delaunay <[email protected]>
---
drivers/usb/dwc2/params.c | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 9e5dd7f3f2f6..92df3d620f7d 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -194,6 +194,10 @@ static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
p->host_perio_tx_fifo_size = 256;
p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+ p->lpm = false;
+ p->lpm_clock_gating = false;
+ p->besl = false;
+ p->hird_threshold_en = false;
}

const struct of_device_id dwc2_of_match_table[] = {
--
2.17.1

2020-11-23 09:07:15

by Amelie Delaunay

Subject: [PATCH 2/3] usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTG

When the core is in FS host mode, using the FS transceiver, and a Low-Speed
device is connected, transceiver clock is 6Mhz.
So, to support Low-Speed devices, enable support of FS/LS Low Power mode,
so that the PHY supplies a 6 MHz clock during Low-Speed mode.

Signed-off-by: Amelie Delaunay <[email protected]>
---
drivers/usb/dwc2/params.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 0df693319f0a..9e5dd7f3f2f6 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -179,6 +179,8 @@ static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
p->activate_stm_id_vb_detection = true;
p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+ p->host_support_fs_ls_low_power = true;
+ p->host_ls_low_power_phy_clk = true;
}

static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
--
2.17.1

2020-11-30 06:21:46

by Minas Harutyunyan

Subject: Re: [PATCH 2/3] usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTG

On 11/23/2020 1:01 PM, Amelie Delaunay wrote:
> When the core is in FS host mode, using the FS transceiver, and a Low-Speed
> device is connected, transceiver clock is 6Mhz.
> So, to support Low-Speed devices, enable support of FS/LS Low Power mode,
> so that the PHY supplies a 6 MHz clock during Low-Speed mode.
>
> Signed-off-by: Amelie Delaunay <[email protected]>

Acked-by: Minas Harutyunyan <[email protected]>

> ---
> drivers/usb/dwc2/params.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
> index 0df693319f0a..9e5dd7f3f2f6 100644
> --- a/drivers/usb/dwc2/params.c
> +++ b/drivers/usb/dwc2/params.c
> @@ -179,6 +179,8 @@ static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
> p->activate_stm_id_vb_detection = true;
> p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
> p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
> + p->host_support_fs_ls_low_power = true;
> + p->host_ls_low_power_phy_clk = true;
> }
>
> static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
>

2020-11-30 06:23:15

by Minas Harutyunyan

Subject: Re: [PATCH 3/3] usb: dwc2: disable Link Power Management on STM32MP15 HS OTG

On 11/23/2020 1:01 PM, Amelie Delaunay wrote:
> Link Power Management (LPM) on STM32MP15 OTG HS encounters instabilities
> with some Host controllers. OTG core fails to exit L1 state in 200us:
> "dwc2 49000000.usb-otg: Failed to exit L1 sleep state in 200us."
> Then the device is still not enumerated.
>
> To avoid this issue, disable Link Power Management on STM32MP15 HS OTG.
>
> Signed-off-by: Amelie Delaunay <[email protected]>

Acked-by: Minas Harutyunyan <[email protected]>

> ---
> drivers/usb/dwc2/params.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
> index 9e5dd7f3f2f6..92df3d620f7d 100644
> --- a/drivers/usb/dwc2/params.c
> +++ b/drivers/usb/dwc2/params.c
> @@ -194,6 +194,10 @@ static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
> p->host_perio_tx_fifo_size = 256;
> p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
> p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
> + p->lpm = false;
> + p->lpm_clock_gating = false;
> + p->besl = false;
> + p->hird_threshold_en = false;
> }
>
> const struct of_device_id dwc2_of_match_table[] = {
>