2021-04-06 11:29:58

by matthew.gerlach

[permalink] [raw]
Subject: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master

From: Matthew Gerlach <[email protected]>

This patch adds DFL bus driver for the Altera SPI Master
controller. The SPI master is connected to an Intel SPI Slave to
Avalon Master Bridge, inside an Intel MAX10 BMC Chip.

Signed-off-by: Matthew Gerlach <[email protected]>
---
drivers/fpga/Kconfig | 9 ++
drivers/fpga/Makefile | 1 +
drivers/fpga/dfl-spi-altera.c | 221 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 231 insertions(+)
create mode 100644 drivers/fpga/dfl-spi-altera.c

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index d591dd9..0a86994 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
the card. It also instantiates the SPI master (spi-altera) for
the card's BMC (Board Management Controller).

+config FPGA_DFL_SPI_ALTERA
+ tristate "FPGA DFL Altera SPI Master Driver"
+ depends on FPGA_DFL
+ select REGMAP
+ help
+ This is a DFL bus driver for the Altera SPI master controller.
+ The SPI master is connected to a SPI slave to Avalon Master
+ bridge in a Intel MAX BMC.
+
config FPGA_DFL_PCI
tristate "FPGA DFL PCIe Device Driver"
depends on PCI && FPGA_DFL
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 18dc9885..58a42ad 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o
dfl-afu-objs += dfl-afu-error.o

obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o
+obj-$(CONFIG_FPGA_DFL_SPI_ALTERA) += dfl-spi-altera.o

# Drivers for FPGAs which implement DFL
obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
diff --git a/drivers/fpga/dfl-spi-altera.c b/drivers/fpga/dfl-spi-altera.c
new file mode 100644
index 0000000..9bec25fd
--- /dev/null
+++ b/drivers/fpga/dfl-spi-altera.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DFL bus driver for Altera SPI Master
+ *
+ * Copyright (C) 2020 Intel Corporation, Inc.
+ *
+ * Authors:
+ * Matthew Gerlach <[email protected]>
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/stddef.h>
+#include <linux/errno.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/bitfield.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/regmap.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/altera.h>
+#include <linux/dfl.h>
+
+struct dfl_altera_spi {
+ void __iomem *base;
+ struct regmap *regmap;
+ struct device *dev;
+ struct platform_device *altr_spi;
+};
+
+#define SPI_CORE_PARAMETER 0x8
+#define SHIFT_MODE BIT_ULL(1)
+#define SHIFT_MODE_MSB 0
+#define SHIFT_MODE_LSB 1
+#define DATA_WIDTH GENMASK_ULL(7, 2)
+#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
+#define CLK_POLARITY BIT_ULL(14)
+#define CLK_PHASE BIT_ULL(15)
+#define PERIPHERAL_ID GENMASK_ULL(47, 32)
+#define SPI_CLK GENMASK_ULL(31, 22)
+#define SPI_INDIRECT_ACC_OFST 0x10
+
+#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
+#define INDIRECT_WR BIT_ULL(8)
+#define INDIRECT_RD BIT_ULL(9)
+#define INDIRECT_RD_DATA (SPI_INDIRECT_ACC_OFST+0x8)
+#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
+#define INDIRECT_DEBUG BIT_ULL(32)
+#define INDIRECT_WR_DATA (SPI_INDIRECT_ACC_OFST+0x10)
+#define INDIRECT_TIMEOUT 10000
+
+static int indirect_bus_reg_read(void *context, unsigned int reg,
+ unsigned int *val)
+{
+ struct dfl_altera_spi *aspi = context;
+ void __iomem *base = aspi->base;
+ int loops;
+ u64 v;
+
+ writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
+
+ loops = 0;
+ while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
+ (loops++ < INDIRECT_TIMEOUT))
+ cpu_relax();
+
+ if (loops >= INDIRECT_TIMEOUT) {
+ pr_err("%s timed out %d\n", __func__, loops);
+ return -ETIME;
+ }
+
+ v = readq(base + INDIRECT_RD_DATA);
+
+ *val = v & INDIRECT_DATA_MASK;
+
+ return 0;
+}
+
+static int indirect_bus_reg_write(void *context, unsigned int reg,
+ unsigned int val)
+{
+ struct dfl_altera_spi *aspi = context;
+ void __iomem *base = aspi->base;
+ int loops;
+
+ writeq(val, base + INDIRECT_WR_DATA);
+ writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
+
+ loops = 0;
+ while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
+ (loops++ < INDIRECT_TIMEOUT))
+ cpu_relax();
+
+ if (loops >= INDIRECT_TIMEOUT) {
+ pr_err("%s timed out %d\n", __func__, loops);
+ return -ETIME;
+ }
+ return 0;
+}
+
+static const struct regmap_config indirect_regbus_cfg = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .fast_io = true,
+
+ .reg_write = indirect_bus_reg_write,
+ .reg_read = indirect_bus_reg_read,
+};
+
+static struct spi_board_info m10_bmc_info = {
+ .modalias = "m10-d5005",
+ .max_speed_hz = 12500000,
+ .bus_num = 0,
+ .chip_select = 0,
+};
+
+static struct platform_device *create_cntrl(struct device *dev,
+ void __iomem *base,
+ struct spi_board_info *m10_info)
+{
+ struct altera_spi_platform_data pdata;
+ struct platform_device_info pdevinfo;
+ u64 v;
+
+ v = readq(base + SPI_CORE_PARAMETER);
+
+ memset(&pdata, 0, sizeof(pdata));
+ pdata.mode_bits = SPI_CS_HIGH;
+ if (FIELD_GET(CLK_POLARITY, v))
+ pdata.mode_bits |= SPI_CPOL;
+ if (FIELD_GET(CLK_PHASE, v))
+ pdata.mode_bits |= SPI_CPHA;
+
+ pdata.num_chipselect = FIELD_GET(NUM_CHIPSELECT, v);
+ pdata.bits_per_word_mask =
+ SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v));
+
+ pdata.num_devices = 1;
+ pdata.devices = m10_info;
+
+ dev_dbg(dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__,
+ pdata.num_chipselect, pdata.bits_per_word_mask,
+ pdata.mode_bits);
+
+ memset(&pdevinfo, 0, sizeof(pdevinfo));
+
+ pdevinfo.name = "subdev_spi_altera";
+ pdevinfo.id = PLATFORM_DEVID_AUTO;
+ pdevinfo.parent = dev;
+ pdevinfo.data = &pdata;
+ pdevinfo.size_data = sizeof(pdata);
+
+ return platform_device_register_full(&pdevinfo);
+}
+static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
+{
+ struct device *dev = &dfl_dev->dev;
+ struct dfl_altera_spi *aspi;
+
+ aspi = devm_kzalloc(dev, sizeof(*aspi), GFP_KERNEL);
+
+ if (!aspi)
+ return -ENOMEM;
+
+ dev_set_drvdata(dev, aspi);
+
+ aspi->dev = dev;
+
+ aspi->base = devm_ioremap_resource(dev, &dfl_dev->mmio_res);
+
+ if (IS_ERR(aspi->base)) {
+ dev_err(dev, "%s get mem resource fail!\n", __func__);
+ return PTR_ERR(aspi->base);
+ }
+
+ aspi->regmap = devm_regmap_init(dev, NULL, aspi, &indirect_regbus_cfg);
+ if (IS_ERR(aspi->regmap))
+ return PTR_ERR(aspi->regmap);
+
+ aspi->altr_spi = create_cntrl(dev, aspi->base, &m10_bmc_info);
+
+ if (IS_ERR(aspi->altr_spi)) {
+ dev_err(dev, "%s failed to create spi platform driver\n",
+ __func__);
+ return PTR_ERR(aspi->base);
+ }
+
+ return 0;
+}
+
+static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
+{
+ struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
+
+ platform_device_unregister(aspi->altr_spi);
+}
+
+#define FME_FEATURE_ID_MAX10_SPI 0xe
+
+static const struct dfl_device_id dfl_spi_altera_ids[] = {
+ { FME_ID, FME_FEATURE_ID_MAX10_SPI },
+ { }
+};
+
+static struct dfl_driver dfl_spi_altera_driver = {
+ .drv = {
+ .name = "dfl-spi-altera",
+ },
+ .id_table = dfl_spi_altera_ids,
+ .probe = dfl_spi_altera_probe,
+ .remove = dfl_spi_altera_remove,
+};
+
+module_dfl_driver(dfl_spi_altera_driver);
+
+MODULE_DEVICE_TABLE(dfl, dfl_spi_altera_ids);
+MODULE_DESCRIPTION("DFL spi altera driver");
+MODULE_AUTHOR("Intel Corporation");
+MODULE_LICENSE("GPL v2");
--
1.8.3.1


2021-04-06 12:22:44

by Moritz Fischer

[permalink] [raw]
Subject: Re: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master

Hi Matthew,

On Mon, Apr 05, 2021 at 04:53:00PM -0700, [email protected] wrote:
> From: Matthew Gerlach <[email protected]>
>
> This patch adds DFL bus driver for the Altera SPI Master
> controller. The SPI master is connected to an Intel SPI Slave to
> Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
>
> Signed-off-by: Matthew Gerlach <[email protected]>
> ---
> drivers/fpga/Kconfig | 9 ++
> drivers/fpga/Makefile | 1 +
> drivers/fpga/dfl-spi-altera.c | 221 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 231 insertions(+)
> create mode 100644 drivers/fpga/dfl-spi-altera.c
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index d591dd9..0a86994 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
> the card. It also instantiates the SPI master (spi-altera) for
> the card's BMC (Board Management Controller).
>
> +config FPGA_DFL_SPI_ALTERA
> + tristate "FPGA DFL Altera SPI Master Driver"
> + depends on FPGA_DFL
> + select REGMAP
> + help
> + This is a DFL bus driver for the Altera SPI master controller.
> + The SPI master is connected to a SPI slave to Avalon Master
> + bridge in a Intel MAX BMC.
> +
> config FPGA_DFL_PCI
> tristate "FPGA DFL PCIe Device Driver"
> depends on PCI && FPGA_DFL
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 18dc9885..58a42ad 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o
> dfl-afu-objs += dfl-afu-error.o
>
> obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o
> +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA) += dfl-spi-altera.o
>
> # Drivers for FPGAs which implement DFL
> obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
> diff --git a/drivers/fpga/dfl-spi-altera.c b/drivers/fpga/dfl-spi-altera.c
> new file mode 100644
> index 0000000..9bec25fd
> --- /dev/null
> +++ b/drivers/fpga/dfl-spi-altera.c
> @@ -0,0 +1,221 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * DFL bus driver for Altera SPI Master
> + *
> + * Copyright (C) 2020 Intel Corporation, Inc.
> + *
> + * Authors:
> + * Matthew Gerlach <[email protected]>
> + */
> +
> +#include <linux/types.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/stddef.h>
> +#include <linux/errno.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +#include <linux/bitfield.h>
> +#include <linux/io-64-nonatomic-lo-hi.h>
> +#include <linux/regmap.h>
> +#include <linux/spi/spi.h>
> +#include <linux/spi/altera.h>
> +#include <linux/dfl.h>
> +
> +struct dfl_altera_spi {
> + void __iomem *base;
> + struct regmap *regmap;
> + struct device *dev;
> + struct platform_device *altr_spi;
> +};
> +
> +#define SPI_CORE_PARAMETER 0x8
> +#define SHIFT_MODE BIT_ULL(1)
> +#define SHIFT_MODE_MSB 0
> +#define SHIFT_MODE_LSB 1
> +#define DATA_WIDTH GENMASK_ULL(7, 2)
> +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> +#define CLK_POLARITY BIT_ULL(14)
> +#define CLK_PHASE BIT_ULL(15)
> +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> +#define SPI_CLK GENMASK_ULL(31, 22)
> +#define SPI_INDIRECT_ACC_OFST 0x10
> +
> +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> +#define INDIRECT_WR BIT_ULL(8)
> +#define INDIRECT_RD BIT_ULL(9)
> +#define INDIRECT_RD_DATA (SPI_INDIRECT_ACC_OFST+0x8)
> +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> +#define INDIRECT_DEBUG BIT_ULL(32)
> +#define INDIRECT_WR_DATA (SPI_INDIRECT_ACC_OFST+0x10)
> +#define INDIRECT_TIMEOUT 10000
> +
> +static int indirect_bus_reg_read(void *context, unsigned int reg,
> + unsigned int *val)
> +{
> + struct dfl_altera_spi *aspi = context;
> + void __iomem *base = aspi->base;
> + int loops;
> + u64 v;
> +
> + writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
> +
> + loops = 0;
> + while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
> + (loops++ < INDIRECT_TIMEOUT))
> + cpu_relax();
> +
> + if (loops >= INDIRECT_TIMEOUT) {
> + pr_err("%s timed out %d\n", __func__, loops);
> + return -ETIME;
> + }
> +
> + v = readq(base + INDIRECT_RD_DATA);
> +
> + *val = v & INDIRECT_DATA_MASK;
> +
> + return 0;
> +}
> +
> +static int indirect_bus_reg_write(void *context, unsigned int reg,
> + unsigned int val)
> +{
> + struct dfl_altera_spi *aspi = context;
> + void __iomem *base = aspi->base;
> + int loops;
> +
> + writeq(val, base + INDIRECT_WR_DATA);
> + writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
> +
> + loops = 0;
> + while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
> + (loops++ < INDIRECT_TIMEOUT))
> + cpu_relax();
> +
> + if (loops >= INDIRECT_TIMEOUT) {
> + pr_err("%s timed out %d\n", __func__, loops);
> + return -ETIME;
> + }
> + return 0;
> +}
> +
> +static const struct regmap_config indirect_regbus_cfg = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .fast_io = true,
> +
> + .reg_write = indirect_bus_reg_write,
> + .reg_read = indirect_bus_reg_read,
> +};
> +
> +static struct spi_board_info m10_bmc_info = {
> + .modalias = "m10-d5005",
> + .max_speed_hz = 12500000,
> + .bus_num = 0,
> + .chip_select = 0,
> +};
> +
> +static struct platform_device *create_cntrl(struct device *dev,
> + void __iomem *base,
> + struct spi_board_info *m10_info)
> +{
> + struct altera_spi_platform_data pdata;
> + struct platform_device_info pdevinfo;
> + u64 v;
> +
> + v = readq(base + SPI_CORE_PARAMETER);
> +
> + memset(&pdata, 0, sizeof(pdata));
> + pdata.mode_bits = SPI_CS_HIGH;
> + if (FIELD_GET(CLK_POLARITY, v))
> + pdata.mode_bits |= SPI_CPOL;
> + if (FIELD_GET(CLK_PHASE, v))
> + pdata.mode_bits |= SPI_CPHA;
> +
> + pdata.num_chipselect = FIELD_GET(NUM_CHIPSELECT, v);
> + pdata.bits_per_word_mask =
> + SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v));
> +
> + pdata.num_devices = 1;
> + pdata.devices = m10_info;
> +
> + dev_dbg(dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__,
> + pdata.num_chipselect, pdata.bits_per_word_mask,
> + pdata.mode_bits);
> +
> + memset(&pdevinfo, 0, sizeof(pdevinfo));
> +
> + pdevinfo.name = "subdev_spi_altera";
> + pdevinfo.id = PLATFORM_DEVID_AUTO;
> + pdevinfo.parent = dev;
> + pdevinfo.data = &pdata;
> + pdevinfo.size_data = sizeof(pdata);
> +
> + return platform_device_register_full(&pdevinfo);

Should this be a SPI driver? I think looking at the UIO case we had
decided against this pattern?

> +}
> +static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
> +{
> + struct device *dev = &dfl_dev->dev;
> + struct dfl_altera_spi *aspi;
> +
> + aspi = devm_kzalloc(dev, sizeof(*aspi), GFP_KERNEL);
> +
> + if (!aspi)
> + return -ENOMEM;
> +
> + dev_set_drvdata(dev, aspi);
> +
> + aspi->dev = dev;
> +
> + aspi->base = devm_ioremap_resource(dev, &dfl_dev->mmio_res);
> +
> + if (IS_ERR(aspi->base)) {
> + dev_err(dev, "%s get mem resource fail!\n", __func__);
> + return PTR_ERR(aspi->base);
> + }
> +
> + aspi->regmap = devm_regmap_init(dev, NULL, aspi, &indirect_regbus_cfg);
> + if (IS_ERR(aspi->regmap))
> + return PTR_ERR(aspi->regmap);
> +
> + aspi->altr_spi = create_cntrl(dev, aspi->base, &m10_bmc_info);
> +
> + if (IS_ERR(aspi->altr_spi)) {
> + dev_err(dev, "%s failed to create spi platform driver\n",
> + __func__);
> + return PTR_ERR(aspi->base);
> + }
> +
> + return 0;
> +}
> +
> +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> +{
> + struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
> +
> + platform_device_unregister(aspi->altr_spi);
> +}
> +
> +#define FME_FEATURE_ID_MAX10_SPI 0xe
> +
> +static const struct dfl_device_id dfl_spi_altera_ids[] = {
> + { FME_ID, FME_FEATURE_ID_MAX10_SPI },
> + { }
> +};

Maybe you can extend the Altera SPI driver with this part?
> +
> +static struct dfl_driver dfl_spi_altera_driver = {
> + .drv = {
> + .name = "dfl-spi-altera",
> + },
> + .id_table = dfl_spi_altera_ids,
> + .probe = dfl_spi_altera_probe,
> + .remove = dfl_spi_altera_remove,
> +};
> +
> +module_dfl_driver(dfl_spi_altera_driver);
> +
> +MODULE_DEVICE_TABLE(dfl, dfl_spi_altera_ids);
> +MODULE_DESCRIPTION("DFL spi altera driver");
> +MODULE_AUTHOR("Intel Corporation");
> +MODULE_LICENSE("GPL v2");
> --
> 1.8.3.1
>

- Moritz

2021-04-07 07:10:28

by matthew.gerlach

[permalink] [raw]
Subject: Re: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master


Hi Moritz,

On Mon, 5 Apr 2021, Moritz Fischer wrote:

> Hi Matthew,
>
> On Mon, Apr 05, 2021 at 04:53:00PM -0700, [email protected] wrote:
>> From: Matthew Gerlach <[email protected]>
>>
>> This patch adds DFL bus driver for the Altera SPI Master
>> controller. The SPI master is connected to an Intel SPI Slave to
>> Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
>>
>> Signed-off-by: Matthew Gerlach <[email protected]>
>> ---
>> drivers/fpga/Kconfig | 9 ++
>> drivers/fpga/Makefile | 1 +
>> drivers/fpga/dfl-spi-altera.c | 221 ++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 231 insertions(+)
>> create mode 100644 drivers/fpga/dfl-spi-altera.c
>>
>> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
>> index d591dd9..0a86994 100644
>> --- a/drivers/fpga/Kconfig
>> +++ b/drivers/fpga/Kconfig
>> @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
>> the card. It also instantiates the SPI master (spi-altera) for
>> the card's BMC (Board Management Controller).
>>
>> +config FPGA_DFL_SPI_ALTERA
>> + tristate "FPGA DFL Altera SPI Master Driver"
>> + depends on FPGA_DFL
>> + select REGMAP
>> + help
>> + This is a DFL bus driver for the Altera SPI master controller.
>> + The SPI master is connected to a SPI slave to Avalon Master
>> + bridge in a Intel MAX BMC.
>> +
>> config FPGA_DFL_PCI
>> tristate "FPGA DFL PCIe Device Driver"
>> depends on PCI && FPGA_DFL
>> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
>> index 18dc9885..58a42ad 100644
>> --- a/drivers/fpga/Makefile
>> +++ b/drivers/fpga/Makefile
>> @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o
>> dfl-afu-objs += dfl-afu-error.o
>>
>> obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o
>> +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA) += dfl-spi-altera.o
>>
>> # Drivers for FPGAs which implement DFL
>> obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
>> diff --git a/drivers/fpga/dfl-spi-altera.c b/drivers/fpga/dfl-spi-altera.c
>> new file mode 100644
>> index 0000000..9bec25fd
>> --- /dev/null
>> +++ b/drivers/fpga/dfl-spi-altera.c
>> @@ -0,0 +1,221 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * DFL bus driver for Altera SPI Master
>> + *
>> + * Copyright (C) 2020 Intel Corporation, Inc.
>> + *
>> + * Authors:
>> + * Matthew Gerlach <[email protected]>
>> + */
>> +
>> +#include <linux/types.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/stddef.h>
>> +#include <linux/errno.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/io.h>
>> +#include <linux/bitfield.h>
>> +#include <linux/io-64-nonatomic-lo-hi.h>
>> +#include <linux/regmap.h>
>> +#include <linux/spi/spi.h>
>> +#include <linux/spi/altera.h>
>> +#include <linux/dfl.h>
>> +
>> +struct dfl_altera_spi {
>> + void __iomem *base;
>> + struct regmap *regmap;
>> + struct device *dev;
>> + struct platform_device *altr_spi;
>> +};
>> +
>> +#define SPI_CORE_PARAMETER 0x8
>> +#define SHIFT_MODE BIT_ULL(1)
>> +#define SHIFT_MODE_MSB 0
>> +#define SHIFT_MODE_LSB 1
>> +#define DATA_WIDTH GENMASK_ULL(7, 2)
>> +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
>> +#define CLK_POLARITY BIT_ULL(14)
>> +#define CLK_PHASE BIT_ULL(15)
>> +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
>> +#define SPI_CLK GENMASK_ULL(31, 22)
>> +#define SPI_INDIRECT_ACC_OFST 0x10
>> +
>> +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
>> +#define INDIRECT_WR BIT_ULL(8)
>> +#define INDIRECT_RD BIT_ULL(9)
>> +#define INDIRECT_RD_DATA (SPI_INDIRECT_ACC_OFST+0x8)
>> +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
>> +#define INDIRECT_DEBUG BIT_ULL(32)
>> +#define INDIRECT_WR_DATA (SPI_INDIRECT_ACC_OFST+0x10)
>> +#define INDIRECT_TIMEOUT 10000
>> +
>> +static int indirect_bus_reg_read(void *context, unsigned int reg,
>> + unsigned int *val)
>> +{
>> + struct dfl_altera_spi *aspi = context;
>> + void __iomem *base = aspi->base;
>> + int loops;
>> + u64 v;
>> +
>> + writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
>> +
>> + loops = 0;
>> + while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
>> + (loops++ < INDIRECT_TIMEOUT))
>> + cpu_relax();
>> +
>> + if (loops >= INDIRECT_TIMEOUT) {
>> + pr_err("%s timed out %d\n", __func__, loops);
>> + return -ETIME;
>> + }
>> +
>> + v = readq(base + INDIRECT_RD_DATA);
>> +
>> + *val = v & INDIRECT_DATA_MASK;
>> +
>> + return 0;
>> +}
>> +
>> +static int indirect_bus_reg_write(void *context, unsigned int reg,
>> + unsigned int val)
>> +{
>> + struct dfl_altera_spi *aspi = context;
>> + void __iomem *base = aspi->base;
>> + int loops;
>> +
>> + writeq(val, base + INDIRECT_WR_DATA);
>> + writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
>> +
>> + loops = 0;
>> + while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
>> + (loops++ < INDIRECT_TIMEOUT))
>> + cpu_relax();
>> +
>> + if (loops >= INDIRECT_TIMEOUT) {
>> + pr_err("%s timed out %d\n", __func__, loops);
>> + return -ETIME;
>> + }
>> + return 0;
>> +}
>> +
>> +static const struct regmap_config indirect_regbus_cfg = {
>> + .reg_bits = 32,
>> + .reg_stride = 4,
>> + .val_bits = 32,
>> + .fast_io = true,
>> +
>> + .reg_write = indirect_bus_reg_write,
>> + .reg_read = indirect_bus_reg_read,
>> +};
>> +
>> +static struct spi_board_info m10_bmc_info = {
>> + .modalias = "m10-d5005",
>> + .max_speed_hz = 12500000,
>> + .bus_num = 0,
>> + .chip_select = 0,
>> +};
>> +
>> +static struct platform_device *create_cntrl(struct device *dev,
>> + void __iomem *base,
>> + struct spi_board_info *m10_info)
>> +{
>> + struct altera_spi_platform_data pdata;
>> + struct platform_device_info pdevinfo;
>> + u64 v;
>> +
>> + v = readq(base + SPI_CORE_PARAMETER);
>> +
>> + memset(&pdata, 0, sizeof(pdata));
>> + pdata.mode_bits = SPI_CS_HIGH;
>> + if (FIELD_GET(CLK_POLARITY, v))
>> + pdata.mode_bits |= SPI_CPOL;
>> + if (FIELD_GET(CLK_PHASE, v))
>> + pdata.mode_bits |= SPI_CPHA;
>> +
>> + pdata.num_chipselect = FIELD_GET(NUM_CHIPSELECT, v);
>> + pdata.bits_per_word_mask =
>> + SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v));
>> +
>> + pdata.num_devices = 1;
>> + pdata.devices = m10_info;
>> +
>> + dev_dbg(dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__,
>> + pdata.num_chipselect, pdata.bits_per_word_mask,
>> + pdata.mode_bits);
>> +
>> + memset(&pdevinfo, 0, sizeof(pdevinfo));
>> +
>> + pdevinfo.name = "subdev_spi_altera";
>> + pdevinfo.id = PLATFORM_DEVID_AUTO;
>> + pdevinfo.parent = dev;
>> + pdevinfo.data = &pdata;
>> + pdevinfo.size_data = sizeof(pdata);
>> +
>> + return platform_device_register_full(&pdevinfo);
>
> Should this be a SPI driver? I think looking at the UIO case we had
> decided against this pattern?

This driver is similar in function to drivers/fpga/dfl-n3000-nios.c which
uses this design pattern. Is it okay to keep this design pattern for
consistency?


>
>> +}
>> +static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
>> +{
>> + struct device *dev = &dfl_dev->dev;
>> + struct dfl_altera_spi *aspi;
>> +
>> + aspi = devm_kzalloc(dev, sizeof(*aspi), GFP_KERNEL);
>> +
>> + if (!aspi)
>> + return -ENOMEM;
>> +
>> + dev_set_drvdata(dev, aspi);
>> +
>> + aspi->dev = dev;
>> +
>> + aspi->base = devm_ioremap_resource(dev, &dfl_dev->mmio_res);
>> +
>> + if (IS_ERR(aspi->base)) {
>> + dev_err(dev, "%s get mem resource fail!\n", __func__);
>> + return PTR_ERR(aspi->base);
>> + }
>> +
>> + aspi->regmap = devm_regmap_init(dev, NULL, aspi, &indirect_regbus_cfg);
>> + if (IS_ERR(aspi->regmap))
>> + return PTR_ERR(aspi->regmap);
>> +
>> + aspi->altr_spi = create_cntrl(dev, aspi->base, &m10_bmc_info);
>> +
>> + if (IS_ERR(aspi->altr_spi)) {
>> + dev_err(dev, "%s failed to create spi platform driver\n",
>> + __func__);
>> + return PTR_ERR(aspi->base);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
>> +{
>> + struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
>> +
>> + platform_device_unregister(aspi->altr_spi);
>> +}
>> +
>> +#define FME_FEATURE_ID_MAX10_SPI 0xe
>> +
>> +static const struct dfl_device_id dfl_spi_altera_ids[] = {
>> + { FME_ID, FME_FEATURE_ID_MAX10_SPI },
>> + { }
>> +};
>
> Maybe you can extend the Altera SPI driver with this part?

The file, drivers/spi/spi-altera.c, already has platform MODULE_ related
code. Wouldn't moving this code to that file produce conflicts?


>> +
>> +static struct dfl_driver dfl_spi_altera_driver = {
>> + .drv = {
>> + .name = "dfl-spi-altera",
>> + },
>> + .id_table = dfl_spi_altera_ids,
>> + .probe = dfl_spi_altera_probe,
>> + .remove = dfl_spi_altera_remove,
>> +};
>> +
>> +module_dfl_driver(dfl_spi_altera_driver);
>> +
>> +MODULE_DEVICE_TABLE(dfl, dfl_spi_altera_ids);
>> +MODULE_DESCRIPTION("DFL spi altera driver");
>> +MODULE_AUTHOR("Intel Corporation");
>> +MODULE_LICENSE("GPL v2");
>> --
>> 1.8.3.1
>>
>
> - Moritz
>

2021-04-07 10:25:08

by Moritz Fischer

[permalink] [raw]
Subject: Re: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master

Hi Matthew,

On Tue, Apr 06, 2021 at 09:05:35AM -0700, [email protected] wrote:
>
> Hi Moritz,
>
> On Mon, 5 Apr 2021, Moritz Fischer wrote:
>
> > Hi Matthew,
> >
> > On Mon, Apr 05, 2021 at 04:53:00PM -0700, [email protected] wrote:
> > > From: Matthew Gerlach <[email protected]>
> > >
> > > This patch adds DFL bus driver for the Altera SPI Master
> > > controller. The SPI master is connected to an Intel SPI Slave to
> > > Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
> > >
> > > Signed-off-by: Matthew Gerlach <[email protected]>
> > > ---
> > > drivers/fpga/Kconfig | 9 ++
> > > drivers/fpga/Makefile | 1 +
> > > drivers/fpga/dfl-spi-altera.c | 221 ++++++++++++++++++++++++++++++++++++++++++
> > > 3 files changed, 231 insertions(+)
> > > create mode 100644 drivers/fpga/dfl-spi-altera.c
> > >
> > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > index d591dd9..0a86994 100644
> > > --- a/drivers/fpga/Kconfig
> > > +++ b/drivers/fpga/Kconfig
> > > @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
> > > the card. It also instantiates the SPI master (spi-altera) for
> > > the card's BMC (Board Management Controller).
> > >
> > > +config FPGA_DFL_SPI_ALTERA
> > > + tristate "FPGA DFL Altera SPI Master Driver"
> > > + depends on FPGA_DFL
> > > + select REGMAP
> > > + help
> > > + This is a DFL bus driver for the Altera SPI master controller.
> > > + The SPI master is connected to a SPI slave to Avalon Master
> > > + bridge in a Intel MAX BMC.
> > > +
> > > config FPGA_DFL_PCI
> > > tristate "FPGA DFL PCIe Device Driver"
> > > depends on PCI && FPGA_DFL
> > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > index 18dc9885..58a42ad 100644
> > > --- a/drivers/fpga/Makefile
> > > +++ b/drivers/fpga/Makefile
> > > @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o
> > > dfl-afu-objs += dfl-afu-error.o
> > >
> > > obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o
> > > +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA) += dfl-spi-altera.o
> > >
> > > # Drivers for FPGAs which implement DFL
> > > obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
> > > diff --git a/drivers/fpga/dfl-spi-altera.c b/drivers/fpga/dfl-spi-altera.c
> > > new file mode 100644
> > > index 0000000..9bec25fd
> > > --- /dev/null
> > > +++ b/drivers/fpga/dfl-spi-altera.c
> > > @@ -0,0 +1,221 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * DFL bus driver for Altera SPI Master
> > > + *
> > > + * Copyright (C) 2020 Intel Corporation, Inc.
> > > + *
> > > + * Authors:
> > > + * Matthew Gerlach <[email protected]>
> > > + */
> > > +
> > > +#include <linux/types.h>
> > > +#include <linux/kernel.h>
> > > +#include <linux/module.h>
> > > +#include <linux/stddef.h>
> > > +#include <linux/errno.h>
> > > +#include <linux/platform_device.h>
> > > +#include <linux/io.h>
> > > +#include <linux/bitfield.h>
> > > +#include <linux/io-64-nonatomic-lo-hi.h>
> > > +#include <linux/regmap.h>
> > > +#include <linux/spi/spi.h>
> > > +#include <linux/spi/altera.h>
> > > +#include <linux/dfl.h>
> > > +
> > > +struct dfl_altera_spi {
> > > + void __iomem *base;
> > > + struct regmap *regmap;
> > > + struct device *dev;
> > > + struct platform_device *altr_spi;
> > > +};
> > > +
> > > +#define SPI_CORE_PARAMETER 0x8
> > > +#define SHIFT_MODE BIT_ULL(1)
> > > +#define SHIFT_MODE_MSB 0
> > > +#define SHIFT_MODE_LSB 1
> > > +#define DATA_WIDTH GENMASK_ULL(7, 2)
> > > +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> > > +#define CLK_POLARITY BIT_ULL(14)
> > > +#define CLK_PHASE BIT_ULL(15)
> > > +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> > > +#define SPI_CLK GENMASK_ULL(31, 22)
> > > +#define SPI_INDIRECT_ACC_OFST 0x10
> > > +
> > > +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> > > +#define INDIRECT_WR BIT_ULL(8)
> > > +#define INDIRECT_RD BIT_ULL(9)
> > > +#define INDIRECT_RD_DATA (SPI_INDIRECT_ACC_OFST+0x8)
> > > +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> > > +#define INDIRECT_DEBUG BIT_ULL(32)
> > > +#define INDIRECT_WR_DATA (SPI_INDIRECT_ACC_OFST+0x10)
> > > +#define INDIRECT_TIMEOUT 10000
> > > +
> > > +static int indirect_bus_reg_read(void *context, unsigned int reg,
> > > + unsigned int *val)
> > > +{
> > > + struct dfl_altera_spi *aspi = context;
> > > + void __iomem *base = aspi->base;
> > > + int loops;
> > > + u64 v;
> > > +
> > > + writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
> > > +
> > > + loops = 0;
> > > + while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
> > > + (loops++ < INDIRECT_TIMEOUT))
> > > + cpu_relax();
> > > +
> > > + if (loops >= INDIRECT_TIMEOUT) {
> > > + pr_err("%s timed out %d\n", __func__, loops);
> > > + return -ETIME;
> > > + }
> > > +
> > > + v = readq(base + INDIRECT_RD_DATA);
> > > +
> > > + *val = v & INDIRECT_DATA_MASK;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int indirect_bus_reg_write(void *context, unsigned int reg,
> > > + unsigned int val)
> > > +{
> > > + struct dfl_altera_spi *aspi = context;
> > > + void __iomem *base = aspi->base;
> > > + int loops;
> > > +
> > > + writeq(val, base + INDIRECT_WR_DATA);
> > > + writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
> > > +
> > > + loops = 0;
> > > + while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
> > > + (loops++ < INDIRECT_TIMEOUT))
> > > + cpu_relax();
> > > +
> > > + if (loops >= INDIRECT_TIMEOUT) {
> > > + pr_err("%s timed out %d\n", __func__, loops);
> > > + return -ETIME;
> > > + }
> > > + return 0;
> > > +}
> > > +
> > > +static const struct regmap_config indirect_regbus_cfg = {
> > > + .reg_bits = 32,
> > > + .reg_stride = 4,
> > > + .val_bits = 32,
> > > + .fast_io = true,
> > > +
> > > + .reg_write = indirect_bus_reg_write,
> > > + .reg_read = indirect_bus_reg_read,
> > > +};
> > > +
> > > +static struct spi_board_info m10_bmc_info = {
> > > + .modalias = "m10-d5005",
> > > + .max_speed_hz = 12500000,
> > > + .bus_num = 0,
> > > + .chip_select = 0,
> > > +};
> > > +
> > > +static struct platform_device *create_cntrl(struct device *dev,
> > > + void __iomem *base,
> > > + struct spi_board_info *m10_info)
> > > +{
> > > + struct altera_spi_platform_data pdata;
> > > + struct platform_device_info pdevinfo;
> > > + u64 v;
> > > +
> > > + v = readq(base + SPI_CORE_PARAMETER);
> > > +
> > > + memset(&pdata, 0, sizeof(pdata));
> > > + pdata.mode_bits = SPI_CS_HIGH;
> > > + if (FIELD_GET(CLK_POLARITY, v))
> > > + pdata.mode_bits |= SPI_CPOL;
> > > + if (FIELD_GET(CLK_PHASE, v))
> > > + pdata.mode_bits |= SPI_CPHA;
> > > +
> > > + pdata.num_chipselect = FIELD_GET(NUM_CHIPSELECT, v);
> > > + pdata.bits_per_word_mask =
> > > + SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v));
> > > +
> > > + pdata.num_devices = 1;
> > > + pdata.devices = m10_info;
> > > +
> > > + dev_dbg(dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__,
> > > + pdata.num_chipselect, pdata.bits_per_word_mask,
> > > + pdata.mode_bits);
> > > +
> > > + memset(&pdevinfo, 0, sizeof(pdevinfo));
> > > +
> > > + pdevinfo.name = "subdev_spi_altera";
> > > + pdevinfo.id = PLATFORM_DEVID_AUTO;
> > > + pdevinfo.parent = dev;
> > > + pdevinfo.data = &pdata;
> > > + pdevinfo.size_data = sizeof(pdata);
> > > +
> > > + return platform_device_register_full(&pdevinfo);
> >
> > Should this be a SPI driver? I think looking at the UIO case we had
> > decided against this pattern?
>
> This driver is similar in function to drivers/fpga/dfl-n3000-nios.c which
> uses this design pattern. Is it okay to keep this design pattern for
> consistency?
>
>
> >
> > > +}
> > > +static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
> > > +{
> > > + struct device *dev = &dfl_dev->dev;
> > > + struct dfl_altera_spi *aspi;
> > > +
> > > + aspi = devm_kzalloc(dev, sizeof(*aspi), GFP_KERNEL);
> > > +
> > > + if (!aspi)
> > > + return -ENOMEM;
> > > +
> > > + dev_set_drvdata(dev, aspi);
> > > +
> > > + aspi->dev = dev;
> > > +
> > > + aspi->base = devm_ioremap_resource(dev, &dfl_dev->mmio_res);
> > > +
> > > + if (IS_ERR(aspi->base)) {
> > > + dev_err(dev, "%s get mem resource fail!\n", __func__);
> > > + return PTR_ERR(aspi->base);
> > > + }
> > > +
> > > + aspi->regmap = devm_regmap_init(dev, NULL, aspi, &indirect_regbus_cfg);
> > > + if (IS_ERR(aspi->regmap))
> > > + return PTR_ERR(aspi->regmap);
> > > +
> > > + aspi->altr_spi = create_cntrl(dev, aspi->base, &m10_bmc_info);
> > > +
> > > + if (IS_ERR(aspi->altr_spi)) {
> > > + dev_err(dev, "%s failed to create spi platform driver\n",
> > > + __func__);
> > > + return PTR_ERR(aspi->base);
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > +{
> > > + struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
> > > +
> > > + platform_device_unregister(aspi->altr_spi);
> > > +}
> > > +
> > > +#define FME_FEATURE_ID_MAX10_SPI 0xe
> > > +
> > > +static const struct dfl_device_id dfl_spi_altera_ids[] = {
> > > + { FME_ID, FME_FEATURE_ID_MAX10_SPI },
> > > + { }
> > > +};
> >
> > Maybe you can extend the Altera SPI driver with this part?
>
> The file, drivers/spi/spi-altera.c, already has platform MODULE_ related
> code. Wouldn't moving this code to that file produce conflicts?

I've seen other drivers support multiple busses, so it should be
possible, there might be nuances I'm missing in my brief look at this,
though.

I think one of them would be MODULE_DEVICE_TABLE(platform, ...)
and the other one MODULE_DEVICE_TABLE(dfl, ...)

See drivers/i2c/busses/i2c-designware-platdrv.c for an example (though
they might be guarding against what you describe with CONFIG_OF vs
CONFIG_ACPI)

If that doesn't work we could split it up into

altera-spi-plat.c and altera-spi-dfl.c and altera-spi-core.c
or something of that sort?

My point being, now that we have a bus, let's use it and develop drivers
according to the Linux device model where possible :)

Cheers,
Moritz

2021-04-08 07:33:09

by Wu, Hao

[permalink] [raw]
Subject: RE: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master

> > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> >
> > > Hi Matthew,
> > >
> > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> [email protected] wrote:
> > > > From: Matthew Gerlach <[email protected]>
> > > >
> > > > This patch adds DFL bus driver for the Altera SPI Master
> > > > controller. The SPI master is connected to an Intel SPI Slave to
> > > > Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
> > > >
> > > > Signed-off-by: Matthew Gerlach <[email protected]>
> > > > ---
> > > > drivers/fpga/Kconfig | 9 ++
> > > > drivers/fpga/Makefile | 1 +
> > > > drivers/fpga/dfl-spi-altera.c | 221
> ++++++++++++++++++++++++++++++++++++++++++
> > > > 3 files changed, 231 insertions(+)
> > > > create mode 100644 drivers/fpga/dfl-spi-altera.c
> > > >
> > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > index d591dd9..0a86994 100644
> > > > --- a/drivers/fpga/Kconfig
> > > > +++ b/drivers/fpga/Kconfig
> > > > @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
> > > > the card. It also instantiates the SPI master (spi-altera) for
> > > > the card's BMC (Board Management Controller).
> > > >
> > > > +config FPGA_DFL_SPI_ALTERA
> > > > + tristate "FPGA DFL Altera SPI Master Driver"
> > > > + depends on FPGA_DFL
> > > > + select REGMAP
> > > > + help
> > > > + This is a DFL bus driver for the Altera SPI master controller.
> > > > + The SPI master is connected to a SPI slave to Avalon Master
> > > > + bridge in a Intel MAX BMC.
> > > > +
> > > > config FPGA_DFL_PCI
> > > > tristate "FPGA DFL PCIe Device Driver"
> > > > depends on PCI && FPGA_DFL
> > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > > index 18dc9885..58a42ad 100644
> > > > --- a/drivers/fpga/Makefile
> > > > +++ b/drivers/fpga/Makefile
> > > > @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-
> afu-dma-region.o
> > > > dfl-afu-objs += dfl-afu-error.o
> > > >
> > > > obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-
> nios.o
> > > > +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA) += dfl-spi-altera.o
> > > >
> > > > # Drivers for FPGAs which implement DFL
> > > > obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o
> > > > diff --git a/drivers/fpga/dfl-spi-altera.c b/drivers/fpga/dfl-spi-altera.c
> > > > new file mode 100644
> > > > index 0000000..9bec25fd
> > > > --- /dev/null
> > > > +++ b/drivers/fpga/dfl-spi-altera.c
> > > > @@ -0,0 +1,221 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +/*
> > > > + * DFL bus driver for Altera SPI Master
> > > > + *
> > > > + * Copyright (C) 2020 Intel Corporation, Inc.
> > > > + *
> > > > + * Authors:
> > > > + * Matthew Gerlach <[email protected]>
> > > > + */
> > > > +
> > > > +#include <linux/types.h>
> > > > +#include <linux/kernel.h>
> > > > +#include <linux/module.h>
> > > > +#include <linux/stddef.h>
> > > > +#include <linux/errno.h>
> > > > +#include <linux/platform_device.h>
> > > > +#include <linux/io.h>
> > > > +#include <linux/bitfield.h>
> > > > +#include <linux/io-64-nonatomic-lo-hi.h>
> > > > +#include <linux/regmap.h>
> > > > +#include <linux/spi/spi.h>
> > > > +#include <linux/spi/altera.h>
> > > > +#include <linux/dfl.h>
> > > > +
> > > > +struct dfl_altera_spi {
> > > > + void __iomem *base;
> > > > + struct regmap *regmap;
> > > > + struct device *dev;
> > > > + struct platform_device *altr_spi;
> > > > +};
> > > > +
> > > > +#define SPI_CORE_PARAMETER 0x8
> > > > +#define SHIFT_MODE BIT_ULL(1)
> > > > +#define SHIFT_MODE_MSB 0
> > > > +#define SHIFT_MODE_LSB 1
> > > > +#define DATA_WIDTH GENMASK_ULL(7, 2)
> > > > +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> > > > +#define CLK_POLARITY BIT_ULL(14)
> > > > +#define CLK_PHASE BIT_ULL(15)
> > > > +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> > > > +#define SPI_CLK GENMASK_ULL(31, 22)
> > > > +#define SPI_INDIRECT_ACC_OFST 0x10
> > > > +
> > > > +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> > > > +#define INDIRECT_WR BIT_ULL(8)
> > > > +#define INDIRECT_RD BIT_ULL(9)
> > > > +#define INDIRECT_RD_DATA (SPI_INDIRECT_ACC_OFST+0x8)
> > > > +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> > > > +#define INDIRECT_DEBUG BIT_ULL(32)
> > > > +#define INDIRECT_WR_DATA (SPI_INDIRECT_ACC_OFST+0x10)
> > > > +#define INDIRECT_TIMEOUT 10000
> > > > +
> > > > +static int indirect_bus_reg_read(void *context, unsigned int reg,
> > > > + unsigned int *val)
> > > > +{
> > > > + struct dfl_altera_spi *aspi = context;
> > > > + void __iomem *base = aspi->base;
> > > > + int loops;
> > > > + u64 v;
> > > > +
> > > > + writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
> > > > +
> > > > + loops = 0;
> > > > + while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
> > > > + (loops++ < INDIRECT_TIMEOUT))
> > > > + cpu_relax();
> > > > +
> > > > + if (loops >= INDIRECT_TIMEOUT) {
> > > > + pr_err("%s timed out %d\n", __func__, loops);
> > > > + return -ETIME;
> > > > + }
> > > > +
> > > > + v = readq(base + INDIRECT_RD_DATA);
> > > > +
> > > > + *val = v & INDIRECT_DATA_MASK;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int indirect_bus_reg_write(void *context, unsigned int reg,
> > > > + unsigned int val)
> > > > +{
> > > > + struct dfl_altera_spi *aspi = context;
> > > > + void __iomem *base = aspi->base;
> > > > + int loops;
> > > > +
> > > > + writeq(val, base + INDIRECT_WR_DATA);
> > > > + writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
> > > > +
> > > > + loops = 0;
> > > > + while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
> > > > + (loops++ < INDIRECT_TIMEOUT))
> > > > + cpu_relax();
> > > > +
> > > > + if (loops >= INDIRECT_TIMEOUT) {
> > > > + pr_err("%s timed out %d\n", __func__, loops);
> > > > + return -ETIME;
> > > > + }
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static const struct regmap_config indirect_regbus_cfg = {
> > > > + .reg_bits = 32,
> > > > + .reg_stride = 4,
> > > > + .val_bits = 32,
> > > > + .fast_io = true,
> > > > +
> > > > + .reg_write = indirect_bus_reg_write,
> > > > + .reg_read = indirect_bus_reg_read,
> > > > +};
> > > > +
> > > > +static struct spi_board_info m10_bmc_info = {
> > > > + .modalias = "m10-d5005",
> > > > + .max_speed_hz = 12500000,
> > > > + .bus_num = 0,
> > > > + .chip_select = 0,
> > > > +};
> > > > +
> > > > +static struct platform_device *create_cntrl(struct device *dev,
> > > > + void __iomem *base,
> > > > + struct spi_board_info *m10_info)
> > > > +{
> > > > + struct altera_spi_platform_data pdata;
> > > > + struct platform_device_info pdevinfo;
> > > > + u64 v;
> > > > +
> > > > + v = readq(base + SPI_CORE_PARAMETER);
> > > > +
> > > > + memset(&pdata, 0, sizeof(pdata));
> > > > + pdata.mode_bits = SPI_CS_HIGH;
> > > > + if (FIELD_GET(CLK_POLARITY, v))
> > > > + pdata.mode_bits |= SPI_CPOL;
> > > > + if (FIELD_GET(CLK_PHASE, v))
> > > > + pdata.mode_bits |= SPI_CPHA;
> > > > +
> > > > + pdata.num_chipselect = FIELD_GET(NUM_CHIPSELECT, v);
> > > > + pdata.bits_per_word_mask =
> > > > + SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v));
> > > > +
> > > > + pdata.num_devices = 1;
> > > > + pdata.devices = m10_info;
> > > > +
> > > > + dev_dbg(dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__,
> > > > + pdata.num_chipselect, pdata.bits_per_word_mask,
> > > > + pdata.mode_bits);
> > > > +
> > > > + memset(&pdevinfo, 0, sizeof(pdevinfo));
> > > > +
> > > > + pdevinfo.name = "subdev_spi_altera";
> > > > + pdevinfo.id = PLATFORM_DEVID_AUTO;
> > > > + pdevinfo.parent = dev;
> > > > + pdevinfo.data = &pdata;
> > > > + pdevinfo.size_data = sizeof(pdata);
> > > > +
> > > > + return platform_device_register_full(&pdevinfo);
> > >
> > > Should this be a SPI driver? I think looking at the UIO case we had
> > > decided against this pattern?
> >
> > This driver is similar in function to drivers/fpga/dfl-n3000-nios.c which
> > uses this design pattern. Is it okay to keep this design pattern for
> > consistency?
> >
> >
> > >
> > > > +}
> > > > +static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
> > > > +{
> > > > + struct device *dev = &dfl_dev->dev;
> > > > + struct dfl_altera_spi *aspi;
> > > > +
> > > > + aspi = devm_kzalloc(dev, sizeof(*aspi), GFP_KERNEL);
> > > > +
> > > > + if (!aspi)
> > > > + return -ENOMEM;
> > > > +
> > > > + dev_set_drvdata(dev, aspi);
> > > > +
> > > > + aspi->dev = dev;
> > > > +
> > > > + aspi->base = devm_ioremap_resource(dev, &dfl_dev->mmio_res);
> > > > +
> > > > + if (IS_ERR(aspi->base)) {
> > > > + dev_err(dev, "%s get mem resource fail!\n", __func__);
> > > > + return PTR_ERR(aspi->base);
> > > > + }
> > > > +
> > > > + aspi->regmap = devm_regmap_init(dev, NULL, aspi,
> &indirect_regbus_cfg);
> > > > + if (IS_ERR(aspi->regmap))
> > > > + return PTR_ERR(aspi->regmap);
> > > > +
> > > > + aspi->altr_spi = create_cntrl(dev, aspi->base, &m10_bmc_info);
> > > > +
> > > > + if (IS_ERR(aspi->altr_spi)) {
> > > > + dev_err(dev, "%s failed to create spi platform driver\n",
> > > > + __func__);
> > > > + return PTR_ERR(aspi->base);
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > > +{
> > > > + struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
> > > > +
> > > > + platform_device_unregister(aspi->altr_spi);
> > > > +}
> > > > +
> > > > +#define FME_FEATURE_ID_MAX10_SPI 0xe
> > > > +
> > > > +static const struct dfl_device_id dfl_spi_altera_ids[] = {
> > > > + { FME_ID, FME_FEATURE_ID_MAX10_SPI },
> > > > + { }
> > > > +};
> > >
> > > Maybe you can extend the Altera SPI driver with this part?
> >
> > The file, drivers/spi/spi-altera.c, already has platform MODULE_ related
> > code. Wouldn't moving this code to that file produce conflicts?
>
> I've seen other drivers support multiple busses, so it should be
> possible, there might be nuances I'm missing in my brief look at this,
> though.
>
> I think one of them would be MODULE_DEVICE_TABLE(platform, ...)
> and the other one MODULE_DEVICE_TABLE(dfl, ...)
>
> See drivers/i2c/busses/i2c-designware-platdrv.c for an example (though
> they might be guarding against what you describe with CONFIG_OF vs
> CONFIG_ACPI)
>
> If that doesn't work we could split it up into
>
> altera-spi-plat.c and altera-spi-dfl.c and altera-spi-core.c
> or something of that sort?
>
> My point being, now that we have a bus, let's use it and develop drivers
> according to the Linux device model where possible :)

Agree. This does make sense from my side too. DFL core provides the mechanism
to enumerate different IPs on FPGA, but each function driver needs to go to
related subsystem for review. : )

I understand that for FPGA case, it may have some additional logics for specific
purposes based on common altera spi master IP, then additional code for
a specific product still can be put into altera-spi-xxxx.c or altera-spi-dfl-xxxx.c

Thanks
Hao

>
> Cheers,
> Moritz

2021-04-08 08:17:39

by Xu Yilun

[permalink] [raw]
Subject: Re: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master

On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > >
> > > > Hi Matthew,
> > > >
> > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > [email protected] wrote:
> > > > > From: Matthew Gerlach <[email protected]>
> > > > >
> > > > > This patch adds DFL bus driver for the Altera SPI Master
> > > > > controller. The SPI master is connected to an Intel SPI Slave to
> > > > > Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
> > > > >
> > > > > Signed-off-by: Matthew Gerlach <[email protected]>
> > > > > ---
> > > > > drivers/fpga/Kconfig | 9 ++
> > > > > drivers/fpga/Makefile | 1 +
> > > > > drivers/fpga/dfl-spi-altera.c | 221
> > ++++++++++++++++++++++++++++++++++++++++++
> > > > > 3 files changed, 231 insertions(+)
> > > > > create mode 100644 drivers/fpga/dfl-spi-altera.c
> > > > >
> > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > > index d591dd9..0a86994 100644
> > > > > --- a/drivers/fpga/Kconfig
> > > > > +++ b/drivers/fpga/Kconfig
> > > > > @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
> > > > > the card. It also instantiates the SPI master (spi-altera) for
> > > > > the card's BMC (Board Management Controller).
> > > > >
> > > > > +config FPGA_DFL_SPI_ALTERA
> > > > > +tristate "FPGA DFL Altera SPI Master Driver"
> > > > > +depends on FPGA_DFL
> > > > > +select REGMAP
> > > > > +help
> > > > > + This is a DFL bus driver for the Altera SPI master controller.
> > > > > + The SPI master is connected to a SPI slave to Avalon Master
> > > > > + bridge in a Intel MAX BMC.
> > > > > +
> > > > > config FPGA_DFL_PCI
> > > > > tristate "FPGA DFL PCIe Device Driver"
> > > > > depends on PCI && FPGA_DFL
> > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > > > index 18dc9885..58a42ad 100644
> > > > > --- a/drivers/fpga/Makefile
> > > > > +++ b/drivers/fpga/Makefile
> > > > > @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-
> > afu-dma-region.o
> > > > > dfl-afu-objs += dfl-afu-error.o
> > > > >
> > > > > obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000)+= dfl-n3000-
> > nios.o
> > > > > +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA)+= dfl-spi-altera.o
> > > > >
> > > > > # Drivers for FPGAs which implement DFL
> > > > > obj-$(CONFIG_FPGA_DFL_PCI)+= dfl-pci.o
> > > > > diff --git a/drivers/fpga/dfl-spi-altera.c b/drivers/fpga/dfl-spi-altera.c
> > > > > new file mode 100644
> > > > > index 0000000..9bec25fd
> > > > > --- /dev/null
> > > > > +++ b/drivers/fpga/dfl-spi-altera.c
> > > > > @@ -0,0 +1,221 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > +/*
> > > > > + * DFL bus driver for Altera SPI Master
> > > > > + *
> > > > > + * Copyright (C) 2020 Intel Corporation, Inc.
> > > > > + *
> > > > > + * Authors:
> > > > > + * Matthew Gerlach <[email protected]>
> > > > > + */
> > > > > +
> > > > > +#include <linux/types.h>
> > > > > +#include <linux/kernel.h>
> > > > > +#include <linux/module.h>
> > > > > +#include <linux/stddef.h>
> > > > > +#include <linux/errno.h>
> > > > > +#include <linux/platform_device.h>
> > > > > +#include <linux/io.h>
> > > > > +#include <linux/bitfield.h>
> > > > > +#include <linux/io-64-nonatomic-lo-hi.h>
> > > > > +#include <linux/regmap.h>
> > > > > +#include <linux/spi/spi.h>
> > > > > +#include <linux/spi/altera.h>
> > > > > +#include <linux/dfl.h>
> > > > > +
> > > > > +struct dfl_altera_spi {
> > > > > +void __iomem *base;
> > > > > +struct regmap *regmap;
> > > > > +struct device *dev;
> > > > > +struct platform_device *altr_spi;
> > > > > +};
> > > > > +
> > > > > +#define SPI_CORE_PARAMETER 0x8
> > > > > +#define SHIFT_MODE BIT_ULL(1)
> > > > > +#define SHIFT_MODE_MSB 0
> > > > > +#define SHIFT_MODE_LSB 1
> > > > > +#define DATA_WIDTH GENMASK_ULL(7, 2)
> > > > > +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> > > > > +#define CLK_POLARITY BIT_ULL(14)
> > > > > +#define CLK_PHASE BIT_ULL(15)
> > > > > +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> > > > > +#define SPI_CLK GENMASK_ULL(31, 22)
> > > > > +#define SPI_INDIRECT_ACC_OFST 0x10
> > > > > +
> > > > > +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> > > > > +#define INDIRECT_WR BIT_ULL(8)
> > > > > +#define INDIRECT_RD BIT_ULL(9)
> > > > > +#define INDIRECT_RD_DATA (SPI_INDIRECT_ACC_OFST+0x8)
> > > > > +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> > > > > +#define INDIRECT_DEBUG BIT_ULL(32)
> > > > > +#define INDIRECT_WR_DATA (SPI_INDIRECT_ACC_OFST+0x10)
> > > > > +#define INDIRECT_TIMEOUT 10000
> > > > > +
> > > > > +static int indirect_bus_reg_read(void *context, unsigned int reg,
> > > > > + unsigned int *val)
> > > > > +{
> > > > > +struct dfl_altera_spi *aspi = context;
> > > > > +void __iomem *base = aspi->base;
> > > > > +int loops;
> > > > > +u64 v;
> > > > > +
> > > > > +writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
> > > > > +
> > > > > +loops = 0;
> > > > > +while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
> > > > > + (loops++ < INDIRECT_TIMEOUT))
> > > > > +cpu_relax();
> > > > > +
> > > > > +if (loops >= INDIRECT_TIMEOUT) {
> > > > > +pr_err("%s timed out %d\n", __func__, loops);
> > > > > +return -ETIME;
> > > > > +}
> > > > > +
> > > > > +v = readq(base + INDIRECT_RD_DATA);
> > > > > +
> > > > > +*val = v & INDIRECT_DATA_MASK;
> > > > > +
> > > > > +return 0;
> > > > > +}
> > > > > +
> > > > > +static int indirect_bus_reg_write(void *context, unsigned int reg,
> > > > > + unsigned int val)
> > > > > +{
> > > > > +struct dfl_altera_spi *aspi = context;
> > > > > +void __iomem *base = aspi->base;
> > > > > +int loops;
> > > > > +
> > > > > +writeq(val, base + INDIRECT_WR_DATA);
> > > > > +writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
> > > > > +
> > > > > +loops = 0;
> > > > > +while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
> > > > > + (loops++ < INDIRECT_TIMEOUT))
> > > > > +cpu_relax();
> > > > > +
> > > > > +if (loops >= INDIRECT_TIMEOUT) {
> > > > > +pr_err("%s timed out %d\n", __func__, loops);
> > > > > +return -ETIME;
> > > > > +}
> > > > > +return 0;
> > > > > +}
> > > > > +
> > > > > +static const struct regmap_config indirect_regbus_cfg = {
> > > > > +.reg_bits = 32,
> > > > > +.reg_stride = 4,
> > > > > +.val_bits = 32,
> > > > > +.fast_io = true,
> > > > > +
> > > > > +.reg_write = indirect_bus_reg_write,
> > > > > +.reg_read = indirect_bus_reg_read,
> > > > > +};
> > > > > +
> > > > > +static struct spi_board_info m10_bmc_info = {
> > > > > +.modalias = "m10-d5005",
> > > > > +.max_speed_hz = 12500000,
> > > > > +.bus_num = 0,
> > > > > +.chip_select = 0,
> > > > > +};
> > > > > +
> > > > > +static struct platform_device *create_cntrl(struct device *dev,
> > > > > + void __iomem *base,
> > > > > + struct spi_board_info *m10_info)
> > > > > +{
> > > > > +struct altera_spi_platform_data pdata;
> > > > > +struct platform_device_info pdevinfo;
> > > > > +u64 v;
> > > > > +
> > > > > +v = readq(base + SPI_CORE_PARAMETER);
> > > > > +
> > > > > +memset(&pdata, 0, sizeof(pdata));
> > > > > +pdata.mode_bits = SPI_CS_HIGH;
> > > > > +if (FIELD_GET(CLK_POLARITY, v))
> > > > > +pdata.mode_bits |= SPI_CPOL;
> > > > > +if (FIELD_GET(CLK_PHASE, v))
> > > > > +pdata.mode_bits |= SPI_CPHA;
> > > > > +
> > > > > +pdata.num_chipselect = FIELD_GET(NUM_CHIPSELECT, v);
> > > > > +pdata.bits_per_word_mask =
> > > > > +SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v));
> > > > > +
> > > > > +pdata.num_devices = 1;
> > > > > +pdata.devices = m10_info;
> > > > > +
> > > > > +dev_dbg(dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__,
> > > > > +pdata.num_chipselect, pdata.bits_per_word_mask,
> > > > > +pdata.mode_bits);
> > > > > +
> > > > > +memset(&pdevinfo, 0, sizeof(pdevinfo));
> > > > > +
> > > > > +pdevinfo.name = "subdev_spi_altera";
> > > > > +pdevinfo.id = PLATFORM_DEVID_AUTO;
> > > > > +pdevinfo.parent = dev;
> > > > > +pdevinfo.data = &pdata;
> > > > > +pdevinfo.size_data = sizeof(pdata);
> > > > > +
> > > > > +return platform_device_register_full(&pdevinfo);
> > > >
> > > > Should this be a SPI driver? I think looking at the UIO case we had
> > > > decided against this pattern?
> > >
> > > This driver is similar in function to drivers/fpga/dfl-n3000-nios.c which
> > > uses this design pattern. Is it okay to keep this design pattern for
> > > consistency?
> > >
> > >
> > > >
> > > > > +}
> > > > > +static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
> > > > > +{
> > > > > +struct device *dev = &dfl_dev->dev;
> > > > > +struct dfl_altera_spi *aspi;
> > > > > +
> > > > > +aspi = devm_kzalloc(dev, sizeof(*aspi), GFP_KERNEL);
> > > > > +
> > > > > +if (!aspi)
> > > > > +return -ENOMEM;
> > > > > +
> > > > > +dev_set_drvdata(dev, aspi);
> > > > > +
> > > > > +aspi->dev = dev;
> > > > > +
> > > > > +aspi->base = devm_ioremap_resource(dev, &dfl_dev->mmio_res);
> > > > > +
> > > > > +if (IS_ERR(aspi->base)) {
> > > > > +dev_err(dev, "%s get mem resource fail!\n", __func__);
> > > > > +return PTR_ERR(aspi->base);
> > > > > +}
> > > > > +
> > > > > +aspi->regmap = devm_regmap_init(dev, NULL, aspi,
> > &indirect_regbus_cfg);
> > > > > +if (IS_ERR(aspi->regmap))
> > > > > +return PTR_ERR(aspi->regmap);
> > > > > +
> > > > > +aspi->altr_spi = create_cntrl(dev, aspi->base, &m10_bmc_info);
> > > > > +
> > > > > +if (IS_ERR(aspi->altr_spi)) {
> > > > > +dev_err(dev, "%s failed to create spi platform driver\n",
> > > > > +__func__);
> > > > > +return PTR_ERR(aspi->base);
> > > > > +}
> > > > > +
> > > > > +return 0;
> > > > > +}
> > > > > +
> > > > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > > > +{
> > > > > +struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
> > > > > +
> > > > > +platform_device_unregister(aspi->altr_spi);
> > > > > +}
> > > > > +
> > > > > +#define FME_FEATURE_ID_MAX10_SPI 0xe
> > > > > +
> > > > > +static const struct dfl_device_id dfl_spi_altera_ids[] = {
> > > > > +{ FME_ID, FME_FEATURE_ID_MAX10_SPI },
> > > > > +{ }
> > > > > +};
> > > >
> > > > Maybe you can extend the Altera SPI driver with this part?
> > >
> > > The file, drivers/spi/spi-altera.c, already has platform MODULE_ related
> > > code. Wouldn't moving this code to that file produce conflicts?
> >
> > I've seen other drivers support multiple busses, so it should be
> > possible, there might be nuances I'm missing in my brief look at this,
> > though.
> >
> > I think one of them would be MODULE_DEVICE_TABLE(platform, ...)
> > and the other one MODULE_DEVICE_TABLE(dfl, ...)
> >
> > See drivers/i2c/busses/i2c-designware-platdrv.c for an example (though
> > they might be guarding against what you describe with CONFIG_OF vs
> > CONFIG_ACPI)
> >
> > If that doesn't work we could split it up into
> >
> > altera-spi-plat.c and altera-spi-dfl.c and altera-spi-core.c
> > or something of that sort?
> >
> > My point being, now that we have a bus, let's use it and develop drivers
> > according to the Linux device model where possible :)
>
> Agree. This does make sense from my side too. DFL core provides the mechanism
> to enumerate different IPs on FPGA, but each function driver needs to go to
> related subsystem for review. : )
>
> I understand that for FPGA case, it may have some additional logics for specific
> purposes based on common altera spi master IP, then additional code for

I'm wondering if the additional logics are extensions for common spi-altera. Like the
SPI_CORE_PARAMETER register, it is not within the register space of
spi-altera,


| | +-------------+
|DFL|------| +--------+ |
|BUS| | |SPI CORE| |
| | | |PARAM | |
| | | +--------+ |
| | | |
| | | +--------+ | +-------+
| |Indirect| | |spi |
| |access +--+---|altera |
| |master | | +-------+
| +--------+ |
+-------------+
> a specific product still can be put into altera-spi-xxxx.c or altera-spi-dfl-xxxx.c

So is it proper we integrate this feature into spi-altera? Previously
we have merged the dfl-n3000-nios, its spi part is very similar as
this driver. The dfl-n3000-nios make the spi-altera as a sub device.
Could we borrow the idea, or could we just integrate this driver in
dfl-n3000-nios?

Thanks,
Yilun

>
> Thanks
> Hao
>
> >
> > Cheers,
> > Moritz

2021-04-08 09:22:30

by Wu, Hao

[permalink] [raw]
Subject: RE: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master

> On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > >
> > > > > Hi Matthew,
> > > > >
> > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > > [email protected] wrote:
> > > > > > From: Matthew Gerlach <[email protected]>
> > > > > >
> > > > > > This patch adds DFL bus driver for the Altera SPI Master
> > > > > > controller. The SPI master is connected to an Intel SPI Slave to
> > > > > > Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
> > > > > >
> > > > > > Signed-off-by: Matthew Gerlach <[email protected]>
> > > > > > ---
> > > > > > drivers/fpga/Kconfig | 9 ++
> > > > > > drivers/fpga/Makefile | 1 +
> > > > > > drivers/fpga/dfl-spi-altera.c | 221
> > > ++++++++++++++++++++++++++++++++++++++++++
> > > > > > 3 files changed, 231 insertions(+)
> > > > > > create mode 100644 drivers/fpga/dfl-spi-altera.c
> > > > > >
> > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > > > index d591dd9..0a86994 100644
> > > > > > --- a/drivers/fpga/Kconfig
> > > > > > +++ b/drivers/fpga/Kconfig
> > > > > > @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
> > > > > > the card. It also instantiates the SPI master (spi-altera) for
> > > > > > the card's BMC (Board Management Controller).
> > > > > >
> > > > > > +config FPGA_DFL_SPI_ALTERA
> > > > > > +tristate "FPGA DFL Altera SPI Master Driver"
> > > > > > +depends on FPGA_DFL
> > > > > > +select REGMAP
> > > > > > +help
> > > > > > + This is a DFL bus driver for the Altera SPI master controller.
> > > > > > + The SPI master is connected to a SPI slave to Avalon Master
> > > > > > + bridge in a Intel MAX BMC.
> > > > > > +
> > > > > > config FPGA_DFL_PCI
> > > > > > tristate "FPGA DFL PCIe Device Driver"
> > > > > > depends on PCI && FPGA_DFL
> > > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > > > > index 18dc9885..58a42ad 100644
> > > > > > --- a/drivers/fpga/Makefile
> > > > > > +++ b/drivers/fpga/Makefile
> > > > > > @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-
> > > afu-dma-region.o
> > > > > > dfl-afu-objs += dfl-afu-error.o
> > > > > >
> > > > > > obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000)+= dfl-n3000-
> > > nios.o
> > > > > > +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA)+= dfl-spi-altera.o
> > > > > >
> > > > > > # Drivers for FPGAs which implement DFL
> > > > > > obj-$(CONFIG_FPGA_DFL_PCI)+= dfl-pci.o
> > > > > > diff --git a/drivers/fpga/dfl-spi-altera.c b/drivers/fpga/dfl-spi-altera.c
> > > > > > new file mode 100644
> > > > > > index 0000000..9bec25fd
> > > > > > --- /dev/null
> > > > > > +++ b/drivers/fpga/dfl-spi-altera.c
> > > > > > @@ -0,0 +1,221 @@
> > > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > > +/*
> > > > > > + * DFL bus driver for Altera SPI Master
> > > > > > + *
> > > > > > + * Copyright (C) 2020 Intel Corporation, Inc.
> > > > > > + *
> > > > > > + * Authors:
> > > > > > + * Matthew Gerlach <[email protected]>
> > > > > > + */
> > > > > > +
> > > > > > +#include <linux/types.h>
> > > > > > +#include <linux/kernel.h>
> > > > > > +#include <linux/module.h>
> > > > > > +#include <linux/stddef.h>
> > > > > > +#include <linux/errno.h>
> > > > > > +#include <linux/platform_device.h>
> > > > > > +#include <linux/io.h>
> > > > > > +#include <linux/bitfield.h>
> > > > > > +#include <linux/io-64-nonatomic-lo-hi.h>
> > > > > > +#include <linux/regmap.h>
> > > > > > +#include <linux/spi/spi.h>
> > > > > > +#include <linux/spi/altera.h>
> > > > > > +#include <linux/dfl.h>
> > > > > > +
> > > > > > +struct dfl_altera_spi {
> > > > > > +void __iomem *base;
> > > > > > +struct regmap *regmap;
> > > > > > +struct device *dev;
> > > > > > +struct platform_device *altr_spi;
> > > > > > +};
> > > > > > +
> > > > > > +#define SPI_CORE_PARAMETER 0x8
> > > > > > +#define SHIFT_MODE BIT_ULL(1)
> > > > > > +#define SHIFT_MODE_MSB 0
> > > > > > +#define SHIFT_MODE_LSB 1
> > > > > > +#define DATA_WIDTH GENMASK_ULL(7, 2)
> > > > > > +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> > > > > > +#define CLK_POLARITY BIT_ULL(14)
> > > > > > +#define CLK_PHASE BIT_ULL(15)
> > > > > > +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> > > > > > +#define SPI_CLK GENMASK_ULL(31, 22)
> > > > > > +#define SPI_INDIRECT_ACC_OFST 0x10
> > > > > > +
> > > > > > +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> > > > > > +#define INDIRECT_WR BIT_ULL(8)
> > > > > > +#define INDIRECT_RD BIT_ULL(9)
> > > > > > +#define INDIRECT_RD_DATA (SPI_INDIRECT_ACC_OFST+0x8)
> > > > > > +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> > > > > > +#define INDIRECT_DEBUG BIT_ULL(32)
> > > > > > +#define INDIRECT_WR_DATA (SPI_INDIRECT_ACC_OFST+0x10)
> > > > > > +#define INDIRECT_TIMEOUT 10000
> > > > > > +
> > > > > > +static int indirect_bus_reg_read(void *context, unsigned int reg,
> > > > > > + unsigned int *val)
> > > > > > +{
> > > > > > +struct dfl_altera_spi *aspi = context;
> > > > > > +void __iomem *base = aspi->base;
> > > > > > +int loops;
> > > > > > +u64 v;
> > > > > > +
> > > > > > +writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
> > > > > > +
> > > > > > +loops = 0;
> > > > > > +while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
> > > > > > + (loops++ < INDIRECT_TIMEOUT))
> > > > > > +cpu_relax();
> > > > > > +
> > > > > > +if (loops >= INDIRECT_TIMEOUT) {
> > > > > > +pr_err("%s timed out %d\n", __func__, loops);
> > > > > > +return -ETIME;
> > > > > > +}
> > > > > > +
> > > > > > +v = readq(base + INDIRECT_RD_DATA);
> > > > > > +
> > > > > > +*val = v & INDIRECT_DATA_MASK;
> > > > > > +
> > > > > > +return 0;
> > > > > > +}
> > > > > > +
> > > > > > +static int indirect_bus_reg_write(void *context, unsigned int reg,
> > > > > > + unsigned int val)
> > > > > > +{
> > > > > > +struct dfl_altera_spi *aspi = context;
> > > > > > +void __iomem *base = aspi->base;
> > > > > > +int loops;
> > > > > > +
> > > > > > +writeq(val, base + INDIRECT_WR_DATA);
> > > > > > +writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
> > > > > > +
> > > > > > +loops = 0;
> > > > > > +while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
> > > > > > + (loops++ < INDIRECT_TIMEOUT))
> > > > > > +cpu_relax();
> > > > > > +
> > > > > > +if (loops >= INDIRECT_TIMEOUT) {
> > > > > > +pr_err("%s timed out %d\n", __func__, loops);
> > > > > > +return -ETIME;
> > > > > > +}
> > > > > > +return 0;
> > > > > > +}
> > > > > > +
> > > > > > +static const struct regmap_config indirect_regbus_cfg = {
> > > > > > +.reg_bits = 32,
> > > > > > +.reg_stride = 4,
> > > > > > +.val_bits = 32,
> > > > > > +.fast_io = true,
> > > > > > +
> > > > > > +.reg_write = indirect_bus_reg_write,
> > > > > > +.reg_read = indirect_bus_reg_read,
> > > > > > +};
> > > > > > +
> > > > > > +static struct spi_board_info m10_bmc_info = {
> > > > > > +.modalias = "m10-d5005",
> > > > > > +.max_speed_hz = 12500000,
> > > > > > +.bus_num = 0,
> > > > > > +.chip_select = 0,
> > > > > > +};
> > > > > > +
> > > > > > +static struct platform_device *create_cntrl(struct device *dev,
> > > > > > + void __iomem *base,
> > > > > > + struct spi_board_info *m10_info)
> > > > > > +{
> > > > > > +struct altera_spi_platform_data pdata;
> > > > > > +struct platform_device_info pdevinfo;
> > > > > > +u64 v;
> > > > > > +
> > > > > > +v = readq(base + SPI_CORE_PARAMETER);
> > > > > > +
> > > > > > +memset(&pdata, 0, sizeof(pdata));
> > > > > > +pdata.mode_bits = SPI_CS_HIGH;
> > > > > > +if (FIELD_GET(CLK_POLARITY, v))
> > > > > > +pdata.mode_bits |= SPI_CPOL;
> > > > > > +if (FIELD_GET(CLK_PHASE, v))
> > > > > > +pdata.mode_bits |= SPI_CPHA;
> > > > > > +
> > > > > > +pdata.num_chipselect = FIELD_GET(NUM_CHIPSELECT, v);
> > > > > > +pdata.bits_per_word_mask =
> > > > > > +SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v));
> > > > > > +
> > > > > > +pdata.num_devices = 1;
> > > > > > +pdata.devices = m10_info;
> > > > > > +
> > > > > > +dev_dbg(dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__,
> > > > > > +pdata.num_chipselect, pdata.bits_per_word_mask,
> > > > > > +pdata.mode_bits);
> > > > > > +
> > > > > > +memset(&pdevinfo, 0, sizeof(pdevinfo));
> > > > > > +
> > > > > > +pdevinfo.name = "subdev_spi_altera";
> > > > > > +pdevinfo.id = PLATFORM_DEVID_AUTO;
> > > > > > +pdevinfo.parent = dev;
> > > > > > +pdevinfo.data = &pdata;
> > > > > > +pdevinfo.size_data = sizeof(pdata);
> > > > > > +
> > > > > > +return platform_device_register_full(&pdevinfo);
> > > > >
> > > > > Should this be a SPI driver? I think looking at the UIO case we had
> > > > > decided against this pattern?
> > > >
> > > > This driver is similar in function to drivers/fpga/dfl-n3000-nios.c which
> > > > uses this design pattern. Is it okay to keep this design pattern for
> > > > consistency?
> > > >
> > > >
> > > > >
> > > > > > +}
> > > > > > +static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
> > > > > > +{
> > > > > > +struct device *dev = &dfl_dev->dev;
> > > > > > +struct dfl_altera_spi *aspi;
> > > > > > +
> > > > > > +aspi = devm_kzalloc(dev, sizeof(*aspi), GFP_KERNEL);
> > > > > > +
> > > > > > +if (!aspi)
> > > > > > +return -ENOMEM;
> > > > > > +
> > > > > > +dev_set_drvdata(dev, aspi);
> > > > > > +
> > > > > > +aspi->dev = dev;
> > > > > > +
> > > > > > +aspi->base = devm_ioremap_resource(dev, &dfl_dev->mmio_res);
> > > > > > +
> > > > > > +if (IS_ERR(aspi->base)) {
> > > > > > +dev_err(dev, "%s get mem resource fail!\n", __func__);
> > > > > > +return PTR_ERR(aspi->base);
> > > > > > +}
> > > > > > +
> > > > > > +aspi->regmap = devm_regmap_init(dev, NULL, aspi,
> > > &indirect_regbus_cfg);
> > > > > > +if (IS_ERR(aspi->regmap))
> > > > > > +return PTR_ERR(aspi->regmap);
> > > > > > +
> > > > > > +aspi->altr_spi = create_cntrl(dev, aspi->base, &m10_bmc_info);
> > > > > > +
> > > > > > +if (IS_ERR(aspi->altr_spi)) {
> > > > > > +dev_err(dev, "%s failed to create spi platform driver\n",
> > > > > > +__func__);
> > > > > > +return PTR_ERR(aspi->base);
> > > > > > +}
> > > > > > +
> > > > > > +return 0;
> > > > > > +}
> > > > > > +
> > > > > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > > > > +{
> > > > > > +struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
> > > > > > +
> > > > > > +platform_device_unregister(aspi->altr_spi);
> > > > > > +}
> > > > > > +
> > > > > > +#define FME_FEATURE_ID_MAX10_SPI 0xe
> > > > > > +
> > > > > > +static const struct dfl_device_id dfl_spi_altera_ids[] = {
> > > > > > +{ FME_ID, FME_FEATURE_ID_MAX10_SPI },
> > > > > > +{ }
> > > > > > +};
> > > > >
> > > > > Maybe you can extend the Altera SPI driver with this part?
> > > >
> > > > The file, drivers/spi/spi-altera.c, already has platform MODULE_ related
> > > > code. Wouldn't moving this code to that file produce conflicts?
> > >
> > > I've seen other drivers support multiple busses, so it should be
> > > possible, there might be nuances I'm missing in my brief look at this,
> > > though.
> > >
> > > I think one of them would be MODULE_DEVICE_TABLE(platform, ...)
> > > and the other one MODULE_DEVICE_TABLE(dfl, ...)
> > >
> > > See drivers/i2c/busses/i2c-designware-platdrv.c for an example (though
> > > they might be guarding against what you describe with CONFIG_OF vs
> > > CONFIG_ACPI)
> > >
> > > If that doesn't work we could split it up into
> > >
> > > altera-spi-plat.c and altera-spi-dfl.c and altera-spi-core.c
> > > or something of that sort?
> > >
> > > My point being, now that we have a bus, let's use it and develop drivers
> > > according to the Linux device model where possible :)
> >
> > Agree. This does make sense from my side too. DFL core provides the
> mechanism
> > to enumerate different IPs on FPGA, but each function driver needs to go to
> > related subsystem for review. : )
> >
> > I understand that for FPGA case, it may have some additional logics for specific
> > purposes based on common altera spi master IP, then additional code for
>
> I'm wondering if the additional logics are extensions for common spi-altera. Like
> the
> SPI_CORE_PARAMETER register, it is not within the register space of
> spi-altera,
>
>
> | | +-------------+
> |DFL|------| +--------+ |
> |BUS| | |SPI CORE| |
> | | | |PARAM | |
> | | | +--------+ |
> | | | |
> | | | +--------+ | +-------+
> | |Indirect| | |spi |
> | |access +--+---|altera |
> | |master | | +-------+
> | +--------+ |
> +-------------+
> > a specific product still can be put into altera-spi-xxxx.c or altera-spi-dfl-xxxx.c
>
> So is it proper we integrate this feature into spi-altera? Previously
> we have merged the dfl-n3000-nios, its spi part is very similar as
> this driver. The dfl-n3000-nios make the spi-altera as a sub device.
> Could we borrow the idea, or could we just integrate this driver in
> dfl-n3000-nios?

Looks like those are enhancements of the IP. They can be applied even
other buses are used, not only for DFL, like PCI device or platform device,
right? then why not put related code together with the original IP?

The reason I suggested that function drivers which use DFL bus, still need
to go to related subsystem, because we know DFL quite well but may
not be the experts for every subsystem (e.g. SPI), and every IPs (e.g.
Altera SPI Master). Altera SPI Master driver maintainer could give more
valuable suggestions on your question if this feature can be integrated
into spi-altera or not. : )

Hao

>
> Thanks,
> Yilun
>
> >
> > Thanks
> > Hao
> >
> > >
> > > Cheers,
> > > Moritz

2021-04-08 18:55:32

by Moritz Fischer

[permalink] [raw]
Subject: Re: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master

On Thu, Apr 08, 2021 at 09:20:19AM +0000, Wu, Hao wrote:
> > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > >
> > > > > > Hi Matthew,
> > > > > >
> > > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > > > [email protected] wrote:
> > > > > > > From: Matthew Gerlach <[email protected]>
> > > > > > >
> > > > > > > This patch adds DFL bus driver for the Altera SPI Master
> > > > > > > controller. The SPI master is connected to an Intel SPI Slave to
> > > > > > > Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
> > > > > > >
> > > > > > > Signed-off-by: Matthew Gerlach <[email protected]>
> > > > > > > ---
> > > > > > > drivers/fpga/Kconfig | 9 ++
> > > > > > > drivers/fpga/Makefile | 1 +
> > > > > > > drivers/fpga/dfl-spi-altera.c | 221
> > > > ++++++++++++++++++++++++++++++++++++++++++
> > > > > > > 3 files changed, 231 insertions(+)
> > > > > > > create mode 100644 drivers/fpga/dfl-spi-altera.c
> > > > > > >
> > > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > > > > index d591dd9..0a86994 100644
> > > > > > > --- a/drivers/fpga/Kconfig
> > > > > > > +++ b/drivers/fpga/Kconfig
> > > > > > > @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
> > > > > > > the card. It also instantiates the SPI master (spi-altera) for
> > > > > > > the card's BMC (Board Management Controller).
> > > > > > >
> > > > > > > +config FPGA_DFL_SPI_ALTERA
> > > > > > > +tristate "FPGA DFL Altera SPI Master Driver"
> > > > > > > +depends on FPGA_DFL
> > > > > > > +select REGMAP
> > > > > > > +help
> > > > > > > + This is a DFL bus driver for the Altera SPI master controller.
> > > > > > > + The SPI master is connected to a SPI slave to Avalon Master
> > > > > > > + bridge in a Intel MAX BMC.
> > > > > > > +
> > > > > > > config FPGA_DFL_PCI
> > > > > > > tristate "FPGA DFL PCIe Device Driver"
> > > > > > > depends on PCI && FPGA_DFL
> > > > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > > > > > index 18dc9885..58a42ad 100644
> > > > > > > --- a/drivers/fpga/Makefile
> > > > > > > +++ b/drivers/fpga/Makefile
> > > > > > > @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-
> > > > afu-dma-region.o
> > > > > > > dfl-afu-objs += dfl-afu-error.o
> > > > > > >
> > > > > > > obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000)+= dfl-n3000-
> > > > nios.o
> > > > > > > +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA)+= dfl-spi-altera.o
> > > > > > >
> > > > > > > # Drivers for FPGAs which implement DFL
> > > > > > > obj-$(CONFIG_FPGA_DFL_PCI)+= dfl-pci.o
> > > > > > > diff --git a/drivers/fpga/dfl-spi-altera.c b/drivers/fpga/dfl-spi-altera.c
> > > > > > > new file mode 100644
> > > > > > > index 0000000..9bec25fd
> > > > > > > --- /dev/null
> > > > > > > +++ b/drivers/fpga/dfl-spi-altera.c
> > > > > > > @@ -0,0 +1,221 @@
> > > > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > > > +/*
> > > > > > > + * DFL bus driver for Altera SPI Master
> > > > > > > + *
> > > > > > > + * Copyright (C) 2020 Intel Corporation, Inc.
> > > > > > > + *
> > > > > > > + * Authors:
> > > > > > > + * Matthew Gerlach <[email protected]>
> > > > > > > + */
> > > > > > > +
> > > > > > > +#include <linux/types.h>
> > > > > > > +#include <linux/kernel.h>
> > > > > > > +#include <linux/module.h>
> > > > > > > +#include <linux/stddef.h>
> > > > > > > +#include <linux/errno.h>
> > > > > > > +#include <linux/platform_device.h>
> > > > > > > +#include <linux/io.h>
> > > > > > > +#include <linux/bitfield.h>
> > > > > > > +#include <linux/io-64-nonatomic-lo-hi.h>
> > > > > > > +#include <linux/regmap.h>
> > > > > > > +#include <linux/spi/spi.h>
> > > > > > > +#include <linux/spi/altera.h>
> > > > > > > +#include <linux/dfl.h>
> > > > > > > +
> > > > > > > +struct dfl_altera_spi {
> > > > > > > +void __iomem *base;
> > > > > > > +struct regmap *regmap;
> > > > > > > +struct device *dev;
> > > > > > > +struct platform_device *altr_spi;
> > > > > > > +};
> > > > > > > +
> > > > > > > +#define SPI_CORE_PARAMETER 0x8
> > > > > > > +#define SHIFT_MODE BIT_ULL(1)
> > > > > > > +#define SHIFT_MODE_MSB 0
> > > > > > > +#define SHIFT_MODE_LSB 1
> > > > > > > +#define DATA_WIDTH GENMASK_ULL(7, 2)
> > > > > > > +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> > > > > > > +#define CLK_POLARITY BIT_ULL(14)
> > > > > > > +#define CLK_PHASE BIT_ULL(15)
> > > > > > > +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> > > > > > > +#define SPI_CLK GENMASK_ULL(31, 22)
> > > > > > > +#define SPI_INDIRECT_ACC_OFST 0x10
> > > > > > > +
> > > > > > > +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> > > > > > > +#define INDIRECT_WR BIT_ULL(8)
> > > > > > > +#define INDIRECT_RD BIT_ULL(9)
> > > > > > > +#define INDIRECT_RD_DATA (SPI_INDIRECT_ACC_OFST+0x8)
> > > > > > > +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> > > > > > > +#define INDIRECT_DEBUG BIT_ULL(32)
> > > > > > > +#define INDIRECT_WR_DATA (SPI_INDIRECT_ACC_OFST+0x10)
> > > > > > > +#define INDIRECT_TIMEOUT 10000
> > > > > > > +
> > > > > > > +static int indirect_bus_reg_read(void *context, unsigned int reg,
> > > > > > > + unsigned int *val)
> > > > > > > +{
> > > > > > > +struct dfl_altera_spi *aspi = context;
> > > > > > > +void __iomem *base = aspi->base;
> > > > > > > +int loops;
> > > > > > > +u64 v;
> > > > > > > +
> > > > > > > +writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
> > > > > > > +
> > > > > > > +loops = 0;
> > > > > > > +while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
> > > > > > > + (loops++ < INDIRECT_TIMEOUT))
> > > > > > > +cpu_relax();
> > > > > > > +
> > > > > > > +if (loops >= INDIRECT_TIMEOUT) {
> > > > > > > +pr_err("%s timed out %d\n", __func__, loops);
> > > > > > > +return -ETIME;
> > > > > > > +}
> > > > > > > +
> > > > > > > +v = readq(base + INDIRECT_RD_DATA);
> > > > > > > +
> > > > > > > +*val = v & INDIRECT_DATA_MASK;
> > > > > > > +
> > > > > > > +return 0;
> > > > > > > +}
> > > > > > > +
> > > > > > > +static int indirect_bus_reg_write(void *context, unsigned int reg,
> > > > > > > + unsigned int val)
> > > > > > > +{
> > > > > > > +struct dfl_altera_spi *aspi = context;
> > > > > > > +void __iomem *base = aspi->base;
> > > > > > > +int loops;
> > > > > > > +
> > > > > > > +writeq(val, base + INDIRECT_WR_DATA);
> > > > > > > +writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
> > > > > > > +
> > > > > > > +loops = 0;
> > > > > > > +while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
> > > > > > > + (loops++ < INDIRECT_TIMEOUT))
> > > > > > > +cpu_relax();
> > > > > > > +
> > > > > > > +if (loops >= INDIRECT_TIMEOUT) {
> > > > > > > +pr_err("%s timed out %d\n", __func__, loops);
> > > > > > > +return -ETIME;
> > > > > > > +}
> > > > > > > +return 0;
> > > > > > > +}
> > > > > > > +
> > > > > > > +static const struct regmap_config indirect_regbus_cfg = {
> > > > > > > +.reg_bits = 32,
> > > > > > > +.reg_stride = 4,
> > > > > > > +.val_bits = 32,
> > > > > > > +.fast_io = true,
> > > > > > > +
> > > > > > > +.reg_write = indirect_bus_reg_write,
> > > > > > > +.reg_read = indirect_bus_reg_read,
> > > > > > > +};
> > > > > > > +
> > > > > > > +static struct spi_board_info m10_bmc_info = {
> > > > > > > +.modalias = "m10-d5005",
> > > > > > > +.max_speed_hz = 12500000,
> > > > > > > +.bus_num = 0,
> > > > > > > +.chip_select = 0,
> > > > > > > +};
> > > > > > > +
> > > > > > > +static struct platform_device *create_cntrl(struct device *dev,
> > > > > > > + void __iomem *base,
> > > > > > > + struct spi_board_info *m10_info)
> > > > > > > +{
> > > > > > > +struct altera_spi_platform_data pdata;
> > > > > > > +struct platform_device_info pdevinfo;
> > > > > > > +u64 v;
> > > > > > > +
> > > > > > > +v = readq(base + SPI_CORE_PARAMETER);
> > > > > > > +
> > > > > > > +memset(&pdata, 0, sizeof(pdata));
> > > > > > > +pdata.mode_bits = SPI_CS_HIGH;
> > > > > > > +if (FIELD_GET(CLK_POLARITY, v))
> > > > > > > +pdata.mode_bits |= SPI_CPOL;
> > > > > > > +if (FIELD_GET(CLK_PHASE, v))
> > > > > > > +pdata.mode_bits |= SPI_CPHA;
> > > > > > > +
> > > > > > > +pdata.num_chipselect = FIELD_GET(NUM_CHIPSELECT, v);
> > > > > > > +pdata.bits_per_word_mask =
> > > > > > > +SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v));
> > > > > > > +
> > > > > > > +pdata.num_devices = 1;
> > > > > > > +pdata.devices = m10_info;
> > > > > > > +
> > > > > > > +dev_dbg(dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__,
> > > > > > > +pdata.num_chipselect, pdata.bits_per_word_mask,
> > > > > > > +pdata.mode_bits);
> > > > > > > +
> > > > > > > +memset(&pdevinfo, 0, sizeof(pdevinfo));
> > > > > > > +
> > > > > > > +pdevinfo.name = "subdev_spi_altera";
> > > > > > > +pdevinfo.id = PLATFORM_DEVID_AUTO;
> > > > > > > +pdevinfo.parent = dev;
> > > > > > > +pdevinfo.data = &pdata;
> > > > > > > +pdevinfo.size_data = sizeof(pdata);
> > > > > > > +
> > > > > > > +return platform_device_register_full(&pdevinfo);
> > > > > >
> > > > > > Should this be a SPI driver? I think looking at the UIO case we had
> > > > > > decided against this pattern?
> > > > >
> > > > > This driver is similar in function to drivers/fpga/dfl-n3000-nios.c which
> > > > > uses this design pattern. Is it okay to keep this design pattern for
> > > > > consistency?
> > > > >
> > > > >
> > > > > >
> > > > > > > +}
> > > > > > > +static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
> > > > > > > +{
> > > > > > > +struct device *dev = &dfl_dev->dev;
> > > > > > > +struct dfl_altera_spi *aspi;
> > > > > > > +
> > > > > > > +aspi = devm_kzalloc(dev, sizeof(*aspi), GFP_KERNEL);
> > > > > > > +
> > > > > > > +if (!aspi)
> > > > > > > +return -ENOMEM;
> > > > > > > +
> > > > > > > +dev_set_drvdata(dev, aspi);
> > > > > > > +
> > > > > > > +aspi->dev = dev;
> > > > > > > +
> > > > > > > +aspi->base = devm_ioremap_resource(dev, &dfl_dev->mmio_res);
> > > > > > > +
> > > > > > > +if (IS_ERR(aspi->base)) {
> > > > > > > +dev_err(dev, "%s get mem resource fail!\n", __func__);
> > > > > > > +return PTR_ERR(aspi->base);
> > > > > > > +}
> > > > > > > +
> > > > > > > +aspi->regmap = devm_regmap_init(dev, NULL, aspi,
> > > > &indirect_regbus_cfg);
> > > > > > > +if (IS_ERR(aspi->regmap))
> > > > > > > +return PTR_ERR(aspi->regmap);
> > > > > > > +
> > > > > > > +aspi->altr_spi = create_cntrl(dev, aspi->base, &m10_bmc_info);
> > > > > > > +
> > > > > > > +if (IS_ERR(aspi->altr_spi)) {
> > > > > > > +dev_err(dev, "%s failed to create spi platform driver\n",
> > > > > > > +__func__);
> > > > > > > +return PTR_ERR(aspi->base);
> > > > > > > +}
> > > > > > > +
> > > > > > > +return 0;
> > > > > > > +}
> > > > > > > +
> > > > > > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > > > > > +{
> > > > > > > +struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
> > > > > > > +
> > > > > > > +platform_device_unregister(aspi->altr_spi);
> > > > > > > +}
> > > > > > > +
> > > > > > > +#define FME_FEATURE_ID_MAX10_SPI 0xe
> > > > > > > +
> > > > > > > +static const struct dfl_device_id dfl_spi_altera_ids[] = {
> > > > > > > +{ FME_ID, FME_FEATURE_ID_MAX10_SPI },
> > > > > > > +{ }
> > > > > > > +};
> > > > > >
> > > > > > Maybe you can extend the Altera SPI driver with this part?
> > > > >
> > > > > The file, drivers/spi/spi-altera.c, already has platform MODULE_ related
> > > > > code. Wouldn't moving this code to that file produce conflicts?
> > > >
> > > > I've seen other drivers support multiple busses, so it should be
> > > > possible, there might be nuances I'm missing in my brief look at this,
> > > > though.
> > > >
> > > > I think one of them would be MODULE_DEVICE_TABLE(platform, ...)
> > > > and the other one MODULE_DEVICE_TABLE(dfl, ...)
> > > >
> > > > See drivers/i2c/busses/i2c-designware-platdrv.c for an example (though
> > > > they might be guarding against what you describe with CONFIG_OF vs
> > > > CONFIG_ACPI)
> > > >
> > > > If that doesn't work we could split it up into
> > > >
> > > > altera-spi-plat.c and altera-spi-dfl.c and altera-spi-core.c
> > > > or something of that sort?
> > > >
> > > > My point being, now that we have a bus, let's use it and develop drivers
> > > > according to the Linux device model where possible :)
> > >
> > > Agree. This does make sense from my side too. DFL core provides the
> > mechanism
> > > to enumerate different IPs on FPGA, but each function driver needs to go to
> > > related subsystem for review. : )
> > >
> > > I understand that for FPGA case, it may have some additional logics for specific
> > > purposes based on common altera spi master IP, then additional code for
> >
> > I'm wondering if the additional logics are extensions for common spi-altera. Like
> > the
> > SPI_CORE_PARAMETER register, it is not within the register space of
> > spi-altera,
> >
> >
> > | | +-------------+
> > |DFL|------| +--------+ |
> > |BUS| | |SPI CORE| |
> > | | | |PARAM | |
> > | | | +--------+ |
> > | | | |
> > | | | +--------+ | +-------+
> > | |Indirect| | |spi |
> > | |access +--+---|altera |
> > | |master | | +-------+
> > | +--------+ |
> > +-------------+
> > > a specific product still can be put into altera-spi-xxxx.c or altera-spi-dfl-xxxx.c
> >
> > So is it proper we integrate this feature into spi-altera? Previously
> > we have merged the dfl-n3000-nios, its spi part is very similar as
> > this driver. The dfl-n3000-nios make the spi-altera as a sub device.
> > Could we borrow the idea, or could we just integrate this driver in
> > dfl-n3000-nios?
>
> Looks like those are enhancements of the IP. They can be applied even
> other buses are used, not only for DFL, like PCI device or platform device,
> right? then why not put related code together with the original IP?

Do you maybe need to extend struct dfl_device to have multiple mmio_res,
then?

Can DFL describe such a scenario?

That seems the logical step to support what's been drawn up there?

>
> The reason I suggested that function drivers which use DFL bus, still need
> to go to related subsystem, because we know DFL quite well but may
> not be the experts for every subsystem (e.g. SPI), and every IPs (e.g.
> Altera SPI Master). Altera SPI Master driver maintainer could give more
> valuable suggestions on your question if this feature can be integrated
> into spi-altera or not. : )
>
> Hao
>
> >
> > Thanks,
> > Yilun
> >
> > >
> > > Thanks
> > > Hao
> > >
> > > >
> > > > Cheers,
> > > > Moritz

Cheers,
Moritz

2021-04-09 01:43:33

by Xu Yilun

[permalink] [raw]
Subject: Re: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master

On Thu, Apr 08, 2021 at 05:20:19PM +0800, Wu, Hao wrote:
> > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > >
> > > > > > Hi Matthew,
> > > > > >
> > > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > > > [email protected] wrote:
> > > > > > > From: Matthew Gerlach <[email protected]>
> > > > > > >
> > > > > > > This patch adds DFL bus driver for the Altera SPI Master
> > > > > > > controller. The SPI master is connected to an Intel SPI Slave to
> > > > > > > Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
> > > > > > >
> > > > > > > Signed-off-by: Matthew Gerlach <[email protected]>
> > > > > > > ---
> > > > > > > drivers/fpga/Kconfig | 9 ++
> > > > > > > drivers/fpga/Makefile | 1 +
> > > > > > > drivers/fpga/dfl-spi-altera.c | 221
> > > > ++++++++++++++++++++++++++++++++++++++++++
> > > > > > > 3 files changed, 231 insertions(+)
> > > > > > > create mode 100644 drivers/fpga/dfl-spi-altera.c
> > > > > > >
> > > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > > > > index d591dd9..0a86994 100644
> > > > > > > --- a/drivers/fpga/Kconfig
> > > > > > > +++ b/drivers/fpga/Kconfig
> > > > > > > @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
> > > > > > > the card. It also instantiates the SPI master (spi-altera) for
> > > > > > > the card's BMC (Board Management Controller).
> > > > > > >
> > > > > > > +config FPGA_DFL_SPI_ALTERA
> > > > > > > +tristate "FPGA DFL Altera SPI Master Driver"
> > > > > > > +depends on FPGA_DFL
> > > > > > > +select REGMAP
> > > > > > > +help
> > > > > > > + This is a DFL bus driver for the Altera SPI master controller.
> > > > > > > + The SPI master is connected to a SPI slave to Avalon Master
> > > > > > > + bridge in a Intel MAX BMC.
> > > > > > > +
> > > > > > > config FPGA_DFL_PCI
> > > > > > > tristate "FPGA DFL PCIe Device Driver"
> > > > > > > depends on PCI && FPGA_DFL
> > > > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > > > > > index 18dc9885..58a42ad 100644
> > > > > > > --- a/drivers/fpga/Makefile
> > > > > > > +++ b/drivers/fpga/Makefile
> > > > > > > @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-
> > > > afu-dma-region.o
> > > > > > > dfl-afu-objs += dfl-afu-error.o
> > > > > > >
> > > > > > > obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000)+= dfl-n3000-
> > > > nios.o
> > > > > > > +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA)+= dfl-spi-altera.o
> > > > > > >
> > > > > > > # Drivers for FPGAs which implement DFL
> > > > > > > obj-$(CONFIG_FPGA_DFL_PCI)+= dfl-pci.o
> > > > > > > diff --git a/drivers/fpga/dfl-spi-altera.c b/drivers/fpga/dfl-spi-altera.c
> > > > > > > new file mode 100644
> > > > > > > index 0000000..9bec25fd
> > > > > > > --- /dev/null
> > > > > > > +++ b/drivers/fpga/dfl-spi-altera.c
> > > > > > > @@ -0,0 +1,221 @@
> > > > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > > > +/*
> > > > > > > + * DFL bus driver for Altera SPI Master
> > > > > > > + *
> > > > > > > + * Copyright (C) 2020 Intel Corporation, Inc.
> > > > > > > + *
> > > > > > > + * Authors:
> > > > > > > + * Matthew Gerlach <[email protected]>
> > > > > > > + */
> > > > > > > +
> > > > > > > +#include <linux/types.h>
> > > > > > > +#include <linux/kernel.h>
> > > > > > > +#include <linux/module.h>
> > > > > > > +#include <linux/stddef.h>
> > > > > > > +#include <linux/errno.h>
> > > > > > > +#include <linux/platform_device.h>
> > > > > > > +#include <linux/io.h>
> > > > > > > +#include <linux/bitfield.h>
> > > > > > > +#include <linux/io-64-nonatomic-lo-hi.h>
> > > > > > > +#include <linux/regmap.h>
> > > > > > > +#include <linux/spi/spi.h>
> > > > > > > +#include <linux/spi/altera.h>
> > > > > > > +#include <linux/dfl.h>
> > > > > > > +
> > > > > > > +struct dfl_altera_spi {
> > > > > > > +void __iomem *base;
> > > > > > > +struct regmap *regmap;
> > > > > > > +struct device *dev;
> > > > > > > +struct platform_device *altr_spi;
> > > > > > > +};
> > > > > > > +
> > > > > > > +#define SPI_CORE_PARAMETER 0x8
> > > > > > > +#define SHIFT_MODE BIT_ULL(1)
> > > > > > > +#define SHIFT_MODE_MSB 0
> > > > > > > +#define SHIFT_MODE_LSB 1
> > > > > > > +#define DATA_WIDTH GENMASK_ULL(7, 2)
> > > > > > > +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> > > > > > > +#define CLK_POLARITY BIT_ULL(14)
> > > > > > > +#define CLK_PHASE BIT_ULL(15)
> > > > > > > +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> > > > > > > +#define SPI_CLK GENMASK_ULL(31, 22)
> > > > > > > +#define SPI_INDIRECT_ACC_OFST 0x10
> > > > > > > +
> > > > > > > +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> > > > > > > +#define INDIRECT_WR BIT_ULL(8)
> > > > > > > +#define INDIRECT_RD BIT_ULL(9)
> > > > > > > +#define INDIRECT_RD_DATA (SPI_INDIRECT_ACC_OFST+0x8)
> > > > > > > +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> > > > > > > +#define INDIRECT_DEBUG BIT_ULL(32)
> > > > > > > +#define INDIRECT_WR_DATA (SPI_INDIRECT_ACC_OFST+0x10)
> > > > > > > +#define INDIRECT_TIMEOUT 10000
> > > > > > > +
> > > > > > > +static int indirect_bus_reg_read(void *context, unsigned int reg,
> > > > > > > + unsigned int *val)
> > > > > > > +{
> > > > > > > +struct dfl_altera_spi *aspi = context;
> > > > > > > +void __iomem *base = aspi->base;
> > > > > > > +int loops;
> > > > > > > +u64 v;
> > > > > > > +
> > > > > > > +writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
> > > > > > > +
> > > > > > > +loops = 0;
> > > > > > > +while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
> > > > > > > + (loops++ < INDIRECT_TIMEOUT))
> > > > > > > +cpu_relax();
> > > > > > > +
> > > > > > > +if (loops >= INDIRECT_TIMEOUT) {
> > > > > > > +pr_err("%s timed out %d\n", __func__, loops);
> > > > > > > +return -ETIME;
> > > > > > > +}
> > > > > > > +
> > > > > > > +v = readq(base + INDIRECT_RD_DATA);
> > > > > > > +
> > > > > > > +*val = v & INDIRECT_DATA_MASK;
> > > > > > > +
> > > > > > > +return 0;
> > > > > > > +}
> > > > > > > +
> > > > > > > +static int indirect_bus_reg_write(void *context, unsigned int reg,
> > > > > > > + unsigned int val)
> > > > > > > +{
> > > > > > > +struct dfl_altera_spi *aspi = context;
> > > > > > > +void __iomem *base = aspi->base;
> > > > > > > +int loops;
> > > > > > > +
> > > > > > > +writeq(val, base + INDIRECT_WR_DATA);
> > > > > > > +writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
> > > > > > > +
> > > > > > > +loops = 0;
> > > > > > > +while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
> > > > > > > + (loops++ < INDIRECT_TIMEOUT))
> > > > > > > +cpu_relax();
> > > > > > > +
> > > > > > > +if (loops >= INDIRECT_TIMEOUT) {
> > > > > > > +pr_err("%s timed out %d\n", __func__, loops);
> > > > > > > +return -ETIME;
> > > > > > > +}
> > > > > > > +return 0;
> > > > > > > +}
> > > > > > > +
> > > > > > > +static const struct regmap_config indirect_regbus_cfg = {
> > > > > > > +.reg_bits = 32,
> > > > > > > +.reg_stride = 4,
> > > > > > > +.val_bits = 32,
> > > > > > > +.fast_io = true,
> > > > > > > +
> > > > > > > +.reg_write = indirect_bus_reg_write,
> > > > > > > +.reg_read = indirect_bus_reg_read,
> > > > > > > +};
> > > > > > > +
> > > > > > > +static struct spi_board_info m10_bmc_info = {
> > > > > > > +.modalias = "m10-d5005",
> > > > > > > +.max_speed_hz = 12500000,
> > > > > > > +.bus_num = 0,
> > > > > > > +.chip_select = 0,
> > > > > > > +};
> > > > > > > +
> > > > > > > +static struct platform_device *create_cntrl(struct device *dev,
> > > > > > > + void __iomem *base,
> > > > > > > + struct spi_board_info *m10_info)
> > > > > > > +{
> > > > > > > +struct altera_spi_platform_data pdata;
> > > > > > > +struct platform_device_info pdevinfo;
> > > > > > > +u64 v;
> > > > > > > +
> > > > > > > +v = readq(base + SPI_CORE_PARAMETER);
> > > > > > > +
> > > > > > > +memset(&pdata, 0, sizeof(pdata));
> > > > > > > +pdata.mode_bits = SPI_CS_HIGH;
> > > > > > > +if (FIELD_GET(CLK_POLARITY, v))
> > > > > > > +pdata.mode_bits |= SPI_CPOL;
> > > > > > > +if (FIELD_GET(CLK_PHASE, v))
> > > > > > > +pdata.mode_bits |= SPI_CPHA;
> > > > > > > +
> > > > > > > +pdata.num_chipselect = FIELD_GET(NUM_CHIPSELECT, v);
> > > > > > > +pdata.bits_per_word_mask =
> > > > > > > +SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v));
> > > > > > > +
> > > > > > > +pdata.num_devices = 1;
> > > > > > > +pdata.devices = m10_info;
> > > > > > > +
> > > > > > > +dev_dbg(dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__,
> > > > > > > +pdata.num_chipselect, pdata.bits_per_word_mask,
> > > > > > > +pdata.mode_bits);
> > > > > > > +
> > > > > > > +memset(&pdevinfo, 0, sizeof(pdevinfo));
> > > > > > > +
> > > > > > > +pdevinfo.name = "subdev_spi_altera";
> > > > > > > +pdevinfo.id = PLATFORM_DEVID_AUTO;
> > > > > > > +pdevinfo.parent = dev;
> > > > > > > +pdevinfo.data = &pdata;
> > > > > > > +pdevinfo.size_data = sizeof(pdata);
> > > > > > > +
> > > > > > > +return platform_device_register_full(&pdevinfo);
> > > > > >
> > > > > > Should this be a SPI driver? I think looking at the UIO case we had
> > > > > > decided against this pattern?
> > > > >
> > > > > This driver is similar in function to drivers/fpga/dfl-n3000-nios.c which
> > > > > uses this design pattern. Is it okay to keep this design pattern for
> > > > > consistency?
> > > > >
> > > > >
> > > > > >
> > > > > > > +}
> > > > > > > +static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
> > > > > > > +{
> > > > > > > +struct device *dev = &dfl_dev->dev;
> > > > > > > +struct dfl_altera_spi *aspi;
> > > > > > > +
> > > > > > > +aspi = devm_kzalloc(dev, sizeof(*aspi), GFP_KERNEL);
> > > > > > > +
> > > > > > > +if (!aspi)
> > > > > > > +return -ENOMEM;
> > > > > > > +
> > > > > > > +dev_set_drvdata(dev, aspi);
> > > > > > > +
> > > > > > > +aspi->dev = dev;
> > > > > > > +
> > > > > > > +aspi->base = devm_ioremap_resource(dev, &dfl_dev->mmio_res);
> > > > > > > +
> > > > > > > +if (IS_ERR(aspi->base)) {
> > > > > > > +dev_err(dev, "%s get mem resource fail!\n", __func__);
> > > > > > > +return PTR_ERR(aspi->base);
> > > > > > > +}
> > > > > > > +
> > > > > > > +aspi->regmap = devm_regmap_init(dev, NULL, aspi,
> > > > &indirect_regbus_cfg);
> > > > > > > +if (IS_ERR(aspi->regmap))
> > > > > > > +return PTR_ERR(aspi->regmap);
> > > > > > > +
> > > > > > > +aspi->altr_spi = create_cntrl(dev, aspi->base, &m10_bmc_info);
> > > > > > > +
> > > > > > > +if (IS_ERR(aspi->altr_spi)) {
> > > > > > > +dev_err(dev, "%s failed to create spi platform driver\n",
> > > > > > > +__func__);
> > > > > > > +return PTR_ERR(aspi->base);
> > > > > > > +}
> > > > > > > +
> > > > > > > +return 0;
> > > > > > > +}
> > > > > > > +
> > > > > > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > > > > > +{
> > > > > > > +struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
> > > > > > > +
> > > > > > > +platform_device_unregister(aspi->altr_spi);
> > > > > > > +}
> > > > > > > +
> > > > > > > +#define FME_FEATURE_ID_MAX10_SPI 0xe
> > > > > > > +
> > > > > > > +static const struct dfl_device_id dfl_spi_altera_ids[] = {
> > > > > > > +{ FME_ID, FME_FEATURE_ID_MAX10_SPI },
> > > > > > > +{ }
> > > > > > > +};
> > > > > >
> > > > > > Maybe you can extend the Altera SPI driver with this part?
> > > > >
> > > > > The file, drivers/spi/spi-altera.c, already has platform MODULE_ related
> > > > > code. Wouldn't moving this code to that file produce conflicts?
> > > >
> > > > I've seen other drivers support multiple busses, so it should be
> > > > possible, there might be nuances I'm missing in my brief look at this,
> > > > though.
> > > >
> > > > I think one of them would be MODULE_DEVICE_TABLE(platform, ...)
> > > > and the other one MODULE_DEVICE_TABLE(dfl, ...)
> > > >
> > > > See drivers/i2c/busses/i2c-designware-platdrv.c for an example (though
> > > > they might be guarding against what you describe with CONFIG_OF vs
> > > > CONFIG_ACPI)
> > > >
> > > > If that doesn't work we could split it up into
> > > >
> > > > altera-spi-plat.c and altera-spi-dfl.c and altera-spi-core.c
> > > > or something of that sort?
> > > >
> > > > My point being, now that we have a bus, let's use it and develop drivers
> > > > according to the Linux device model where possible :)
> > >
> > > Agree. This does make sense from my side too. DFL core provides the
> > mechanism
> > > to enumerate different IPs on FPGA, but each function driver needs to go to
> > > related subsystem for review. : )
> > >
> > > I understand that for FPGA case, it may have some additional logics for specific
> > > purposes based on common altera spi master IP, then additional code for
> >
> > I'm wondering if the additional logics are extensions for common spi-altera. Like
> > the
> > SPI_CORE_PARAMETER register, it is not within the register space of
> > spi-altera,
> >
> >
> > | | +-------------+
> > |DFL|------| +--------+ |
> > |BUS| | |SPI CORE| |
> > | | | |PARAM | |
> > | | | +--------+ |
> > | | | |
> > | | | +--------+ | +-------+
> > | |Indirect| | |spi |
> > | |access +--+---|altera |
> > | |master | | +-------+
> > | +--------+ |
> > +-------------+
> > > a specific product still can be put into altera-spi-xxxx.c or altera-spi-dfl-xxxx.c
> >
> > So is it proper we integrate this feature into spi-altera? Previously
> > we have merged the dfl-n3000-nios, its spi part is very similar as
> > this driver. The dfl-n3000-nios make the spi-altera as a sub device.
> > Could we borrow the idea, or could we just integrate this driver in
> > dfl-n3000-nios?
>
> Looks like those are enhancements of the IP. They can be applied even

I don't think the extra registers are the enhancement of the IP. They
are not part of the IP because they are not within the IP's register
space. They are like some external way of describing the IP like
Devicetree or ACPI.

> other buses are used, not only for DFL, like PCI device or platform device,
> right? then why not put related code together with the original IP?

The code of devicetree or ACPI parsing are integrated in the IP drivers,
but for this case, it may not be proper for now, cause this style is not
formally introduced by any standard. IP specific parameters description
are not within the scope of DFL now.

>
> The reason I suggested that function drivers which use DFL bus, still need
> to go to related subsystem, because we know DFL quite well but may
> not be the experts for every subsystem (e.g. SPI), and every IPs (e.g.
> Altera SPI Master). Altera SPI Master driver maintainer could give more
> valuable suggestions on your question if this feature can be integrated
> into spi-altera or not. : )

I agree that we put drivers to their related subsystem. I'm just
wondering if drivers/spi is the proper domain for it. Anyway getting
some inputs from SPI maintainers is a good suggestion.

Thanks,
Yilun

>
> Hao
>
> >
> > Thanks,
> > Yilun
> >
> > >
> > > Thanks
> > > Hao
> > >
> > > >
> > > > Cheers,
> > > > Moritz

2021-04-09 01:57:34

by Xu Yilun

[permalink] [raw]
Subject: Re: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master

On Thu, Apr 08, 2021 at 11:53:06AM -0700, Moritz Fischer wrote:
> On Thu, Apr 08, 2021 at 09:20:19AM +0000, Wu, Hao wrote:
> > > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > > >
> > > > > > > Hi Matthew,
> > > > > > >
> > > > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > > > > [email protected] wrote:
> > > > > > > > From: Matthew Gerlach <[email protected]>
> > > > > > > >
> > > > > > > > This patch adds DFL bus driver for the Altera SPI Master
> > > > > > > > controller. The SPI master is connected to an Intel SPI Slave to
> > > > > > > > Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
> > > > > > > >
> > > > > > > > Signed-off-by: Matthew Gerlach <[email protected]>
> > > > > > > > ---
> > > > > > > > drivers/fpga/Kconfig | 9 ++
> > > > > > > > drivers/fpga/Makefile | 1 +
> > > > > > > > drivers/fpga/dfl-spi-altera.c | 221
> > > > > ++++++++++++++++++++++++++++++++++++++++++
> > > > > > > > 3 files changed, 231 insertions(+)
> > > > > > > > create mode 100644 drivers/fpga/dfl-spi-altera.c
> > > > > > > >
> > > > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > > > > > index d591dd9..0a86994 100644
> > > > > > > > --- a/drivers/fpga/Kconfig
> > > > > > > > +++ b/drivers/fpga/Kconfig
> > > > > > > > @@ -210,6 +210,15 @@ config FPGA_DFL_NIOS_INTEL_PAC_N3000
> > > > > > > > the card. It also instantiates the SPI master (spi-altera) for
> > > > > > > > the card's BMC (Board Management Controller).
> > > > > > > >
> > > > > > > > +config FPGA_DFL_SPI_ALTERA
> > > > > > > > +tristate "FPGA DFL Altera SPI Master Driver"
> > > > > > > > +depends on FPGA_DFL
> > > > > > > > +select REGMAP
> > > > > > > > +help
> > > > > > > > + This is a DFL bus driver for the Altera SPI master controller.
> > > > > > > > + The SPI master is connected to a SPI slave to Avalon Master
> > > > > > > > + bridge in a Intel MAX BMC.
> > > > > > > > +
> > > > > > > > config FPGA_DFL_PCI
> > > > > > > > tristate "FPGA DFL PCIe Device Driver"
> > > > > > > > depends on PCI && FPGA_DFL
> > > > > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > > > > > > index 18dc9885..58a42ad 100644
> > > > > > > > --- a/drivers/fpga/Makefile
> > > > > > > > +++ b/drivers/fpga/Makefile
> > > > > > > > @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-
> > > > > afu-dma-region.o
> > > > > > > > dfl-afu-objs += dfl-afu-error.o
> > > > > > > >
> > > > > > > > obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000)+= dfl-n3000-
> > > > > nios.o
> > > > > > > > +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA)+= dfl-spi-altera.o
> > > > > > > >
> > > > > > > > # Drivers for FPGAs which implement DFL
> > > > > > > > obj-$(CONFIG_FPGA_DFL_PCI)+= dfl-pci.o
> > > > > > > > diff --git a/drivers/fpga/dfl-spi-altera.c b/drivers/fpga/dfl-spi-altera.c
> > > > > > > > new file mode 100644
> > > > > > > > index 0000000..9bec25fd
> > > > > > > > --- /dev/null
> > > > > > > > +++ b/drivers/fpga/dfl-spi-altera.c
> > > > > > > > @@ -0,0 +1,221 @@
> > > > > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > > > > +/*
> > > > > > > > + * DFL bus driver for Altera SPI Master
> > > > > > > > + *
> > > > > > > > + * Copyright (C) 2020 Intel Corporation, Inc.
> > > > > > > > + *
> > > > > > > > + * Authors:
> > > > > > > > + * Matthew Gerlach <[email protected]>
> > > > > > > > + */
> > > > > > > > +
> > > > > > > > +#include <linux/types.h>
> > > > > > > > +#include <linux/kernel.h>
> > > > > > > > +#include <linux/module.h>
> > > > > > > > +#include <linux/stddef.h>
> > > > > > > > +#include <linux/errno.h>
> > > > > > > > +#include <linux/platform_device.h>
> > > > > > > > +#include <linux/io.h>
> > > > > > > > +#include <linux/bitfield.h>
> > > > > > > > +#include <linux/io-64-nonatomic-lo-hi.h>
> > > > > > > > +#include <linux/regmap.h>
> > > > > > > > +#include <linux/spi/spi.h>
> > > > > > > > +#include <linux/spi/altera.h>
> > > > > > > > +#include <linux/dfl.h>
> > > > > > > > +
> > > > > > > > +struct dfl_altera_spi {
> > > > > > > > +void __iomem *base;
> > > > > > > > +struct regmap *regmap;
> > > > > > > > +struct device *dev;
> > > > > > > > +struct platform_device *altr_spi;
> > > > > > > > +};
> > > > > > > > +
> > > > > > > > +#define SPI_CORE_PARAMETER 0x8
> > > > > > > > +#define SHIFT_MODE BIT_ULL(1)
> > > > > > > > +#define SHIFT_MODE_MSB 0
> > > > > > > > +#define SHIFT_MODE_LSB 1
> > > > > > > > +#define DATA_WIDTH GENMASK_ULL(7, 2)
> > > > > > > > +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> > > > > > > > +#define CLK_POLARITY BIT_ULL(14)
> > > > > > > > +#define CLK_PHASE BIT_ULL(15)
> > > > > > > > +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> > > > > > > > +#define SPI_CLK GENMASK_ULL(31, 22)
> > > > > > > > +#define SPI_INDIRECT_ACC_OFST 0x10
> > > > > > > > +
> > > > > > > > +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> > > > > > > > +#define INDIRECT_WR BIT_ULL(8)
> > > > > > > > +#define INDIRECT_RD BIT_ULL(9)
> > > > > > > > +#define INDIRECT_RD_DATA (SPI_INDIRECT_ACC_OFST+0x8)
> > > > > > > > +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> > > > > > > > +#define INDIRECT_DEBUG BIT_ULL(32)
> > > > > > > > +#define INDIRECT_WR_DATA (SPI_INDIRECT_ACC_OFST+0x10)
> > > > > > > > +#define INDIRECT_TIMEOUT 10000
> > > > > > > > +
> > > > > > > > +static int indirect_bus_reg_read(void *context, unsigned int reg,
> > > > > > > > + unsigned int *val)
> > > > > > > > +{
> > > > > > > > +struct dfl_altera_spi *aspi = context;
> > > > > > > > +void __iomem *base = aspi->base;
> > > > > > > > +int loops;
> > > > > > > > +u64 v;
> > > > > > > > +
> > > > > > > > +writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
> > > > > > > > +
> > > > > > > > +loops = 0;
> > > > > > > > +while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
> > > > > > > > + (loops++ < INDIRECT_TIMEOUT))
> > > > > > > > +cpu_relax();
> > > > > > > > +
> > > > > > > > +if (loops >= INDIRECT_TIMEOUT) {
> > > > > > > > +pr_err("%s timed out %d\n", __func__, loops);
> > > > > > > > +return -ETIME;
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +v = readq(base + INDIRECT_RD_DATA);
> > > > > > > > +
> > > > > > > > +*val = v & INDIRECT_DATA_MASK;
> > > > > > > > +
> > > > > > > > +return 0;
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +static int indirect_bus_reg_write(void *context, unsigned int reg,
> > > > > > > > + unsigned int val)
> > > > > > > > +{
> > > > > > > > +struct dfl_altera_spi *aspi = context;
> > > > > > > > +void __iomem *base = aspi->base;
> > > > > > > > +int loops;
> > > > > > > > +
> > > > > > > > +writeq(val, base + INDIRECT_WR_DATA);
> > > > > > > > +writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
> > > > > > > > +
> > > > > > > > +loops = 0;
> > > > > > > > +while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
> > > > > > > > + (loops++ < INDIRECT_TIMEOUT))
> > > > > > > > +cpu_relax();
> > > > > > > > +
> > > > > > > > +if (loops >= INDIRECT_TIMEOUT) {
> > > > > > > > +pr_err("%s timed out %d\n", __func__, loops);
> > > > > > > > +return -ETIME;
> > > > > > > > +}
> > > > > > > > +return 0;
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +static const struct regmap_config indirect_regbus_cfg = {
> > > > > > > > +.reg_bits = 32,
> > > > > > > > +.reg_stride = 4,
> > > > > > > > +.val_bits = 32,
> > > > > > > > +.fast_io = true,
> > > > > > > > +
> > > > > > > > +.reg_write = indirect_bus_reg_write,
> > > > > > > > +.reg_read = indirect_bus_reg_read,
> > > > > > > > +};
> > > > > > > > +
> > > > > > > > +static struct spi_board_info m10_bmc_info = {
> > > > > > > > +.modalias = "m10-d5005",
> > > > > > > > +.max_speed_hz = 12500000,
> > > > > > > > +.bus_num = 0,
> > > > > > > > +.chip_select = 0,
> > > > > > > > +};
> > > > > > > > +
> > > > > > > > +static struct platform_device *create_cntrl(struct device *dev,
> > > > > > > > + void __iomem *base,
> > > > > > > > + struct spi_board_info *m10_info)
> > > > > > > > +{
> > > > > > > > +struct altera_spi_platform_data pdata;
> > > > > > > > +struct platform_device_info pdevinfo;
> > > > > > > > +u64 v;
> > > > > > > > +
> > > > > > > > +v = readq(base + SPI_CORE_PARAMETER);
> > > > > > > > +
> > > > > > > > +memset(&pdata, 0, sizeof(pdata));
> > > > > > > > +pdata.mode_bits = SPI_CS_HIGH;
> > > > > > > > +if (FIELD_GET(CLK_POLARITY, v))
> > > > > > > > +pdata.mode_bits |= SPI_CPOL;
> > > > > > > > +if (FIELD_GET(CLK_PHASE, v))
> > > > > > > > +pdata.mode_bits |= SPI_CPHA;
> > > > > > > > +
> > > > > > > > +pdata.num_chipselect = FIELD_GET(NUM_CHIPSELECT, v);
> > > > > > > > +pdata.bits_per_word_mask =
> > > > > > > > +SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v));
> > > > > > > > +
> > > > > > > > +pdata.num_devices = 1;
> > > > > > > > +pdata.devices = m10_info;
> > > > > > > > +
> > > > > > > > +dev_dbg(dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__,
> > > > > > > > +pdata.num_chipselect, pdata.bits_per_word_mask,
> > > > > > > > +pdata.mode_bits);
> > > > > > > > +
> > > > > > > > +memset(&pdevinfo, 0, sizeof(pdevinfo));
> > > > > > > > +
> > > > > > > > +pdevinfo.name = "subdev_spi_altera";
> > > > > > > > +pdevinfo.id = PLATFORM_DEVID_AUTO;
> > > > > > > > +pdevinfo.parent = dev;
> > > > > > > > +pdevinfo.data = &pdata;
> > > > > > > > +pdevinfo.size_data = sizeof(pdata);
> > > > > > > > +
> > > > > > > > +return platform_device_register_full(&pdevinfo);
> > > > > > >
> > > > > > > Should this be a SPI driver? I think looking at the UIO case we had
> > > > > > > decided against this pattern?
> > > > > >
> > > > > > This driver is similar in function to drivers/fpga/dfl-n3000-nios.c which
> > > > > > uses this design pattern. Is it okay to keep this design pattern for
> > > > > > consistency?
> > > > > >
> > > > > >
> > > > > > >
> > > > > > > > +}
> > > > > > > > +static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
> > > > > > > > +{
> > > > > > > > +struct device *dev = &dfl_dev->dev;
> > > > > > > > +struct dfl_altera_spi *aspi;
> > > > > > > > +
> > > > > > > > +aspi = devm_kzalloc(dev, sizeof(*aspi), GFP_KERNEL);
> > > > > > > > +
> > > > > > > > +if (!aspi)
> > > > > > > > +return -ENOMEM;
> > > > > > > > +
> > > > > > > > +dev_set_drvdata(dev, aspi);
> > > > > > > > +
> > > > > > > > +aspi->dev = dev;
> > > > > > > > +
> > > > > > > > +aspi->base = devm_ioremap_resource(dev, &dfl_dev->mmio_res);
> > > > > > > > +
> > > > > > > > +if (IS_ERR(aspi->base)) {
> > > > > > > > +dev_err(dev, "%s get mem resource fail!\n", __func__);
> > > > > > > > +return PTR_ERR(aspi->base);
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +aspi->regmap = devm_regmap_init(dev, NULL, aspi,
> > > > > &indirect_regbus_cfg);
> > > > > > > > +if (IS_ERR(aspi->regmap))
> > > > > > > > +return PTR_ERR(aspi->regmap);
> > > > > > > > +
> > > > > > > > +aspi->altr_spi = create_cntrl(dev, aspi->base, &m10_bmc_info);
> > > > > > > > +
> > > > > > > > +if (IS_ERR(aspi->altr_spi)) {
> > > > > > > > +dev_err(dev, "%s failed to create spi platform driver\n",
> > > > > > > > +__func__);
> > > > > > > > +return PTR_ERR(aspi->base);
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +return 0;
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > > > > > > +{
> > > > > > > > +struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
> > > > > > > > +
> > > > > > > > +platform_device_unregister(aspi->altr_spi);
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +#define FME_FEATURE_ID_MAX10_SPI 0xe
> > > > > > > > +
> > > > > > > > +static const struct dfl_device_id dfl_spi_altera_ids[] = {
> > > > > > > > +{ FME_ID, FME_FEATURE_ID_MAX10_SPI },
> > > > > > > > +{ }
> > > > > > > > +};
> > > > > > >
> > > > > > > Maybe you can extend the Altera SPI driver with this part?
> > > > > >
> > > > > > The file, drivers/spi/spi-altera.c, already has platform MODULE_ related
> > > > > > code. Wouldn't moving this code to that file produce conflicts?
> > > > >
> > > > > I've seen other drivers support multiple busses, so it should be
> > > > > possible, there might be nuances I'm missing in my brief look at this,
> > > > > though.
> > > > >
> > > > > I think one of them would be MODULE_DEVICE_TABLE(platform, ...)
> > > > > and the other one MODULE_DEVICE_TABLE(dfl, ...)
> > > > >
> > > > > See drivers/i2c/busses/i2c-designware-platdrv.c for an example (though
> > > > > they might be guarding against what you describe with CONFIG_OF vs
> > > > > CONFIG_ACPI)
> > > > >
> > > > > If that doesn't work we could split it up into
> > > > >
> > > > > altera-spi-plat.c and altera-spi-dfl.c and altera-spi-core.c
> > > > > or something of that sort?
> > > > >
> > > > > My point being, now that we have a bus, let's use it and develop drivers
> > > > > according to the Linux device model where possible :)
> > > >
> > > > Agree. This does make sense from my side too. DFL core provides the
> > > mechanism
> > > > to enumerate different IPs on FPGA, but each function driver needs to go to
> > > > related subsystem for review. : )
> > > >
> > > > I understand that for FPGA case, it may have some additional logics for specific
> > > > purposes based on common altera spi master IP, then additional code for
> > >
> > > I'm wondering if the additional logics are extensions for common spi-altera. Like
> > > the
> > > SPI_CORE_PARAMETER register, it is not within the register space of
> > > spi-altera,
> > >
> > >
> > > | | +-------------+
> > > |DFL|------| +--------+ |
> > > |BUS| | |SPI CORE| |
> > > | | | |PARAM | |
> > > | | | +--------+ |
> > > | | | |
> > > | | | +--------+ | +-------+
> > > | |Indirect| | |spi |
> > > | |access +--+---|altera |
> > > | |master | | +-------+
> > > | +--------+ |
> > > +-------------+
> > > > a specific product still can be put into altera-spi-xxxx.c or altera-spi-dfl-xxxx.c
> > >
> > > So is it proper we integrate this feature into spi-altera? Previously
> > > we have merged the dfl-n3000-nios, its spi part is very similar as
> > > this driver. The dfl-n3000-nios make the spi-altera as a sub device.
> > > Could we borrow the idea, or could we just integrate this driver in
> > > dfl-n3000-nios?
> >
> > Looks like those are enhancements of the IP. They can be applied even
> > other buses are used, not only for DFL, like PCI device or platform device,
> > right? then why not put related code together with the original IP?
>
> Do you maybe need to extend struct dfl_device to have multiple mmio_res,
> then?
>
> Can DFL describe such a scenario?

The current version of DFL is not describing multiple mmio regions
within features, but yes we are on working on some extention to get
it supported.

>
> That seems the logical step to support what's been drawn up there?

Could you describe more about your idea? It's valuable discussion for
DFL design, not only for this case.

Thanks,
Yilun

>
> >
> > The reason I suggested that function drivers which use DFL bus, still need
> > to go to related subsystem, because we know DFL quite well but may
> > not be the experts for every subsystem (e.g. SPI), and every IPs (e.g.
> > Altera SPI Master). Altera SPI Master driver maintainer could give more
> > valuable suggestions on your question if this feature can be integrated
> > into spi-altera or not. : )
> >
> > Hao
> >
> > >
> > > Thanks,
> > > Yilun
> > >
> > > >
> > > > Thanks
> > > > Hao
> > > >
> > > > >
> > > > > Cheers,
> > > > > Moritz
>
> Cheers,
> Moritz

2021-04-09 01:58:22

by Wu, Hao

[permalink] [raw]
Subject: RE: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master

> On Thu, Apr 08, 2021 at 09:20:19AM +0000, Wu, Hao wrote:
> > > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > > >
> > > > > > > Hi Matthew,
> > > > > > >
> > > > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > > > > [email protected] wrote:
> > > > > > > > From: Matthew Gerlach <[email protected]>
> > > > > > > >
> > > > > > > > This patch adds DFL bus driver for the Altera SPI Master
> > > > > > > > controller. The SPI master is connected to an Intel SPI Slave to
> > > > > > > > Avalon Master Bridge, inside an Intel MAX10 BMC Chip.
> > > > > > > >
> > > > > > > > Signed-off-by: Matthew Gerlach <[email protected]>
> > > > > > > > ---
> > > > > > > > drivers/fpga/Kconfig | 9 ++
> > > > > > > > drivers/fpga/Makefile | 1 +
> > > > > > > > drivers/fpga/dfl-spi-altera.c | 221
> > > > > ++++++++++++++++++++++++++++++++++++++++++
> > > > > > > > 3 files changed, 231 insertions(+)
> > > > > > > > create mode 100644 drivers/fpga/dfl-spi-altera.c
> > > > > > > >
> > > > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> > > > > > > > index d591dd9..0a86994 100644
> > > > > > > > --- a/drivers/fpga/Kconfig
> > > > > > > > +++ b/drivers/fpga/Kconfig
> > > > > > > > @@ -210,6 +210,15 @@ config
> FPGA_DFL_NIOS_INTEL_PAC_N3000
> > > > > > > > the card. It also instantiates the SPI master (spi-altera) for
> > > > > > > > the card's BMC (Board Management Controller).
> > > > > > > >
> > > > > > > > +config FPGA_DFL_SPI_ALTERA
> > > > > > > > +tristate "FPGA DFL Altera SPI Master Driver"
> > > > > > > > +depends on FPGA_DFL
> > > > > > > > +select REGMAP
> > > > > > > > +help
> > > > > > > > + This is a DFL bus driver for the Altera SPI master controller.
> > > > > > > > + The SPI master is connected to a SPI slave to Avalon Master
> > > > > > > > + bridge in a Intel MAX BMC.
> > > > > > > > +
> > > > > > > > config FPGA_DFL_PCI
> > > > > > > > tristate "FPGA DFL PCIe Device Driver"
> > > > > > > > depends on PCI && FPGA_DFL
> > > > > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> > > > > > > > index 18dc9885..58a42ad 100644
> > > > > > > > --- a/drivers/fpga/Makefile
> > > > > > > > +++ b/drivers/fpga/Makefile
> > > > > > > > @@ -45,6 +45,7 @@ dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o
> dfl-
> > > > > afu-dma-region.o
> > > > > > > > dfl-afu-objs += dfl-afu-error.o
> > > > > > > >
> > > > > > > > obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000)+= dfl-n3000-
> > > > > nios.o
> > > > > > > > +obj-$(CONFIG_FPGA_DFL_SPI_ALTERA)+= dfl-spi-altera.o
> > > > > > > >
> > > > > > > > # Drivers for FPGAs which implement DFL
> > > > > > > > obj-$(CONFIG_FPGA_DFL_PCI)+= dfl-pci.o
> > > > > > > > diff --git a/drivers/fpga/dfl-spi-altera.c b/drivers/fpga/dfl-spi-
> altera.c
> > > > > > > > new file mode 100644
> > > > > > > > index 0000000..9bec25fd
> > > > > > > > --- /dev/null
> > > > > > > > +++ b/drivers/fpga/dfl-spi-altera.c
> > > > > > > > @@ -0,0 +1,221 @@
> > > > > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > > > > +/*
> > > > > > > > + * DFL bus driver for Altera SPI Master
> > > > > > > > + *
> > > > > > > > + * Copyright (C) 2020 Intel Corporation, Inc.
> > > > > > > > + *
> > > > > > > > + * Authors:
> > > > > > > > + * Matthew Gerlach <[email protected]>
> > > > > > > > + */
> > > > > > > > +
> > > > > > > > +#include <linux/types.h>
> > > > > > > > +#include <linux/kernel.h>
> > > > > > > > +#include <linux/module.h>
> > > > > > > > +#include <linux/stddef.h>
> > > > > > > > +#include <linux/errno.h>
> > > > > > > > +#include <linux/platform_device.h>
> > > > > > > > +#include <linux/io.h>
> > > > > > > > +#include <linux/bitfield.h>
> > > > > > > > +#include <linux/io-64-nonatomic-lo-hi.h>
> > > > > > > > +#include <linux/regmap.h>
> > > > > > > > +#include <linux/spi/spi.h>
> > > > > > > > +#include <linux/spi/altera.h>
> > > > > > > > +#include <linux/dfl.h>
> > > > > > > > +
> > > > > > > > +struct dfl_altera_spi {
> > > > > > > > +void __iomem *base;
> > > > > > > > +struct regmap *regmap;
> > > > > > > > +struct device *dev;
> > > > > > > > +struct platform_device *altr_spi;
> > > > > > > > +};
> > > > > > > > +
> > > > > > > > +#define SPI_CORE_PARAMETER 0x8
> > > > > > > > +#define SHIFT_MODE BIT_ULL(1)
> > > > > > > > +#define SHIFT_MODE_MSB 0
> > > > > > > > +#define SHIFT_MODE_LSB 1
> > > > > > > > +#define DATA_WIDTH GENMASK_ULL(7, 2)
> > > > > > > > +#define NUM_CHIPSELECT GENMASK_ULL(13, 8)
> > > > > > > > +#define CLK_POLARITY BIT_ULL(14)
> > > > > > > > +#define CLK_PHASE BIT_ULL(15)
> > > > > > > > +#define PERIPHERAL_ID GENMASK_ULL(47, 32)
> > > > > > > > +#define SPI_CLK GENMASK_ULL(31, 22)
> > > > > > > > +#define SPI_INDIRECT_ACC_OFST 0x10
> > > > > > > > +
> > > > > > > > +#define INDIRECT_ADDR (SPI_INDIRECT_ACC_OFST+0x0)
> > > > > > > > +#define INDIRECT_WR BIT_ULL(8)
> > > > > > > > +#define INDIRECT_RD BIT_ULL(9)
> > > > > > > > +#define INDIRECT_RD_DATA (SPI_INDIRECT_ACC_OFST+0x8)
> > > > > > > > +#define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
> > > > > > > > +#define INDIRECT_DEBUG BIT_ULL(32)
> > > > > > > > +#define INDIRECT_WR_DATA (SPI_INDIRECT_ACC_OFST+0x10)
> > > > > > > > +#define INDIRECT_TIMEOUT 10000
> > > > > > > > +
> > > > > > > > +static int indirect_bus_reg_read(void *context, unsigned int reg,
> > > > > > > > + unsigned int *val)
> > > > > > > > +{
> > > > > > > > +struct dfl_altera_spi *aspi = context;
> > > > > > > > +void __iomem *base = aspi->base;
> > > > > > > > +int loops;
> > > > > > > > +u64 v;
> > > > > > > > +
> > > > > > > > +writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR);
> > > > > > > > +
> > > > > > > > +loops = 0;
> > > > > > > > +while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) &&
> > > > > > > > + (loops++ < INDIRECT_TIMEOUT))
> > > > > > > > +cpu_relax();
> > > > > > > > +
> > > > > > > > +if (loops >= INDIRECT_TIMEOUT) {
> > > > > > > > +pr_err("%s timed out %d\n", __func__, loops);
> > > > > > > > +return -ETIME;
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +v = readq(base + INDIRECT_RD_DATA);
> > > > > > > > +
> > > > > > > > +*val = v & INDIRECT_DATA_MASK;
> > > > > > > > +
> > > > > > > > +return 0;
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +static int indirect_bus_reg_write(void *context, unsigned int reg,
> > > > > > > > + unsigned int val)
> > > > > > > > +{
> > > > > > > > +struct dfl_altera_spi *aspi = context;
> > > > > > > > +void __iomem *base = aspi->base;
> > > > > > > > +int loops;
> > > > > > > > +
> > > > > > > > +writeq(val, base + INDIRECT_WR_DATA);
> > > > > > > > +writeq((reg >> 2) | INDIRECT_WR, base + INDIRECT_ADDR);
> > > > > > > > +
> > > > > > > > +loops = 0;
> > > > > > > > +while ((readq(base + INDIRECT_ADDR) & INDIRECT_WR) &&
> > > > > > > > + (loops++ < INDIRECT_TIMEOUT))
> > > > > > > > +cpu_relax();
> > > > > > > > +
> > > > > > > > +if (loops >= INDIRECT_TIMEOUT) {
> > > > > > > > +pr_err("%s timed out %d\n", __func__, loops);
> > > > > > > > +return -ETIME;
> > > > > > > > +}
> > > > > > > > +return 0;
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +static const struct regmap_config indirect_regbus_cfg = {
> > > > > > > > +.reg_bits = 32,
> > > > > > > > +.reg_stride = 4,
> > > > > > > > +.val_bits = 32,
> > > > > > > > +.fast_io = true,
> > > > > > > > +
> > > > > > > > +.reg_write = indirect_bus_reg_write,
> > > > > > > > +.reg_read = indirect_bus_reg_read,
> > > > > > > > +};
> > > > > > > > +
> > > > > > > > +static struct spi_board_info m10_bmc_info = {
> > > > > > > > +.modalias = "m10-d5005",
> > > > > > > > +.max_speed_hz = 12500000,
> > > > > > > > +.bus_num = 0,
> > > > > > > > +.chip_select = 0,
> > > > > > > > +};
> > > > > > > > +
> > > > > > > > +static struct platform_device *create_cntrl(struct device *dev,
> > > > > > > > + void __iomem *base,
> > > > > > > > + struct spi_board_info *m10_info)
> > > > > > > > +{
> > > > > > > > +struct altera_spi_platform_data pdata;
> > > > > > > > +struct platform_device_info pdevinfo;
> > > > > > > > +u64 v;
> > > > > > > > +
> > > > > > > > +v = readq(base + SPI_CORE_PARAMETER);
> > > > > > > > +
> > > > > > > > +memset(&pdata, 0, sizeof(pdata));
> > > > > > > > +pdata.mode_bits = SPI_CS_HIGH;
> > > > > > > > +if (FIELD_GET(CLK_POLARITY, v))
> > > > > > > > +pdata.mode_bits |= SPI_CPOL;
> > > > > > > > +if (FIELD_GET(CLK_PHASE, v))
> > > > > > > > +pdata.mode_bits |= SPI_CPHA;
> > > > > > > > +
> > > > > > > > +pdata.num_chipselect = FIELD_GET(NUM_CHIPSELECT, v);
> > > > > > > > +pdata.bits_per_word_mask =
> > > > > > > > +SPI_BPW_RANGE_MASK(1, FIELD_GET(DATA_WIDTH, v));
> > > > > > > > +
> > > > > > > > +pdata.num_devices = 1;
> > > > > > > > +pdata.devices = m10_info;
> > > > > > > > +
> > > > > > > > +dev_dbg(dev, "%s cs %u bpm 0x%x mode 0x%x\n", __func__,
> > > > > > > > +pdata.num_chipselect, pdata.bits_per_word_mask,
> > > > > > > > +pdata.mode_bits);
> > > > > > > > +
> > > > > > > > +memset(&pdevinfo, 0, sizeof(pdevinfo));
> > > > > > > > +
> > > > > > > > +pdevinfo.name = "subdev_spi_altera";
> > > > > > > > +pdevinfo.id = PLATFORM_DEVID_AUTO;
> > > > > > > > +pdevinfo.parent = dev;
> > > > > > > > +pdevinfo.data = &pdata;
> > > > > > > > +pdevinfo.size_data = sizeof(pdata);
> > > > > > > > +
> > > > > > > > +return platform_device_register_full(&pdevinfo);
> > > > > > >
> > > > > > > Should this be a SPI driver? I think looking at the UIO case we had
> > > > > > > decided against this pattern?
> > > > > >
> > > > > > This driver is similar in function to drivers/fpga/dfl-n3000-nios.c which
> > > > > > uses this design pattern. Is it okay to keep this design pattern for
> > > > > > consistency?
> > > > > >
> > > > > >
> > > > > > >
> > > > > > > > +}
> > > > > > > > +static int dfl_spi_altera_probe(struct dfl_device *dfl_dev)
> > > > > > > > +{
> > > > > > > > +struct device *dev = &dfl_dev->dev;
> > > > > > > > +struct dfl_altera_spi *aspi;
> > > > > > > > +
> > > > > > > > +aspi = devm_kzalloc(dev, sizeof(*aspi), GFP_KERNEL);
> > > > > > > > +
> > > > > > > > +if (!aspi)
> > > > > > > > +return -ENOMEM;
> > > > > > > > +
> > > > > > > > +dev_set_drvdata(dev, aspi);
> > > > > > > > +
> > > > > > > > +aspi->dev = dev;
> > > > > > > > +
> > > > > > > > +aspi->base = devm_ioremap_resource(dev, &dfl_dev->mmio_res);
> > > > > > > > +
> > > > > > > > +if (IS_ERR(aspi->base)) {
> > > > > > > > +dev_err(dev, "%s get mem resource fail!\n", __func__);
> > > > > > > > +return PTR_ERR(aspi->base);
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +aspi->regmap = devm_regmap_init(dev, NULL, aspi,
> > > > > &indirect_regbus_cfg);
> > > > > > > > +if (IS_ERR(aspi->regmap))
> > > > > > > > +return PTR_ERR(aspi->regmap);
> > > > > > > > +
> > > > > > > > +aspi->altr_spi = create_cntrl(dev, aspi->base, &m10_bmc_info);
> > > > > > > > +
> > > > > > > > +if (IS_ERR(aspi->altr_spi)) {
> > > > > > > > +dev_err(dev, "%s failed to create spi platform driver\n",
> > > > > > > > +__func__);
> > > > > > > > +return PTR_ERR(aspi->base);
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +return 0;
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > > > > > > +{
> > > > > > > > +struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
> > > > > > > > +
> > > > > > > > +platform_device_unregister(aspi->altr_spi);
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +#define FME_FEATURE_ID_MAX10_SPI 0xe
> > > > > > > > +
> > > > > > > > +static const struct dfl_device_id dfl_spi_altera_ids[] = {
> > > > > > > > +{ FME_ID, FME_FEATURE_ID_MAX10_SPI },
> > > > > > > > +{ }
> > > > > > > > +};
> > > > > > >
> > > > > > > Maybe you can extend the Altera SPI driver with this part?
> > > > > >
> > > > > > The file, drivers/spi/spi-altera.c, already has platform MODULE_
> related
> > > > > > code. Wouldn't moving this code to that file produce conflicts?
> > > > >
> > > > > I've seen other drivers support multiple busses, so it should be
> > > > > possible, there might be nuances I'm missing in my brief look at this,
> > > > > though.
> > > > >
> > > > > I think one of them would be MODULE_DEVICE_TABLE(platform, ...)
> > > > > and the other one MODULE_DEVICE_TABLE(dfl, ...)
> > > > >
> > > > > See drivers/i2c/busses/i2c-designware-platdrv.c for an example (though
> > > > > they might be guarding against what you describe with CONFIG_OF vs
> > > > > CONFIG_ACPI)
> > > > >
> > > > > If that doesn't work we could split it up into
> > > > >
> > > > > altera-spi-plat.c and altera-spi-dfl.c and altera-spi-core.c
> > > > > or something of that sort?
> > > > >
> > > > > My point being, now that we have a bus, let's use it and develop drivers
> > > > > according to the Linux device model where possible :)
> > > >
> > > > Agree. This does make sense from my side too. DFL core provides the
> > > mechanism
> > > > to enumerate different IPs on FPGA, but each function driver needs to go
> to
> > > > related subsystem for review. : )
> > > >
> > > > I understand that for FPGA case, it may have some additional logics for
> specific
> > > > purposes based on common altera spi master IP, then additional code for
> > >
> > > I'm wondering if the additional logics are extensions for common spi-altera.
> Like
> > > the
> > > SPI_CORE_PARAMETER register, it is not within the register space of
> > > spi-altera,
> > >
> > >
> > > | | +-------------+
> > > |DFL|------| +--------+ |
> > > |BUS| | |SPI CORE| |
> > > | | | |PARAM | |
> > > | | | +--------+ |
> > > | | | |
> > > | | | +--------+ | +-------+
> > > | |Indirect| | |spi |
> > > | |access +--+---|altera |
> > > | |master | | +-------+
> > > | +--------+ |
> > > +-------------+
> > > > a specific product still can be put into altera-spi-xxxx.c or altera-spi-dfl-
> xxxx.c
> > >
> > > So is it proper we integrate this feature into spi-altera? Previously
> > > we have merged the dfl-n3000-nios, its spi part is very similar as
> > > this driver. The dfl-n3000-nios make the spi-altera as a sub device.
> > > Could we borrow the idea, or could we just integrate this driver in
> > > dfl-n3000-nios?
> >
> > Looks like those are enhancements of the IP. They can be applied even
> > other buses are used, not only for DFL, like PCI device or platform device,
> > right? then why not put related code together with the original IP?
>
> Do you maybe need to extend struct dfl_device to have multiple mmio_res,
> then?
>
> Can DFL describe such a scenario?
>
> That seems the logical step to support what's been drawn up there?

Current DFH version 0 only supports 1 mmio range, then everything has to
be put into the same mmio range but different offsets I think. DFH doesn't
care about what are inside this range, even it's possible to put multiple IPs
into one range ( DFH doesn't prevent this usage, but then mfd or something
similar need to be used in device driver on DFL bus).

It's should be fine to add multiple mmio ranges support for one DFH device
which requires a new version DFH, so that it can match the platform devices
which have multiple mmio resources or just like pci devices which have multiple
bars, but it is not something must to have for above case I think. : )

Thanks
Hao

>
> >
> > The reason I suggested that function drivers which use DFL bus, still need
> > to go to related subsystem, because we know DFL quite well but may
> > not be the experts for every subsystem (e.g. SPI), and every IPs (e.g.
> > Altera SPI Master). Altera SPI Master driver maintainer could give more
> > valuable suggestions on your question if this feature can be integrated
> > into spi-altera or not. : )
> >
> > Hao
> >
> > >
> > > Thanks,
> > > Yilun
> > >
> > > >
> > > > Thanks
> > > > Hao
> > > >
> > > > >
> > > > > Cheers,
> > > > > Moritz
>
> Cheers,
> Moritz

2021-04-09 04:05:15

by Wu, Hao

[permalink] [raw]
Subject: RE: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master

> > > > > > > > +
> > > > > > > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > > > > > > +{
> > > > > > > > +struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
> > > > > > > > +
> > > > > > > > +platform_device_unregister(aspi->altr_spi);
> > > > > > > > +}
> > > > > > > > +
> > > > > > > > +#define FME_FEATURE_ID_MAX10_SPI 0xe
> > > > > > > > +
> > > > > > > > +static const struct dfl_device_id dfl_spi_altera_ids[] = {
> > > > > > > > +{ FME_ID, FME_FEATURE_ID_MAX10_SPI },
> > > > > > > > +{ }
> > > > > > > > +};
> > > > > > >
> > > > > > > Maybe you can extend the Altera SPI driver with this part?
> > > > > >
> > > > > > The file, drivers/spi/spi-altera.c, already has platform MODULE_
> related
> > > > > > code. Wouldn't moving this code to that file produce conflicts?
> > > > >
> > > > > I've seen other drivers support multiple busses, so it should be
> > > > > possible, there might be nuances I'm missing in my brief look at this,
> > > > > though.
> > > > >
> > > > > I think one of them would be MODULE_DEVICE_TABLE(platform, ...)
> > > > > and the other one MODULE_DEVICE_TABLE(dfl, ...)
> > > > >
> > > > > See drivers/i2c/busses/i2c-designware-platdrv.c for an example (though
> > > > > they might be guarding against what you describe with CONFIG_OF vs
> > > > > CONFIG_ACPI)
> > > > >
> > > > > If that doesn't work we could split it up into
> > > > >
> > > > > altera-spi-plat.c and altera-spi-dfl.c and altera-spi-core.c
> > > > > or something of that sort?
> > > > >
> > > > > My point being, now that we have a bus, let's use it and develop drivers
> > > > > according to the Linux device model where possible :)
> > > >
> > > > Agree. This does make sense from my side too. DFL core provides the
> > > mechanism
> > > > to enumerate different IPs on FPGA, but each function driver needs to go
> to
> > > > related subsystem for review. : )
> > > >
> > > > I understand that for FPGA case, it may have some additional logics for
> specific
> > > > purposes based on common altera spi master IP, then additional code for
> > >
> > > I'm wondering if the additional logics are extensions for common spi-altera.
> Like
> > > the
> > > SPI_CORE_PARAMETER register, it is not within the register space of
> > > spi-altera,
> > >
> > >
> > > | | +-------------+
> > > |DFL|------| +--------+ |
> > > |BUS| | |SPI CORE| |
> > > | | | |PARAM | |
> > > | | | +--------+ |
> > > | | | |
> > > | | | +--------+ | +-------+
> > > | |Indirect| | |spi |
> > > | |access +--+---|altera |
> > > | |master | | +-------+
> > > | +--------+ |
> > > +-------------+
> > > > a specific product still can be put into altera-spi-xxxx.c or altera-spi-dfl-
> xxxx.c
> > >
> > > So is it proper we integrate this feature into spi-altera? Previously
> > > we have merged the dfl-n3000-nios, its spi part is very similar as
> > > this driver. The dfl-n3000-nios make the spi-altera as a sub device.
> > > Could we borrow the idea, or could we just integrate this driver in
> > > dfl-n3000-nios?
> >
> > Looks like those are enhancements of the IP. They can be applied even
>
> I don't think the extra registers are the enhancement of the IP. They
> are not part of the IP because they are not within the IP's register
> space. They are like some external way of describing the IP like
> Devicetree or ACPI.

Why adding new registers can't be consider as enhancement, those
changes serve the original IP and make it better, right? small mmio
footprint and parameter registers?

>
> > other buses are used, not only for DFL, like PCI device or platform device,
> > right? then why not put related code together with the original IP?
>
> The code of devicetree or ACPI parsing are integrated in the IP drivers,
> but for this case, it may not be proper for now, cause this style is not
> formally introduced by any standard. IP specific parameters description
> are not within the scope of DFL now.

Not sure if I get your point, but it's possible that we add some enhancements
to one IP then driver could be simplified and doesn't need devicetree any more.
For sure, it's IP specific thing, not the scope of DFL.

Then things become this: extension to IP to allow this IP to be used without
device tree, so that this IP can be used in DFL or PCI or other buses without
device tree?

Thanks
Hao

>
> >
> > The reason I suggested that function drivers which use DFL bus, still need
> > to go to related subsystem, because we know DFL quite well but may
> > not be the experts for every subsystem (e.g. SPI), and every IPs (e.g.
> > Altera SPI Master). Altera SPI Master driver maintainer could give more
> > valuable suggestions on your question if this feature can be integrated
> > into spi-altera or not. : )
>
> I agree that we put drivers to their related subsystem. I'm just
> wondering if drivers/spi is the proper domain for it. Anyway getting
> some inputs from SPI maintainers is a good suggestion.
>
> Thanks,
> Yilun
>
> >
> > Hao
> >
> > >
> > > Thanks,
> > > Yilun
> > >
> > > >
> > > > Thanks
> > > > Hao
> > > >
> > > > >
> > > > > Cheers,
> > > > > Moritz

2021-04-09 05:47:17

by Xu Yilun

[permalink] [raw]
Subject: Re: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master

On Fri, Apr 09, 2021 at 12:02:47PM +0800, Wu, Hao wrote:
> > > > > > > > > +
> > > > > > > > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > > > > > > > +{
> > > > > > > > > +struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
> > > > > > > > > +
> > > > > > > > > +platform_device_unregister(aspi->altr_spi);
> > > > > > > > > +}
> > > > > > > > > +
> > > > > > > > > +#define FME_FEATURE_ID_MAX10_SPI 0xe
> > > > > > > > > +
> > > > > > > > > +static const struct dfl_device_id dfl_spi_altera_ids[] = {
> > > > > > > > > +{ FME_ID, FME_FEATURE_ID_MAX10_SPI },
> > > > > > > > > +{ }
> > > > > > > > > +};
> > > > > > > >
> > > > > > > > Maybe you can extend the Altera SPI driver with this part?
> > > > > > >
> > > > > > > The file, drivers/spi/spi-altera.c, already has platform MODULE_
> > related
> > > > > > > code. Wouldn't moving this code to that file produce conflicts?
> > > > > >
> > > > > > I've seen other drivers support multiple busses, so it should be
> > > > > > possible, there might be nuances I'm missing in my brief look at this,
> > > > > > though.
> > > > > >
> > > > > > I think one of them would be MODULE_DEVICE_TABLE(platform, ...)
> > > > > > and the other one MODULE_DEVICE_TABLE(dfl, ...)
> > > > > >
> > > > > > See drivers/i2c/busses/i2c-designware-platdrv.c for an example (though
> > > > > > they might be guarding against what you describe with CONFIG_OF vs
> > > > > > CONFIG_ACPI)
> > > > > >
> > > > > > If that doesn't work we could split it up into
> > > > > >
> > > > > > altera-spi-plat.c and altera-spi-dfl.c and altera-spi-core.c
> > > > > > or something of that sort?
> > > > > >
> > > > > > My point being, now that we have a bus, let's use it and develop drivers
> > > > > > according to the Linux device model where possible :)
> > > > >
> > > > > Agree. This does make sense from my side too. DFL core provides the
> > > > mechanism
> > > > > to enumerate different IPs on FPGA, but each function driver needs to go
> > to
> > > > > related subsystem for review. : )
> > > > >
> > > > > I understand that for FPGA case, it may have some additional logics for
> > specific
> > > > > purposes based on common altera spi master IP, then additional code for
> > > >
> > > > I'm wondering if the additional logics are extensions for common spi-altera.
> > Like
> > > > the
> > > > SPI_CORE_PARAMETER register, it is not within the register space of
> > > > spi-altera,
> > > >
> > > >
> > > > | | +-------------+
> > > > |DFL|------| +--------+ |
> > > > |BUS| | |SPI CORE| |
> > > > | | | |PARAM | |
> > > > | | | +--------+ |
> > > > | | | |
> > > > | | | +--------+ | +-------+
> > > > | |Indirect| | |spi |
> > > > | |access +--+---|altera |
> > > > | |master | | +-------+
> > > > | +--------+ |
> > > > +-------------+
> > > > > a specific product still can be put into altera-spi-xxxx.c or altera-spi-dfl-
> > xxxx.c
> > > >
> > > > So is it proper we integrate this feature into spi-altera? Previously
> > > > we have merged the dfl-n3000-nios, its spi part is very similar as
> > > > this driver. The dfl-n3000-nios make the spi-altera as a sub device.
> > > > Could we borrow the idea, or could we just integrate this driver in
> > > > dfl-n3000-nios?
> > >
> > > Looks like those are enhancements of the IP. They can be applied even
> >
> > I don't think the extra registers are the enhancement of the IP. They
> > are not part of the IP because they are not within the IP's register
> > space. They are like some external way of describing the IP like
> > Devicetree or ACPI.
>
> Why adding new registers can't be consider as enhancement, those
> changes serve the original IP and make it better, right? small mmio
> footprint and parameter registers?
>
> >
> > > other buses are used, not only for DFL, like PCI device or platform device,
> > > right? then why not put related code together with the original IP?
> >
> > The code of devicetree or ACPI parsing are integrated in the IP drivers,
> > but for this case, it may not be proper for now, cause this style is not
> > formally introduced by any standard. IP specific parameters description
> > are not within the scope of DFL now.
>
> Not sure if I get your point, but it's possible that we add some enhancements
> to one IP then driver could be simplified and doesn't need devicetree any more.
> For sure, it's IP specific thing, not the scope of DFL.
>
> Then things become this: extension to IP to allow this IP to be used without
> device tree, so that this IP can be used in DFL or PCI or other buses without
> device tree?

It's good to extend an IP, but it needs a published SPEC and stable
register interfaces. For now, the spi-altera driver conforms to the
"SPI Core" chapter of the following spec:

https://www.intel.com/content/www/us/en/programmable/documentation/sfo1400787952932.html

There is no info about the core parameter register and this specific
indirect access bus. That's why I don't see these additional parts as
the enhancements to spi-altera. This DFL feature is like a wrapper for
the spi-altera sub device.

Thanks
Yilun

2021-04-09 07:21:26

by Wu, Hao

[permalink] [raw]
Subject: RE: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master

> On Fri, Apr 09, 2021 at 12:02:47PM +0800, Wu, Hao wrote:
> > > > > > > > > > +
> > > > > > > > > > +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
> > > > > > > > > > +{
> > > > > > > > > > +struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
> > > > > > > > > > +
> > > > > > > > > > +platform_device_unregister(aspi->altr_spi);
> > > > > > > > > > +}
> > > > > > > > > > +
> > > > > > > > > > +#define FME_FEATURE_ID_MAX10_SPI 0xe
> > > > > > > > > > +
> > > > > > > > > > +static const struct dfl_device_id dfl_spi_altera_ids[] = {
> > > > > > > > > > +{ FME_ID, FME_FEATURE_ID_MAX10_SPI },
> > > > > > > > > > +{ }
> > > > > > > > > > +};
> > > > > > > > >
> > > > > > > > > Maybe you can extend the Altera SPI driver with this part?
> > > > > > > >
> > > > > > > > The file, drivers/spi/spi-altera.c, already has platform MODULE_
> > > related
> > > > > > > > code. Wouldn't moving this code to that file produce conflicts?
> > > > > > >
> > > > > > > I've seen other drivers support multiple busses, so it should be
> > > > > > > possible, there might be nuances I'm missing in my brief look at this,
> > > > > > > though.
> > > > > > >
> > > > > > > I think one of them would be MODULE_DEVICE_TABLE(platform, ...)
> > > > > > > and the other one MODULE_DEVICE_TABLE(dfl, ...)
> > > > > > >
> > > > > > > See drivers/i2c/busses/i2c-designware-platdrv.c for an example
> (though
> > > > > > > they might be guarding against what you describe with CONFIG_OF vs
> > > > > > > CONFIG_ACPI)
> > > > > > >
> > > > > > > If that doesn't work we could split it up into
> > > > > > >
> > > > > > > altera-spi-plat.c and altera-spi-dfl.c and altera-spi-core.c
> > > > > > > or something of that sort?
> > > > > > >
> > > > > > > My point being, now that we have a bus, let's use it and develop
> drivers
> > > > > > > according to the Linux device model where possible :)
> > > > > >
> > > > > > Agree. This does make sense from my side too. DFL core provides the
> > > > > mechanism
> > > > > > to enumerate different IPs on FPGA, but each function driver needs to
> go
> > > to
> > > > > > related subsystem for review. : )
> > > > > >
> > > > > > I understand that for FPGA case, it may have some additional logics for
> > > specific
> > > > > > purposes based on common altera spi master IP, then additional code
> for
> > > > >
> > > > > I'm wondering if the additional logics are extensions for common spi-
> altera.
> > > Like
> > > > > the
> > > > > SPI_CORE_PARAMETER register, it is not within the register space of
> > > > > spi-altera,
> > > > >
> > > > >
> > > > > | | +-------------+
> > > > > |DFL|------| +--------+ |
> > > > > |BUS| | |SPI CORE| |
> > > > > | | | |PARAM | |
> > > > > | | | +--------+ |
> > > > > | | | |
> > > > > | | | +--------+ | +-------+
> > > > > | |Indirect| | |spi |
> > > > > | |access +--+---|altera |
> > > > > | |master | | +-------+
> > > > > | +--------+ |
> > > > > +-------------+
> > > > > > a specific product still can be put into altera-spi-xxxx.c or altera-spi-dfl-
> > > xxxx.c
> > > > >
> > > > > So is it proper we integrate this feature into spi-altera? Previously
> > > > > we have merged the dfl-n3000-nios, its spi part is very similar as
> > > > > this driver. The dfl-n3000-nios make the spi-altera as a sub device.
> > > > > Could we borrow the idea, or could we just integrate this driver in
> > > > > dfl-n3000-nios?
> > > >
> > > > Looks like those are enhancements of the IP. They can be applied even
> > >
> > > I don't think the extra registers are the enhancement of the IP. They
> > > are not part of the IP because they are not within the IP's register
> > > space. They are like some external way of describing the IP like
> > > Devicetree or ACPI.
> >
> > Why adding new registers can't be consider as enhancement, those
> > changes serve the original IP and make it better, right? small mmio
> > footprint and parameter registers?
> >
> > >
> > > > other buses are used, not only for DFL, like PCI device or platform device,
> > > > right? then why not put related code together with the original IP?
> > >
> > > The code of devicetree or ACPI parsing are integrated in the IP drivers,
> > > but for this case, it may not be proper for now, cause this style is not
> > > formally introduced by any standard. IP specific parameters description
> > > are not within the scope of DFL now.
> >
> > Not sure if I get your point, but it's possible that we add some enhancements
> > to one IP then driver could be simplified and doesn't need devicetree any more.
> > For sure, it's IP specific thing, not the scope of DFL.
> >
> > Then things become this: extension to IP to allow this IP to be used without
> > device tree, so that this IP can be used in DFL or PCI or other buses without
> > device tree?
>
> It's good to extend an IP, but it needs a published SPEC and stable
> register interfaces. For now, the spi-altera driver conforms to the
> "SPI Core" chapter of the following spec:
>
> https://www.intel.com/content/www/us/en/programmable/documentation/sf
> o1400787952932.html
>
> There is no info about the core parameter register and this specific
> indirect access bus. That's why I don't see these additional parts as
> the enhancements to spi-altera. This DFL feature is like a wrapper for
> the spi-altera sub device.

It really doesn't matter, even if you consider this as an new IP, it's still a SPI
Master, it's driver still need to be reviewed in drivers/spi subsystem. The
worst case is that we need to write a new spi-xxx.c driver, that's it.

From DFL part, DFL only can enumerate the common hardware resources,
but no good way to help thing like this, specific IP parameters (which handle
by devicetree in platform driver). So for some IPs , they still need some
extensions to avoid such dependency (on device tree for parameters). I guess
we may see more similar cases in the future.

Anyway, I think we reached agreement that for device drivers on DFL bus, it
needs to be reviewed in its own subsystem. : )

Thanks
Hao

>
> Thanks
> Yilun

2021-04-13 07:34:09

by matthew.gerlach

[permalink] [raw]
Subject: RE: [PATCH 2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master



On Fri, 9 Apr 2021, Wu, Hao wrote:

>> On Fri, Apr 09, 2021 at 12:02:47PM +0800, Wu, Hao wrote:
>>>>>>>>>>> +
>>>>>>>>>>> +static void dfl_spi_altera_remove(struct dfl_device *dfl_dev)
>>>>>>>>>>> +{
>>>>>>>>>>> +struct dfl_altera_spi *aspi = dev_get_drvdata(&dfl_dev->dev);
>>>>>>>>>>> +
>>>>>>>>>>> +platform_device_unregister(aspi->altr_spi);
>>>>>>>>>>> +}
>>>>>>>>>>> +
>>>>>>>>>>> +#define FME_FEATURE_ID_MAX10_SPI 0xe
>>>>>>>>>>> +
>>>>>>>>>>> +static const struct dfl_device_id dfl_spi_altera_ids[] = {
>>>>>>>>>>> +{ FME_ID, FME_FEATURE_ID_MAX10_SPI },
>>>>>>>>>>> +{ }
>>>>>>>>>>> +};
>>>>>>>>>>
>>>>>>>>>> Maybe you can extend the Altera SPI driver with this part?
>>>>>>>>>
>>>>>>>>> The file, drivers/spi/spi-altera.c, already has platform MODULE_
>>>> related
>>>>>>>>> code. Wouldn't moving this code to that file produce conflicts?
>>>>>>>>
>>>>>>>> I've seen other drivers support multiple busses, so it should be
>>>>>>>> possible, there might be nuances I'm missing in my brief look at this,
>>>>>>>> though.
>>>>>>>>
>>>>>>>> I think one of them would be MODULE_DEVICE_TABLE(platform, ...)
>>>>>>>> and the other one MODULE_DEVICE_TABLE(dfl, ...)
>>>>>>>>
>>>>>>>> See drivers/i2c/busses/i2c-designware-platdrv.c for an example
>> (though
>>>>>>>> they might be guarding against what you describe with CONFIG_OF vs
>>>>>>>> CONFIG_ACPI)
>>>>>>>>
>>>>>>>> If that doesn't work we could split it up into
>>>>>>>>
>>>>>>>> altera-spi-plat.c and altera-spi-dfl.c and altera-spi-core.c
>>>>>>>> or something of that sort?
>>>>>>>>
>>>>>>>> My point being, now that we have a bus, let's use it and develop
>> drivers
>>>>>>>> according to the Linux device model where possible :)
>>>>>>>
>>>>>>> Agree. This does make sense from my side too. DFL core provides the
>>>>>> mechanism
>>>>>>> to enumerate different IPs on FPGA, but each function driver needs to
>> go
>>>> to
>>>>>>> related subsystem for review. : )
>>>>>>>
>>>>>>> I understand that for FPGA case, it may have some additional logics for
>>>> specific
>>>>>>> purposes based on common altera spi master IP, then additional code
>> for
>>>>>>
>>>>>> I'm wondering if the additional logics are extensions for common spi-
>> altera.
>>>> Like
>>>>>> the
>>>>>> SPI_CORE_PARAMETER register, it is not within the register space of
>>>>>> spi-altera,
>>>>>>
>>>>>>
>>>>>> | | +-------------+
>>>>>> |DFL|------| +--------+ |
>>>>>> |BUS| | |SPI CORE| |
>>>>>> | | | |PARAM | |
>>>>>> | | | +--------+ |
>>>>>> | | | |
>>>>>> | | | +--------+ | +-------+
>>>>>> | |Indirect| | |spi |
>>>>>> | |access +--+---|altera |
>>>>>> | |master | | +-------+
>>>>>> | +--------+ |
>>>>>> +-------------+
>>>>>>> a specific product still can be put into altera-spi-xxxx.c or altera-spi-dfl-
>>>> xxxx.c
>>>>>>
>>>>>> So is it proper we integrate this feature into spi-altera? Previously
>>>>>> we have merged the dfl-n3000-nios, its spi part is very similar as
>>>>>> this driver. The dfl-n3000-nios make the spi-altera as a sub device.
>>>>>> Could we borrow the idea, or could we just integrate this driver in
>>>>>> dfl-n3000-nios?
>>>>>
>>>>> Looks like those are enhancements of the IP. They can be applied even
>>>>
>>>> I don't think the extra registers are the enhancement of the IP. They
>>>> are not part of the IP because they are not within the IP's register
>>>> space. They are like some external way of describing the IP like
>>>> Devicetree or ACPI.
>>>
>>> Why adding new registers can't be consider as enhancement, those
>>> changes serve the original IP and make it better, right? small mmio
>>> footprint and parameter registers?
>>>
>>>>
>>>>> other buses are used, not only for DFL, like PCI device or platform device,
>>>>> right? then why not put related code together with the original IP?
>>>>
>>>> The code of devicetree or ACPI parsing are integrated in the IP drivers,
>>>> but for this case, it may not be proper for now, cause this style is not
>>>> formally introduced by any standard. IP specific parameters description
>>>> are not within the scope of DFL now.
>>>
>>> Not sure if I get your point, but it's possible that we add some enhancements
>>> to one IP then driver could be simplified and doesn't need devicetree any more.
>>> For sure, it's IP specific thing, not the scope of DFL.
>>>
>>> Then things become this: extension to IP to allow this IP to be used without
>>> device tree, so that this IP can be used in DFL or PCI or other buses without
>>> device tree?
>>
>> It's good to extend an IP, but it needs a published SPEC and stable
>> register interfaces. For now, the spi-altera driver conforms to the
>> "SPI Core" chapter of the following spec:
>>
>> https://www.intel.com/content/www/us/en/programmable/documentation/sf
>> o1400787952932.html
>>
>> There is no info about the core parameter register and this specific
>> indirect access bus. That's why I don't see these additional parts as
>> the enhancements to spi-altera. This DFL feature is like a wrapper for
>> the spi-altera sub device.
>
> It really doesn't matter, even if you consider this as an new IP, it's still a SPI
> Master, it's driver still need to be reviewed in drivers/spi subsystem. The
> worst case is that we need to write a new spi-xxx.c driver, that's it.
>
> From DFL part, DFL only can enumerate the common hardware resources,
> but no good way to help thing like this, specific IP parameters (which handle
> by devicetree in platform driver). So for some IPs , they still need some
> extensions to avoid such dependency (on device tree for parameters). I guess
> we may see more similar cases in the future.
>
> Anyway, I think we reached agreement that for device drivers on DFL bus, it
> needs to be reviewed in its own subsystem. : )

Yes, I agree that device drivers on the DFL bus should go in the
appropriate the directory of the appropriate framework. As Moritz has
pointed out there are already examples bus specific driver code, for
multiple buses, being the driver framework directory (e.g. Designware
I2C).

In this particular case, the Device Feature is wraps a particular
instantiation of an Altera SPI Master controller. As Yilun pointed out, this
wrapper has a SPI_CORE_PARAMETER register which contains the values
of all the configuration parameters of the Altera SPI Master IP block.
This kind of information would also be included in a Device Tree
description of the instantiation. The Device Feature also implements
indirect register access to the actual registers of the Altera SPI Master
that provides a bridge from the PCIe bus to the Avalon Slave containing
the registers of the Altera SPI Master.

Given the Device Feature wraps an Altera SPI Master, it might still make
sense for the DFL driver to instantiate a sub driver instance for the
Altera SPI Master. I will resubmit the current patches with
drivers/fpga/dfl-spi-altera.c moved to drivers/spi/spi-altera-dfl.c for
feedback from the SPI maintainers and continue investigating collapsing
the DFL driver and the platform sub-driver into a single DFL driver. My
first attempt did not go well.

Matthew

directory of the app >
> Thanks
> Hao
>
>>
>> Thanks
>> Yilun
>