This fixes the RGMII on the sl28 boards. While the network port was
actually working it is still out-of-spec.
Please note, that this is split into two patches because each one fixes
a different commit.
Michael Walle (2):
arm64: dts: freescale: sl28: fix RGMII clock and voltage
arm64: dts: freescale: sl28: fix RGMII clock and voltage
.../boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts | 3 ++-
.../boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts | 5 ++---
2 files changed, 4 insertions(+), 4 deletions(-)
--
2.20.1
During hardware validation it was noticed that the clock isn't
continuously enabled when there is no link. This is because the 125MHz
clock is derived from the internal PLL which seems to go into some kind
of power-down mode every once in a while. The LS1028A expects a contiuous
clock. Thus enable the PLL all the time.
Also, the RGMII pad voltage is wrong. It was configured to 2.5V (that is
the VDDH regulator). The correct voltage is 1.8V, i.e. the VDDIO
regulator.
This fix is for the freescale/fsl-ls1028a-kontron-sl28-var4.dts.
Fixes: 815364d0424e ("arm64: dts: freescale: add Kontron sl28 support")
Signed-off-by: Michael Walle <[email protected]>
---
.../boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts
index df212ed5bb94..e65d1c477e2c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts
@@ -31,11 +31,10 @@
reg = <0x4>;
eee-broken-1000t;
eee-broken-100tx;
-
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
-
- vddio-supply = <&vddh>;
+ qca,keep-pll-enabled;
+ vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";
--
2.20.1
During hardware validation it was noticed that the clock isn't
continuously enabled when there is no link. This is because the 125MHz
clock is derived from the internal PLL which seems to go into some kind
of power-down mode every once in a while. The LS1028A expects a contiuous
clock. Thus enable the PLL all the time.
Also, the RGMII pad voltage is wrong, it was configured to 2.5V (that is
the VDDH regulator). The correct voltage is 1.8V, i.e. the VDDIO
regulator.
This fix is for the freescale/fsl-ls1028a-kontron-sl28-var1.dts.
Fixes: 642856097c18 ("arm64: dts: freescale: sl28: add variant 1")
Signed-off-by: Michael Walle <[email protected]>
---
.../arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts
index 6c309b97587d..e8d31279b7a3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts
@@ -46,7 +46,8 @@
eee-broken-100tx;
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
- vddio-supply = <&vddh>;
+ qca,keep-pll-enabled;
+ vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";
--
2.20.1
On Tue, Apr 13, 2021 at 05:33:47PM +0200, Michael Walle wrote:
> This fixes the RGMII on the sl28 boards. While the network port was
> actually working it is still out-of-spec.
>
> Please note, that this is split into two patches because each one fixes
> a different commit.
>
> Michael Walle (2):
> arm64: dts: freescale: sl28: fix RGMII clock and voltage
> arm64: dts: freescale: sl28: fix RGMII clock and voltage
Can we distinguish the subject a bit by using different prefix like
'sl28-var1' and 'sl28-var4'?
Shawn
>
> .../boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts | 3 ++-
> .../boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts | 5 ++---
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> --
> 2.20.1
>