2021-06-15 17:34:28

by Tinghan Shen

Subject: [PATCH 12/27] arm64: dts: mt8195: fix mmc driver

From: Wenbin Mei <[email protected]>

fix mmc driver with proper clock for mt8195 SoC.

Signed-off-by: Wenbin Mei <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 539f405a4f3d..327ff1b856d2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -926,22 +926,32 @@
};

mmc0: mmc@11230000 {
- compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8192-mmc",
+ "mediatek,mt8183-mmc";
reg = <0 0x11230000 0 0x10000>,
<0 0x11f50000 0 0x1000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>, <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC0>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};

mmc1: mmc@11240000 {
- compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8192-mmc",
+ "mediatek,mt8183-mmc";
reg = <0 0x11240000 0 0x1000>,
<0 0x11c70000 0 0x1000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>, <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC1>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
clock-names = "source", "hclk", "source_cg";
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
status = "disabled";
};

--
2.18.0

2021-06-16 01:32:49

by Wenbin Mei (梅文彬)

Subject: Re: [PATCH 12/27] arm64: dts: mt8195: fix mmc driver

On Wed, 2021-06-16 at 01:32 +0800, Tinghan Shen wrote:
> From: Wenbin Mei <[email protected]>
>
> fix mmc driver with proper clock for mt8195 SoC.
>
> Signed-off-by: Wenbin Mei <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 18 ++++++++++++++----
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 539f405a4f3d..327ff1b856d2 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -926,22 +926,32 @@
> };
>
> mmc0: mmc@11230000 {
> - compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
> + compatible = "mediatek,mt8195-mmc",
> + "mediatek,mt8192-mmc",
> + "mediatek,mt8183-mmc";
I have submitted a patch to fix the
dt-bindings(http://lists.infradead.org/pipermail/linux-mediatek/2021-June/025456.html), Now which should be:
compatible = "mediatek,mt8195-mmc", "mediatek,mt8183-mmc";
> reg = <0 0x11230000 0 0x10000>,
> <0 0x11f50000 0 0x1000>;
> interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>, <&clk26m>;
> + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> + <&infracfg_ao CLK_INFRA_AO_MSDC0>,
> + <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
> clock-names = "source", "hclk", "source_cg";
> status = "disabled";
> };
>
> mmc1: mmc@11240000 {
> - compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
> + compatible = "mediatek,mt8195-mmc",
> + "mediatek,mt8192-mmc",
> + "mediatek,mt8183-mmc";
Ditto, this should be:
compatible = "mediatek,mt8195-mmc", "mediatek,mt8183-mmc";
> reg = <0 0x11240000 0 0x1000>,
> <0 0x11c70000 0 0x1000>;
> interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>, <&clk26m>;
> + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> + <&infracfg_ao CLK_INFRA_AO_MSDC1>,
> + <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
> clock-names = "source", "hclk", "source_cg";
> + assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
> status = "disabled";
> };
>