Hi everyone,
I have just released a second bluesmoke patch:
ftp://ftp.kernel.org/pub/linux/kernel/people/hpa/bluesmoke-2.4.0-test11-pre5-2.diff
This implements support for MCE on chips which don't support MCA (in
addition to enabling MCA for non-Intel chips, like Athlon, which
supports MCA.)
I would appreciate it if people who have chips with MCE but no MCA --
this includes older AMD chips and some Cyrix chips at the very least
-- would please be so kind and try this out.
-hpa
--
<[email protected]> at work, <[email protected]> in private!
"Unix gives you enough rope to shoot yourself in the foot."
http://www.zytor.com/~hpa/puzzle.txt
Followup to: <[email protected]>
By author: "H. Peter Anvin" <[email protected]>
In newsgroup: linux.dev.kernel
>
> Hi everyone,
>
> I have just released a second bluesmoke patch:
>
> ftp://ftp.kernel.org/pub/linux/kernel/people/hpa/bluesmoke-2.4.0-test11-pre5-2.diff
>
> This implements support for MCE on chips which don't support MCA (in
> addition to enabling MCA for non-Intel chips, like Athlon, which
> supports MCA.)
>
> I would appreciate it if people who have chips with MCE but no MCA --
> this includes older AMD chips and some Cyrix chips at the very least
> -- would please be so kind and try this out.
>
Me bad... I accidentally let a one-character typo (missing & sign)
in... I have generated a -3 version of this patch.
-hpa
--
<[email protected]> at work, <[email protected]> in private!
"Unix gives you enough rope to shoot yourself in the foot."
http://www.zytor.com/~hpa/puzzle.txt
On 15 Nov 2000, H. Peter Anvin wrote:
>This implements support for MCE on chips which don't support MCA (in
>addition to enabling MCA for non-Intel chips, like Athlon, which
>supports MCA.)
>
>I would appreciate it if people who have chips with MCE but no MCA --
>this includes older AMD chips and some Cyrix chips at the very least
>-- would please be so kind and try this out.
I have a K6-III which announces MCE but not MCA, so I was going to
test this on that machine.
However, both the K6-III manual and the K6 BIOS guide state quite
clearly that the K6 family only has a "stub" MCE implementation.
The MCE capability is announced, there are two MCE-related MSRs,
and there is a CR4.MCE flag, but none of it actually _does_ anything.
The new CPU detection code should probably clear FEATURE_MCE for K6 CPUs.
(We might consider it an AMD bug, but in their defense, they do state
that the stub implementation was done for "compatibility" reasons.)
/Mikael
Mikael Pettersson wrote:
>
> On 15 Nov 2000, H. Peter Anvin wrote:
>
> >This implements support for MCE on chips which don't support MCA (in
> >addition to enabling MCA for non-Intel chips, like Athlon, which
> >supports MCA.)
> >
> >I would appreciate it if people who have chips with MCE but no MCA --
> >this includes older AMD chips and some Cyrix chips at the very least
> >-- would please be so kind and try this out.
>
> I have a K6-III which announces MCE but not MCA, so I was going to
> test this on that machine.
>
> However, both the K6-III manual and the K6 BIOS guide state quite
> clearly that the K6 family only has a "stub" MCE implementation.
> The MCE capability is announced, there are two MCE-related MSRs,
> and there is a CR4.MCE flag, but none of it actually _does_ anything.
>
> The new CPU detection code should probably clear FEATURE_MCE for K6 CPUs.
> (We might consider it an AMD bug, but in their defense, they do state
> that the stub implementation was done for "compatibility" reasons.)
>
Actually, that's just fine. It won't cause any harm; all that will mean
is that it will never raise #MC. Remember that a CPU should, in proper
operation, never raise #MC anyway!
Their implementation is a legal (albeit useless) implementation of MCE.
No need to special-case it.
-hpa
--
<[email protected]> at work, <[email protected]> in private!
"Unix gives you enough rope to shoot yourself in the foot."
http://www.zytor.com/~hpa/puzzle.txt
> I would appreciate it if people who have chips with MCE but no MCA --
> this includes older AMD chips and some Cyrix chips at the very least
> -- would please be so kind and try this out.
Hmm, I've looked at the patch and I guess you may try to decode MSR#0 and
MSR#1 for Pentium processors (I may provide an example patch). I believe
certain AMD processors support these registers, too. I don't know how
other vendors treat MSR#0 and MSR#1 but given they were sufficiently
documented since the beginning, they may very well be pretty standard for
all of them.
I'll try the patch at my Pentium machine, yet, but it runs so stable I
don't expect an MCE anytime soon. ;-}
--
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+--------------------------------------------------------------+
+ e-mail: [email protected], PGP key available +