Exynos 7885 has product id "0xE7885000". Add this id to the ids with
the name.
The downstream driver sets sub_rev to 2 if we are on Exynos 7885, we
detected sub_rev 1 and the 27th bit of the revision register is set.
This is presumably because Samsung might have set the wrong bits on
rev2 of the SoC in the chipid, but we may never know as we have no
manual.
Both the SM-A530F/jackpotlte with Exynos7885 and the SM-M305/m30lte
with Exynos7904 (rebranded Exynos7885 with lower clock speeds) seem
to have this bit set to 1 and have a sub_rev of 1 otherwise, but the
downstream driver corrects it to 2.
Let's replicate this behaviour in upstream too!
Signed-off-by: David Virag <[email protected]>
---
drivers/soc/samsung/exynos-chipid.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c
index a28053ec7e6a..ec8c76275aec 100644
--- a/drivers/soc/samsung/exynos-chipid.c
+++ b/drivers/soc/samsung/exynos-chipid.c
@@ -55,6 +55,7 @@ static const struct exynos_soc_id {
{ "EXYNOS5440", 0xE5440000 },
{ "EXYNOS5800", 0xE5422000 },
{ "EXYNOS7420", 0xE7420000 },
+ { "EXYNOS7885", 0xE7885000 },
{ "EXYNOS850", 0xE3830000 },
{ "EXYNOSAUTOV9", 0xAAA80000 },
};
@@ -88,6 +89,14 @@ static int exynos_chipid_get_chipid_info(struct regmap *regmap,
}
main_rev = (val >> data->main_rev_shift) & EXYNOS_REV_PART_MASK;
sub_rev = (val >> data->sub_rev_shift) & EXYNOS_REV_PART_MASK;
+
+ //Exynos 7885 revision 2 apparently has the 27th bit set instead of having
+ //a sub_rev of 2. Correct for this!
+ if (soc_info->product_id == 0xE7885000) {
+ if ((sub_rev == 1) && (val & 0x04000000))
+ sub_rev = 2;
+ }
+
soc_info->revision = (main_rev << EXYNOS_REV_PART_SHIFT) | sub_rev;
return 0;
--
2.33.1