This series supercedes [1]. Major change in this series is that it is now
optional to include a gpu name in the gpu-list. This helps to avoid the
confusion when we have different SKUs with different gpu names. And also
I am pretty happy that the overall changes are smaller now.
[1] https://patchwork.freedesktop.org/series/99048/
Changes in v2:
- use devm_kasprintf() to generate gpu name (Rob)
Akhil P Oommen (5):
drm/msm: Use generic name for gpu resources
drm/msm/adreno: Generate name from chipid for 7c3
drm/msm/a6xx: Add support for 7c3 SKUs
drm/msm/adreno: Expose speedbin to userspace
arm64: dts: qcom: sc7280: Support gpu speedbin
arch/arm64/boot/dts/qcom/sc7280.dtsi | 46 ++++++++++++++++++++++++++++++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 ++++++++++--
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 -
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 36 +++++++++++++++++++----
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 ++
drivers/gpu/drm/msm/msm_gpu.c | 4 +--
6 files changed, 97 insertions(+), 11 deletions(-)
--
2.7.4
Add support for 7c3 SKU detection using speedbin fuse.
Signed-off-by: Akhil P Oommen <[email protected]>
---
(no changes since v1)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 17cfad64..f308a3f 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1736,6 +1736,18 @@ static u32 a618_get_speed_bin(u32 fuse)
return UINT_MAX;
}
+static u32 adreno_7c3_get_speed_bin(u32 fuse)
+{
+ if (fuse == 0)
+ return 0;
+ else if (fuse == 117)
+ return 0;
+ else if (fuse == 190)
+ return 1;
+
+ return UINT_MAX;
+}
+
static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
{
u32 val = UINT_MAX;
@@ -1743,6 +1755,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev))
val = a618_get_speed_bin(fuse);
+ if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
+ val = adreno_7c3_get_speed_bin(fuse);
+
if (val == UINT_MAX) {
DRM_DEV_ERROR(dev,
"missing support for speed-bin: %u. Some OPPs may not be supported by hardware",
--
2.7.4
Add speedbin fuse and additional OPPs for gpu to support sc7280 SKUs.
Signed-off-by: Akhil P Oommen <[email protected]>
---
(no changes since v1)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 46 ++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 365a2e0..f8fc8b8 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -605,6 +605,11 @@
power-domains = <&rpmhpd SC7280_MX>;
#address-cells = <1>;
#size-cells = <1>;
+
+ gpu_speed_bin: gpu_speed_bin@1e9 {
+ reg = <0x1e9 0x2>;
+ bits = <5 8>;
+ };
};
sdhc_1: sdhci@7c4000 {
@@ -1762,6 +1767,9 @@
interconnect-names = "gfx-mem";
#cooling-cells = <2>;
+ nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cell-names = "speed_bin";
+
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -1769,18 +1777,56 @@
opp-hz = /bits/ 64 <315000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <1804000>;
+ opp-supported-hw = <0x03>;
};
opp-450000000 {
opp-hz = /bits/ 64 <450000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <4068000>;
+ opp-supported-hw = <0x03>;
};
opp-550000000 {
opp-hz = /bits/ 64 <550000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <6832000>;
+ opp-supported-hw = <0x03>;
+ };
+
+ opp-608000000 {
+ opp-hz = /bits/ 64 <608000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ opp-peak-kBps = <8368000>;
+ opp-supported-hw = <0x02>;
+ };
+
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <8532000>;
+ opp-supported-hw = <0x02>;
+ };
+
+ opp-812000000 {
+ opp-hz = /bits/ 64 <812000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-peak-kBps = <8532000>;
+ opp-supported-hw = <0x02>;
+ };
+
+ opp-840000000 {
+ opp-hz = /bits/ 64 <840000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ opp-peak-kBps = <8532000>;
+ opp-supported-hw = <0x02>;
+ };
+
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ opp-peak-kBps = <8532000>;
+ opp-supported-hw = <0x02>;
};
};
};
--
2.7.4
Use a gpu name which is sprintf'ed from the chipid for 7c3 gpu instead of
hardcoding one. This helps to avoid code churn in case of a gpu rename.
Signed-off-by: Akhil P Oommen <[email protected]>
---
Changes in v2:
- use devm_kasprintf() to generate gpu name (Rob)
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 -
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 +++++++++++++--
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index fb26193..89cfd84 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -318,7 +318,6 @@ static const struct adreno_info gpulist[] = {
.hwcg = a660_hwcg,
}, {
.rev = ADRENO_REV(6, 3, 5, ANY_ID),
- .name = "Adreno 7c Gen 3",
.fw = {
[ADRENO_FW_SQE] = "a660_sqe.fw",
[ADRENO_FW_GMU] = "a660_gmu.bin",
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index f33cfa4..d9d0c13 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -929,12 +929,23 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
struct adreno_platform_config *config = dev->platform_data;
struct msm_gpu_config adreno_gpu_config = { 0 };
struct msm_gpu *gpu = &adreno_gpu->base;
+ struct adreno_rev *rev = &config->rev;
+ const char *gpu_name;
adreno_gpu->funcs = funcs;
adreno_gpu->info = adreno_info(config->rev);
adreno_gpu->gmem = adreno_gpu->info->gmem;
adreno_gpu->revn = adreno_gpu->info->revn;
- adreno_gpu->rev = config->rev;
+ adreno_gpu->rev = *rev;
+
+ gpu_name = adreno_gpu->info->name;
+ if (!gpu_name) {
+ gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d",
+ rev->core, rev->major, rev->minor,
+ rev->patchid);
+ if (!gpu_name)
+ return -ENOMEM;
+ }
adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
@@ -948,7 +959,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
pm_runtime_enable(dev);
return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
- adreno_gpu->info->name, &adreno_gpu_config);
+ gpu_name, &adreno_gpu_config);
}
void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
--
2.7.4