fsl,clk-source property is of type uint8 and need to be defined as
"/bits/ 8 <0>". Simply setting value to 0 raise warning:
can@2180000: fsl,clk-source:0: [0, 0, 0, 0] is too long
Signed-off-by: Kuldeep Singh <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index c5daa15b020d..82bd8c0f318b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -909,7 +909,7 @@ can0: can@2180000 {
QORIQ_CLK_PLL_DIV(8)>,
<&clockgen QORIQ_CLK_SYSCLK 0>;
clock-names = "ipg", "per";
- fsl,clk-source = <0>;
+ fsl,clk-source = /bits/ 8 <0>;
status = "disabled";
};
@@ -921,7 +921,7 @@ can1: can@2190000 {
QORIQ_CLK_PLL_DIV(8)>,
<&clockgen QORIQ_CLK_SYSCLK 0>;
clock-names = "ipg", "per";
- fsl,clk-source = <0>;
+ fsl,clk-source = /bits/ 8 <0>;
status = "disabled";
};
--
2.25.1
On Sun, Apr 03, 2022 at 12:38:55AM +0530, Kuldeep Singh wrote:
> fsl,clk-source property is of type uint8 and need to be defined as
> "/bits/ 8 <0>". Simply setting value to 0 raise warning:
> can@2180000: fsl,clk-source:0: [0, 0, 0, 0] is too long
>
> Signed-off-by: Kuldeep Singh <[email protected]>
Applied, thanks!