2022-04-12 22:03:34

by Herve Codina

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Subject: [PATCH 0/6] RZN1 USB Host support

Hi,

This series add support for the USB Host controllers available on
RZN1 (r9a06g032) SOC.

These USB Host controllers are PCI OHCI/EHCI controllers located
behind a bridge.

Regards,
Herve

Herve Codina (6):
PCI: rcar-gen2: Add support for clocks
dt-bindings: PCI: pci-rcar-gen2: Add device tree support for r9a06g032
PCI: rcar-gen2: Add R9A06G032 support
ARM: dts: r9a06g032: Add internal PCI bridge node
ARM: dts: r9a06g032: Add USB PHY DT support
ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY

.../devicetree/bindings/pci/pci-rcar-gen2.txt | 4 +-
arch/arm/boot/dts/r9a06g032.dtsi | 46 +++++++++++++++++++
drivers/pci/controller/pci-rcar-gen2.c | 30 +++++++++++-
3 files changed, 77 insertions(+), 3 deletions(-)

--
2.35.1


2022-04-12 22:51:51

by Herve Codina

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Subject: [PATCH 1/6] PCI: rcar-gen2: Add support for clocks

The PCI rcar-gen2 does not call any clk_prepare_enable().
This lead to an access failure when the driver tries to access
the IP (at least on a RZ/N1D platform).

Prepare and enable clocks using the bulk version of
clk_prepare_enable() in order to prepare and enable all clocks
attached to this device.

Signed-off-by: Herve Codina <[email protected]>
---
drivers/pci/controller/pci-rcar-gen2.c | 28 ++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/pci-rcar-gen2.c b/drivers/pci/controller/pci-rcar-gen2.c
index 35804ea394fd..528bc3780e01 100644
--- a/drivers/pci/controller/pci-rcar-gen2.c
+++ b/drivers/pci/controller/pci-rcar-gen2.c
@@ -8,6 +8,7 @@
* Author: Valentine Barshak <[email protected]>
*/

+#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
@@ -99,6 +100,8 @@ struct rcar_pci {
struct resource mem_res;
struct resource *cfg_res;
int irq;
+ struct clk_bulk_data *clocks;
+ int nclocks;
};

/* PCI configuration space operations */
@@ -282,6 +285,7 @@ static int rcar_pci_probe(struct platform_device *pdev)
struct rcar_pci *priv;
struct pci_host_bridge *bridge;
void __iomem *reg;
+ int ret;

bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
if (!bridge)
@@ -305,13 +309,25 @@ static int rcar_pci_probe(struct platform_device *pdev)
priv->mem_res = *mem_res;
priv->cfg_res = cfg_res;

+ ret = devm_clk_bulk_get_all(dev, &priv->clocks);
+ if (ret < 0) {
+ dev_err(dev, "failed to get clocks %d\n", ret);
+ return ret;
+ }
+ priv->nclocks = ret;
+
+ ret = clk_bulk_prepare_enable(priv->nclocks, priv->clocks);
+ if (ret)
+ return ret;
+
priv->irq = platform_get_irq(pdev, 0);
priv->reg = reg;
priv->dev = dev;

if (priv->irq < 0) {
dev_err(dev, "no valid irq found\n");
- return priv->irq;
+ ret = priv->irq;
+ goto disable_clocks;
}

bridge->ops = &rcar_pci_ops;
@@ -320,7 +336,15 @@ static int rcar_pci_probe(struct platform_device *pdev)

rcar_pci_setup(priv);

- return pci_host_probe(bridge);
+ ret = pci_host_probe(bridge);
+ if (ret < 0)
+ goto disable_clocks;
+
+ return 0;
+
+disable_clocks:
+ clk_bulk_disable_unprepare(priv->nclocks, priv->clocks);
+ return ret;
}

static const struct of_device_id rcar_pci_of_match[] = {
--
2.35.1

2022-04-12 23:12:39

by Herve Codina

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Subject: [PATCH 5/6] ARM: dts: r9a06g032: Add USB PHY DT support

Define the r9a06g032 generic part of the USB PHY device node.

Signed-off-by: Herve Codina <[email protected]>
---
arch/arm/boot/dts/r9a06g032.dtsi | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index c6a99b2a8fb3..c9336dc4888a 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -59,6 +59,12 @@ ext_rtc_clk: extrtcclk {
clock-frequency = <0>;
};

+ usbphy: usbphy {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ status = "disabled";
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
--
2.35.1

2022-04-12 23:22:42

by Herve Codina

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Subject: [PATCH 2/6] dt-bindings: PCI: pci-rcar-gen2: Add device tree support for r9a06g032

Add internal PCI bridge support for the r9a06g032 SoC. The Renesas
RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one
present in the R-Car Gen2 family.

Signed-off-by: Herve Codina <[email protected]>
---
Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
index aeba38f0a387..098ea12e6c95 100644
--- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
+++ b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
@@ -15,7 +15,9 @@ Required properties:
"renesas,pci-r8a7793" for the R8A7793 SoC;
"renesas,pci-r8a7794" for the R8A7794 SoC;
"renesas,pci-rcar-gen2" for a generic R-Car Gen2 or
- RZ/G1 compatible device.
+ RZ/G1 compatible device;
+ "renesas,pci-r9a06g032" for the R9A06G032 (RZ/N1D) SoC;
+ "renesas,pci-rzn1" for a generic RZ/N1 compatible device.


When compatible with the generic version, nodes must list the
--
2.35.1