Devices on some PCIe buses may be cache coherent and must be marked as
such in the devicetree to avoid data corruption.
This is specifically needed on recent Qualcomm platforms like SC8280XP.
Signed-off-by: Johan Hovold <[email protected]>
---
Lorenzo, the corresponding SC8280XP DT fix is heading for 6.2 so it
would be nice if this one could be merged for 6.2-rc1 (or -rc2) as well
to avoid the corresponding DT validation warnings.
Johan
Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 2f851c804bb0..a5859bb3dc28 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -62,6 +62,8 @@ properties:
minItems: 3
maxItems: 13
+ dma-coherent: true
+
interconnects:
maxItems: 2
--
2.37.4
On Mon, 05 Dec 2022 10:45:30 +0100, Johan Hovold wrote:
> Devices on some PCIe buses may be cache coherent and must be marked as
> such in the devicetree to avoid data corruption.
>
> This is specifically needed on recent Qualcomm platforms like SC8280XP.
>
> Signed-off-by: Johan Hovold <[email protected]>
> ---
>
> Lorenzo, the corresponding SC8280XP DT fix is heading for 6.2 so it
> would be nice if this one could be merged for 6.2-rc1 (or -rc2) as well
> to avoid the corresponding DT validation warnings.
>
> Johan
>
>
> Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <[email protected]>
On Mon, Dec 05, 2022 at 10:45:30AM +0100, Johan Hovold wrote:
> Devices on some PCIe buses may be cache coherent and must be marked as
> such in the devicetree to avoid data corruption.
>
> This is specifically needed on recent Qualcomm platforms like SC8280XP.
>
> Signed-off-by: Johan Hovold <[email protected]>
> ---
>
> Lorenzo, the corresponding SC8280XP DT fix is heading for 6.2 so it
> would be nice if this one could be merged for 6.2-rc1 (or -rc2) as well
> to avoid the corresponding DT validation warnings.
What's the commit base for this patch ? I tried applying to my pci/dt
branch to no avail, please let me know and I will merge it.
Lorenzo
>
> Johan
>
>
> Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index 2f851c804bb0..a5859bb3dc28 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -62,6 +62,8 @@ properties:
> minItems: 3
> maxItems: 13
>
> + dma-coherent: true
> +
> interconnects:
> maxItems: 2
>
> --
> 2.37.4
>
On Tue, Dec 06, 2022 at 11:56:34AM +0100, Lorenzo Pieralisi wrote:
> On Mon, Dec 05, 2022 at 10:45:30AM +0100, Johan Hovold wrote:
> > Devices on some PCIe buses may be cache coherent and must be marked as
> > such in the devicetree to avoid data corruption.
> >
> > This is specifically needed on recent Qualcomm platforms like SC8280XP.
> >
> > Signed-off-by: Johan Hovold <[email protected]>
> > ---
> >
> > Lorenzo, the corresponding SC8280XP DT fix is heading for 6.2 so it
> > would be nice if this one could be merged for 6.2-rc1 (or -rc2) as well
> > to avoid the corresponding DT validation warnings.
>
> What's the commit base for this patch ? I tried applying to my pci/dt
> branch to no avail, please let me know and I will merge it.
That should be pci/qcom which has 3a936b2a5a58 ("dt-bindings: PCI: qcom:
Add SC8280XP/SA8540P interconnects").
Johan
On Mon, 5 Dec 2022 10:45:30 +0100, Johan Hovold wrote:
> Devices on some PCIe buses may be cache coherent and must be marked as
> such in the devicetree to avoid data corruption.
>
> This is specifically needed on recent Qualcomm platforms like SC8280XP.
>
>
Applied to pci/qcom, thanks!
[1/1] dt-bindings: PCI: qcom: Allow 'dma-coherent' property
https://git.kernel.org/lpieralisi/pci/c/74eac50391ce
Thanks,
Lorenzo