Add all the required nodes for SM6350's A619 and fix up its GPUCC
bindings.
This has been ready for like 1.5y now, time to finally merge it as
the display part will take some more time (due to the HW catalog rework).
Depends on (bindings, admittedly I could have organized it better):
https://lore.kernel.org/linux-arm-msm/[email protected]/#t
Signed-off-by: Konrad Dybcio <[email protected]>
---
Changes in v2:
- gpu_speed_bin@ -> gpu-speed-bin@ [3/5]
- Order GPU nodes properly [4/5]
- sort out the clock-names issue
- throw in the dpu patch, as the driver part has been finally merged
- pick up tags
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Konrad Dybcio (7):
clk: qcom: gpucc-sm6350: Introduce index-based clk lookup
clk: qcom: gpucc-sm6350: Fix clock source names
arm64: dts: qcom: sm6350: Add GPUCC node
arm64: dts: qcom: sm6350: Add QFPROM node
arm64: dts: qcom: sm6350: Add GPU nodes
arm64: dts: qcom: sm6350: Fix ZAP region
arm64: dts: qcom: sm6350: Add DPU1 nodes
arch/arm64/boot/dts/qcom/sm6350.dtsi | 394 ++++++++++++++++++++++++++++++++++-
drivers/clk/qcom/gpucc-sm6350.c | 18 +-
2 files changed, 402 insertions(+), 10 deletions(-)
---
base-commit: b16049b21162bb649cdd8519642a35972b7910fe
change-id: 20230315-topic-lagoon_gpu-8c2abccbc6eb
Best regards,
--
Konrad Dybcio <[email protected]>
Add the nowadays-prefered and marginally faster way of looking up parent
clocks in the device tree. It also allows for clock-names-independent
operation, so long as the order (which is enforced by schema) is kept.
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/gpucc-sm6350.c | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm6350.c
index ef15185a99c3..a9887d1f0ed7 100644
--- a/drivers/clk/qcom/gpucc-sm6350.c
+++ b/drivers/clk/qcom/gpucc-sm6350.c
@@ -24,6 +24,12 @@
#define CX_GMU_CBCR_WAKE_MASK 0xF
#define CX_GMU_CBCR_WAKE_SHIFT 8
+enum {
+ DT_BI_TCXO,
+ DT_GPLL0_OUT_MAIN,
+ DT_GPLL0_OUT_MAIN_DIV,
+};
+
enum {
P_BI_TCXO,
P_GPLL0_OUT_MAIN,
@@ -61,6 +67,7 @@ static struct clk_alpha_pll gpu_cc_pll0 = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll0",
.parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO,
.fw_name = "bi_tcxo",
},
.num_parents = 1,
@@ -104,6 +111,7 @@ static struct clk_alpha_pll gpu_cc_pll1 = {
.hw.init = &(struct clk_init_data){
.name = "gpu_cc_pll1",
.parent_data = &(const struct clk_parent_data){
+ .index = DT_BI_TCXO,
.fw_name = "bi_tcxo",
},
.num_parents = 1,
@@ -121,11 +129,11 @@ static const struct parent_map gpu_cc_parent_map_0[] = {
};
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
- { .fw_name = "bi_tcxo" },
+ { .index = DT_BI_TCXO, .fw_name = "bi_tcxo" },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
- { .fw_name = "gcc_gpu_gpll0_clk" },
- { .fw_name = "gcc_gpu_gpll0_div_clk" },
+ { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk" },
+ { .index = DT_GPLL0_OUT_MAIN_DIV, .fw_name = "gcc_gpu_gpll0_div_clk" },
};
static const struct parent_map gpu_cc_parent_map_1[] = {
@@ -138,12 +146,12 @@ static const struct parent_map gpu_cc_parent_map_1[] = {
};
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
- { .fw_name = "bi_tcxo" },
+ { .index = DT_BI_TCXO, .fw_name = "bi_tcxo" },
{ .hw = &crc_div.hw },
{ .hw = &gpu_cc_pll0.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
{ .hw = &gpu_cc_pll1.clkr.hw },
- { .fw_name = "gcc_gpu_gpll0_clk" },
+ { .index = DT_GPLL0_OUT_MAIN, .fw_name = "gcc_gpu_gpll0_clk" },
};
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
--
2.41.0
From: Konrad Dybcio <[email protected]>
Add a node for the QFPROM NVMEM hw and define the GPU fuse.
Signed-off-by: Konrad Dybcio <[email protected]>
Reviewed-by: Luca Weiss <[email protected]>
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index fd35810bcfb5..c0f34bc1d78c 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -805,6 +805,18 @@ ipcc: mailbox@408000 {
#mbox-cells = <2>;
};
+ qfprom: qfprom@784000 {
+ compatible = "qcom,sm6350-qfprom", "qcom,qfprom";
+ reg = <0 0x00784000 0 0x3000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gpu_speed_bin: gpu-speed-bin@2015 {
+ reg = <0x2015 0x1>;
+ bits = <0 8>;
+ };
+ };
+
rng: rng@793000 {
compatible = "qcom,prng-ee";
reg = <0 0x00793000 0 0x1000>;
--
2.41.0
On Wed, 14 Jun 2023 13:35:31 +0200, Konrad Dybcio wrote:
> Add all the required nodes for SM6350's A619 and fix up its GPUCC
> bindings.
>
> This has been ready for like 1.5y now, time to finally merge it as
> the display part will take some more time (due to the HW catalog rework).
>
> Depends on (bindings, admittedly I could have organized it better):
> https://lore.kernel.org/linux-arm-msm/[email protected]/#t
>
> [...]
Applied, thanks!
[3/7] arm64: dts: qcom: sm6350: Add GPUCC node
commit: 75a511b1e5ff6ffadb9b51d85beee8c7bcc29ba9
[4/7] arm64: dts: qcom: sm6350: Add QFPROM node
commit: 5b1e5d9a21ec2ad0654ce192371ed81b12088c6f
[5/7] arm64: dts: qcom: sm6350: Add GPU nodes
commit: bd9b767502806faccbac6f2c8db09d0ea6ca6e3e
[6/7] arm64: dts: qcom: sm6350: Fix ZAP region
commit: 44bcded2be4fe9b9d0b6e48075c9947b75c0af63
[7/7] arm64: dts: qcom: sm6350: Add DPU1 nodes
commit: 26c71d31f8be3493006140961acf6be204004fdb
Best regards,
--
Bjorn Andersson <[email protected]>