This series adds support for the AXI PWM GEN subsystem found on FPGA IP
cores. It can be used to generate configurable PWM outputs, and includes
options for external synchronization and clock signals. The work is
being done on behalf of, and therefore lists maintainers from Analog
Devices, Inc.
The series has been tested on actual hardware using an EVAL-AD7985FMCZ
evaluation board. An oscilloscope was used to validate that the
generated PWM signal matched the requested one.
---
v2 changes:
* Address feedback for driver and device tree in v1:
* Use more reasonable Kconfig approach
* Use common prefixes for all functions
* Rename axi_pwmgen struct to axi_pwmgen_ddata
* Change use of "pwm" to "ddata"
* Set and check state->polarity
* Multiply safely with mul_u64_u64_div_u64()
* Improve handling of max and zero periods
* Error if clk_rate_hz > NSEC_PER_SEC
* Add "Limitations" section at top of pwm-axi-pwmgen.c
* Don't disable outputs by default
* Remove unnecessary macros for period, duty, offset
* Fix axi_pwmgen_ddata alignment
* Don't artificially limit npwm to four
* Use clk_rate_exclusive_get(), balance with clk_rate_exclusive_put()
* Cache clk rate in axi_pwmgen_ddata
* Don't assign pwm->chip.base, do assign pwm->chip.atomic
* Relocate "unevaluatedProperties" in device tree binding
* Remove redundant calls to clk_get_rate
* Test contents of AXI_PWMGEN_REG_CORE_MAGIC instead of
arbitrary AXI_PWMGEN_TEST_DATA in AXI_PWMGEN_REG_SCRATCHPAD
* Remove redundant clk struct from axi_pwmgen_ddata
* Add self as module author
* Add major version check for IP core
Link to v1: https://lore.kernel.org/linux-pwm/[email protected]/
Drew Fustini (2):
dt-bindings: pwm: Add AXI PWM generator
pwm: Add driver for AXI PWM generator
.../bindings/pwm/adi,axi-pwmgen.yaml | 48 ++++
MAINTAINERS | 9 +
drivers/pwm/Kconfig | 13 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-axi-pwmgen.c | 246 ++++++++++++++++++
5 files changed, 317 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml
create mode 100644 drivers/pwm/pwm-axi-pwmgen.c
--
2.43.0
From: Drew Fustini <[email protected]>
Add Analog Devices AXI PWM generator.
Link: https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
Signed-off-by: Drew Fustini <[email protected]>
Co-developed-by: Trevor Gamblin <[email protected]>
Signed-off-by: Trevor Gamblin <[email protected]>
---
v2 changes:
* Address feedback for driver and device tree in v1:
* Relocate "unevaluatedProperties" in device tree binding
* Remove redundant "bindings for" in description
---
.../bindings/pwm/adi,axi-pwmgen.yaml | 48 +++++++++++++++++++
MAINTAINERS | 8 ++++
2 files changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml
diff --git a/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml b/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml
new file mode 100644
index 000000000000..63461920a362
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/adi,axi-pwmgen.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AXI PWM generator
+
+maintainers:
+ - Michael Hennerich <[email protected]>
+ - Nuno Sá <[email protected]>
+
+description:
+ The Analog Devices AXI PWM generator can generate PWM signals
+ with variable pulse width and period.
+
+ https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ const: adi,axi-pwmgen-1.00.a
+
+ reg:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+ clocks:
+ maxItems: 1
+
+required:
+ - reg
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ pwm@44b00000 {
+ compatible = "adi,axi-pwmgen-1.00.a";
+ reg = <0x44b00000 0x1000>;
+ clocks = <&spi_clk>;
+ #pwm-cells = <2>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 8d1052fa6a69..8a4ed5545680 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3431,6 +3431,14 @@ W: https://ez.analog.com/linux-software-drivers
F: Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml
F: drivers/spi/spi-axi-spi-engine.c
+AXI PWM GENERATOR
+M: Michael Hennerich <[email protected]>
+M: Nuno Sá <[email protected]>
+L: [email protected]
+S: Supported
+W: https://ez.analog.com/linux-software-drivers
+F: Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml
+
AXXIA I2C CONTROLLER
M: Krzysztof Adamski <[email protected]>
L: [email protected]
--
2.43.0
From: Drew Fustini <[email protected]>
Add support for the Analog Devices AXI PWM Generator. This device is an
FPGA-implemented peripheral used as PWM signal generator and can be
interfaced with AXI4. The register map of this peripheral makes it
possible to configure the period and duty cycle of the output signal.
Link: https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
Co-developed-by: Sergiu Cuciurean <[email protected]>
Signed-off-by: Sergiu Cuciurean <[email protected]>
Co-developed-by: David Lechner <[email protected]>
Signed-off-by: David Lechner <[email protected]>
Signed-off-by: Drew Fustini <[email protected]>
Co-developed-by: Trevor Gamblin <[email protected]>
Signed-off-by: Trevor Gamblin <[email protected]>
---
v2 changes:
* Address feedback for driver and device tree in v1:
* Use more reasonable Kconfig approach
* Use common prefixes for all functions
* Rename axi_pwmgen struct to axi_pwmgen_ddata
* Change use of "pwm" to "ddata"
* Set and check state->polarity
* Multiply safely with mul_u64_u64_div_u64()
* Improve handling of max and zero periods
* Error if clk_rate_hz > NSEC_PER_SEC
* Add "Limitations" section at top of pwm-axi-pwmgen.c
* Don't disable outputs by default
* Remove unnecessary macros for period, duty, offset
* Fix axi_pwmgen_ddata alignment
* Don't artificially limit npwm to four
* Use clk_rate_exclusive_get(), balance with clk_rate_exclusive_put()
* Cache clk rate in axi_pwmgen_ddata
* Don't assign pwm->chip.base, do assign pwm->chip.atomic
* Remove redundant calls to clk_get_rate
* Test contents of AXI_PWMGEN_REG_CORE_MAGIC instead of
arbitrary AXI_PWMGEN_TEST_DATA in AXI_PWMGEN_REG_SCRATCHPAD
* Remove redundant clk struct from axi_pwmgen_ddata
* Add self as module author
* Add major version check for IP core
---
MAINTAINERS | 1 +
drivers/pwm/Kconfig | 13 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-axi-pwmgen.c | 246 +++++++++++++++++++++++++++++++++++
4 files changed, 261 insertions(+)
create mode 100644 drivers/pwm/pwm-axi-pwmgen.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 8a4ed5545680..2baa7a0a1c8c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3438,6 +3438,7 @@ L: [email protected]
S: Supported
W: https://ez.analog.com/linux-software-drivers
F: Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml
+F: drivers/pwm/pwm-axi-pwmgen.c
AXXIA I2C CONTROLLER
M: Krzysztof Adamski <[email protected]>
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 4b956d661755..d44b0e86adee 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -98,6 +98,19 @@ config PWM_ATMEL_TCB
To compile this driver as a module, choose M here: the module
will be called pwm-atmel-tcb.
+config PWM_AXI_PWMGEN
+ tristate "Analog Devices AXI PWM generator"
+ depends on MICROBLAZE || NIOS2 || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || COMPILE_TEST
+ select REGMAP_MMIO
+ help
+ This enables support for the Analog Devices AXI PWM generator.
+
+ This is a configurable PWM generator with variable pulse width and
+ period.
+
+ To compile this driver as a module, choose M here: the module will be
+ called pwm-axi-pwmgen.
+
config PWM_BCM_IPROC
tristate "iProc PWM support"
depends on ARCH_BCM_IPROC || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index c5ec9e168ee7..8322089954e9 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PWM_APPLE) += pwm-apple.o
obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
+obj-$(CONFIG_PWM_AXI_PWMGEN) += pwm-axi-pwmgen.o
obj-$(CONFIG_PWM_BCM_IPROC) += pwm-bcm-iproc.o
obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o
obj-$(CONFIG_PWM_BCM2835) += pwm-bcm2835.o
diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c
new file mode 100644
index 000000000000..39d2c7be0cb4
--- /dev/null
+++ b/drivers/pwm/pwm-axi-pwmgen.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Analog Devices AXI PWM generator
+ *
+ * Copyright 2024 Analog Devices Inc.
+ * Copyright 2024 Baylibre SAS
+ *
+ * Limitations:
+ * - The writes to registers for period and duty are shadowed until
+ * LOAD_CONFIG is written to AXI_PWMGEN_REG_CONFIG at the end of the
+ * current period.
+ * - Writing LOAD_CONFIG also has the effect of re-synchronizing all
+ * enabled channels, which could cause glitching on other channels. It
+ * is therefore expected that channels are assigned harmonic periods
+ * and all have a single user coordinating this.
+ * - Supports normal polarity. Does not support changing polarity.
+ */
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#define AXI_PWMGEN_VERSION_MAJOR(x) (((x) >> 16) & 0xff)
+#define AXI_PWMGEN_VERSION_MINOR(x) (((x) >> 8) & 0xff)
+#define AXI_PWMGEN_VERSION_PATCH(x) ((x) & 0xff)
+
+#define AXI_PWMGEN_REG_CORE_VERSION 0x00
+#define AXI_PWMGEN_REG_ID 0x04
+#define AXI_PWMGEN_REG_SCRATCHPAD 0x08
+#define AXI_PWMGEN_REG_CORE_MAGIC 0x0C
+#define AXI_PWMGEN_REG_CONFIG 0x10
+#define AXI_PWMGEN_REG_NPWM 0x14
+#define AXI_PWMGEN_CHX_PERIOD(ch) (0x40 + (12 * (ch)))
+#define AXI_PWMGEN_CHX_DUTY(ch) (0x44 + (12 * (ch)))
+#define AXI_PWMGEN_CHX_OFFSET(ch) (0x48 + (12 * (ch)))
+#define AXI_PWMGEN_REG_CORE_MAGIC_VAL 0x601A3471 /* Identification number to test during setup */
+#define AXI_PWMGEN_LOAD_CONFIG BIT(1)
+#define AXI_PWMGEN_RESET BIT(0)
+
+struct axi_pwmgen_ddata {
+ struct pwm_chip chip;
+ struct regmap *regmap;
+ unsigned long clk_rate_hz;
+};
+
+static const struct regmap_config axi_pwmgen_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+};
+
+static struct axi_pwmgen_ddata *axi_pwmgen_from_chip(struct pwm_chip *chip)
+{
+ return container_of(chip, struct axi_pwmgen_ddata, chip);
+}
+
+static int axi_pwmgen_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct axi_pwmgen_ddata *ddata = axi_pwmgen_from_chip(chip);
+ unsigned int ch = pwm->hwpwm;
+ struct regmap *regmap = ddata->regmap;
+ u64 period_cnt, duty_cnt;
+ int ret;
+
+ if (state->polarity != PWM_POLARITY_NORMAL)
+ return -EINVAL;
+
+ if (state->enabled) {
+
+ period_cnt = mul_u64_u64_div_u64(state->period, ddata->clk_rate_hz, NSEC_PER_SEC);
+ if (period_cnt > UINT_MAX)
+ period_cnt = UINT_MAX;
+
+ if (period_cnt == 0)
+ return -EINVAL;
+
+ ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), period_cnt);
+ if (ret)
+ return ret;
+
+ duty_cnt = mul_u64_u64_div_u64(state->duty_cycle, ddata->clk_rate_hz, NSEC_PER_SEC);
+ if (duty_cnt > UINT_MAX)
+ duty_cnt = UINT_MAX;
+
+ ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), duty_cnt);
+ if (ret)
+ return ret;
+ } else {
+ ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), 0);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), 0);
+ if (ret)
+ return ret;
+ }
+
+ return regmap_write(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_LOAD_CONFIG);
+}
+
+static int axi_pwmgen_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct axi_pwmgen_ddata *ddata = axi_pwmgen_from_chip(chip);
+ struct regmap *regmap = ddata->regmap;
+ unsigned int ch = pwm->hwpwm;
+ u32 cnt;
+ int ret;
+
+ ret = regmap_read(regmap, AXI_PWMGEN_CHX_PERIOD(ch), &cnt);
+ if (ret)
+ return ret;
+
+ state->enabled = cnt != 0;
+
+ state->period = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz);
+
+ ret = regmap_read(regmap, AXI_PWMGEN_CHX_DUTY(ch), &cnt);
+ if (ret)
+ return ret;
+
+ state->duty_cycle = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz);
+
+ state->polarity = PWM_POLARITY_NORMAL;
+
+ return 0;
+}
+
+static const struct pwm_ops axi_pwmgen_pwm_ops = {
+ .apply = axi_pwmgen_apply,
+ .get_state = axi_pwmgen_get_state,
+};
+
+static int axi_pwmgen_setup(struct axi_pwmgen_ddata *ddata, struct device *dev)
+{
+ struct regmap *regmap = ddata->regmap;
+ int ret;
+ u32 val;
+
+ ret = regmap_read(regmap, AXI_PWMGEN_REG_CORE_MAGIC, &val);
+ if (ret)
+ return ret;
+
+ if (val != AXI_PWMGEN_REG_CORE_MAGIC_VAL)
+ return dev_err_probe(dev, -ENODEV,
+ "failed to read expected value from register: got %08x, expected %08x\n",
+ val,
+ AXI_PWMGEN_REG_CORE_MAGIC_VAL);
+
+ ret = regmap_read(regmap, AXI_PWMGEN_REG_CORE_VERSION, &val);
+ if (ret)
+ return ret;
+
+ if (AXI_PWMGEN_VERSION_MAJOR(val) != 1) {
+ return dev_err_probe(dev, -ENODEV, "Unsupported peripheral version %u.%u.%u\n",
+ AXI_PWMGEN_VERSION_MAJOR(val),
+ AXI_PWMGEN_VERSION_MINOR(val),
+ AXI_PWMGEN_VERSION_PATCH(val));
+ }
+
+ ret = regmap_read(regmap, AXI_PWMGEN_REG_NPWM, &ddata->chip.npwm);
+ if (ret)
+ return ret;
+
+ /* Enable the core */
+ return regmap_update_bits(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_RESET, 0);
+}
+
+static void axi_pwmgen_clk_rate_exclusive_put(void *data)
+{
+ clk_rate_exclusive_put(data);
+}
+
+static int axi_pwmgen_probe(struct platform_device *pdev)
+{
+ struct axi_pwmgen_ddata *ddata;
+ struct clk *clk;
+ void __iomem *io_base;
+ int ret;
+
+ ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
+ if (!ddata)
+ return -ENOMEM;
+
+ io_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(io_base))
+ return PTR_ERR(io_base);
+
+ ddata->regmap = devm_regmap_init_mmio(&pdev->dev, io_base, &axi_pwmgen_regmap_config);
+ if (IS_ERR(ddata->regmap))
+ return dev_err_probe(&pdev->dev, PTR_ERR(ddata->regmap),
+ "failed to init register map\n");
+
+ clk = devm_clk_get_enabled(&pdev->dev, NULL);
+ if (IS_ERR(clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(clk), "failed to get clock\n");
+
+ ret = clk_rate_exclusive_get(clk);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "failed to get exclusive rate\n");
+
+ ret = devm_add_action_or_reset(&pdev->dev, axi_pwmgen_clk_rate_exclusive_put, clk);
+ if (ret)
+ return ret;
+
+ ddata->clk_rate_hz = clk_get_rate(clk);
+ if (!ddata->clk_rate_hz || ddata->clk_rate_hz > NSEC_PER_SEC)
+ return dev_err_probe(&pdev->dev, -EINVAL,
+ "Invalid clock rate: %lu\n", ddata->clk_rate_hz);
+
+ ddata->chip.dev = &pdev->dev;
+ ddata->chip.ops = &axi_pwmgen_pwm_ops;
+ ddata->chip.atomic = true;
+
+ ret = axi_pwmgen_setup(ddata, &pdev->dev);
+ if (ret < 0)
+ return ret;
+
+ return devm_pwmchip_add(&pdev->dev, &ddata->chip);
+}
+
+static const struct of_device_id axi_pwmgen_ids[] = {
+ { .compatible = "adi,axi-pwmgen-1.00.a" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, axi_pwmgen_ids);
+
+static struct platform_driver axi_pwmgen_driver = {
+ .driver = {
+ .name = "axi-pwmgen",
+ .of_match_table = axi_pwmgen_ids,
+ },
+ .probe = axi_pwmgen_probe,
+};
+module_platform_driver(axi_pwmgen_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Sergiu Cuciurean <[email protected]>");
+MODULE_AUTHOR("Trevor Gamblin <[email protected]>");
+MODULE_DESCRIPTION("Driver for the Analog Devices AXI PWM generator");
--
2.43.0
On 23/01/2024 23:05, Trevor Gamblin wrote:
> From: Drew Fustini <[email protected]>
>
> Add Analog Devices AXI PWM generator.
>
> Link: https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
> Signed-off-by: Drew Fustini <[email protected]>
> Co-developed-by: Trevor Gamblin <[email protected]>
> Signed-off-by: Trevor Gamblin <[email protected]>
>
> ---
> v2 changes:
> * Address feedback for driver and device tree in v1:
> * Relocate "unevaluatedProperties" in device tree binding
> * Remove redundant "bindings for" in description
>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Tue, 2024-01-23 at 17:05 -0500, Trevor Gamblin wrote:
> From: Drew Fustini <[email protected]>
>
> Add support for the Analog Devices AXI PWM Generator. This device is an
> FPGA-implemented peripheral used as PWM signal generator and can be
> interfaced with AXI4. The register map of this peripheral makes it
> possible to configure the period and duty cycle of the output signal.
>
> Link: https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
> Co-developed-by: Sergiu Cuciurean <[email protected]>
> Signed-off-by: Sergiu Cuciurean <[email protected]>
> Co-developed-by: David Lechner <[email protected]>
> Signed-off-by: David Lechner <[email protected]>
> Signed-off-by: Drew Fustini <[email protected]>
> Co-developed-by: Trevor Gamblin <[email protected]>
> Signed-off-by: Trevor Gamblin <[email protected]>
>
> ---
One minor nitpick below (but no need to re-spin just for that).
Anyways, from a code point of view, LGTM:
Acked-by: Nuno Sa <[email protected]>
> v2 changes:
> * Address feedback for driver and device tree in v1:
> * Use more reasonable Kconfig approach
> * Use common prefixes for all functions
> * Rename axi_pwmgen struct to axi_pwmgen_ddata
> * Change use of "pwm" to "ddata"
> * Set and check state->polarity
> * Multiply safely with mul_u64_u64_div_u64()
> * Improve handling of max and zero periods
> * Error if clk_rate_hz > NSEC_PER_SEC
> * Add "Limitations" section at top of pwm-axi-pwmgen.c
> * Don't disable outputs by default
> * Remove unnecessary macros for period, duty, offset
> * Fix axi_pwmgen_ddata alignment
> * Don't artificially limit npwm to four
> * Use clk_rate_exclusive_get(), balance with clk_rate_exclusive_put()
> * Cache clk rate in axi_pwmgen_ddata
> * Don't assign pwm->chip.base, do assign pwm->chip.atomic
> * Remove redundant calls to clk_get_rate
> * Test contents of AXI_PWMGEN_REG_CORE_MAGIC instead of
> arbitrary AXI_PWMGEN_TEST_DATA in AXI_PWMGEN_REG_SCRATCHPAD
> * Remove redundant clk struct from axi_pwmgen_ddata
> * Add self as module author
> * Add major version check for IP core
>
> ---
> MAINTAINERS | 1 +
> drivers/pwm/Kconfig | 13 ++
> drivers/pwm/Makefile | 1 +
> drivers/pwm/pwm-axi-pwmgen.c | 246 +++++++++++++++++++++++++++++++++++
> 4 files changed, 261 insertions(+)
> create mode 100644 drivers/pwm/pwm-axi-pwmgen.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8a4ed5545680..2baa7a0a1c8c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3438,6 +3438,7 @@ L: [email protected]
> S: Supported
> W: https://ez.analog.com/linux-software-drivers
> F: Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml
> +F: drivers/pwm/pwm-axi-pwmgen.c
>
> AXXIA I2C CONTROLLER
> M: Krzysztof Adamski <[email protected]>
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index 4b956d661755..d44b0e86adee 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -98,6 +98,19 @@ config PWM_ATMEL_TCB
> To compile this driver as a module, choose M here: the module
> will be called pwm-atmel-tcb.
>
> +config PWM_AXI_PWMGEN
> + tristate "Analog Devices AXI PWM generator"
> + depends on MICROBLAZE || NIOS2 || ARCH_ZYNQ || ARCH_ZYNQMP ||
> ARCH_INTEL_SOCFPGA || COMPILE_TEST
> + select REGMAP_MMIO
> + help
> + This enables support for the Analog Devices AXI PWM generator.
> +
> + This is a configurable PWM generator with variable pulse width and
> + period.
> +
> + To compile this driver as a module, choose M here: the module will
> be
> + called pwm-axi-pwmgen.
> +
> config PWM_BCM_IPROC
> tristate "iProc PWM support"
> depends on ARCH_BCM_IPROC || COMPILE_TEST
> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> index c5ec9e168ee7..8322089954e9 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_PWM_APPLE) += pwm-apple.o
> obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
> obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
> obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
> +obj-$(CONFIG_PWM_AXI_PWMGEN) += pwm-axi-pwmgen.o
> obj-$(CONFIG_PWM_BCM_IPROC) += pwm-bcm-iproc.o
> obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o
> obj-$(CONFIG_PWM_BCM2835) += pwm-bcm2835.o
> diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c
> new file mode 100644
> index 000000000000..39d2c7be0cb4
> --- /dev/null
> +++ b/drivers/pwm/pwm-axi-pwmgen.c
> @@ -0,0 +1,246 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Analog Devices AXI PWM generator
> + *
> + * Copyright 2024 Analog Devices Inc.
> + * Copyright 2024 Baylibre SAS
> + *
> + * Limitations:
> + * - The writes to registers for period and duty are shadowed until
> + * LOAD_CONFIG is written to AXI_PWMGEN_REG_CONFIG at the end of the
> + * current period.
> + * - Writing LOAD_CONFIG also has the effect of re-synchronizing all
> + * enabled channels, which could cause glitching on other channels. It
> + * is therefore expected that channels are assigned harmonic periods
> + * and all have a single user coordinating this.
> + * - Supports normal polarity. Does not support changing polarity.
> + */
> +#include <linux/bits.h>
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/pwm.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +
> +#define AXI_PWMGEN_VERSION_MAJOR(x) (((x) >> 16) & 0xff)
> +#define AXI_PWMGEN_VERSION_MINOR(x) (((x) >> 8) & 0xff)
> +#define AXI_PWMGEN_VERSION_PATCH(x) ((x) & 0xff)
> +
> +#define AXI_PWMGEN_REG_CORE_VERSION 0x00
> +#define AXI_PWMGEN_REG_ID 0x04
> +#define AXI_PWMGEN_REG_SCRATCHPAD 0x08
> +#define AXI_PWMGEN_REG_CORE_MAGIC 0x0C
> +#define AXI_PWMGEN_REG_CONFIG 0x10
> +#define AXI_PWMGEN_REG_NPWM 0x14
> +#define AXI_PWMGEN_CHX_PERIOD(ch) (0x40 + (12 * (ch)))
> +#define AXI_PWMGEN_CHX_DUTY(ch) (0x44 + (12 * (ch)))
> +#define AXI_PWMGEN_CHX_OFFSET(ch) (0x48 + (12 * (ch)))
> +#define AXI_PWMGEN_REG_CORE_MAGIC_VAL 0x601A3471 /* Identification number
> to test during setup */
> +#define AXI_PWMGEN_LOAD_CONFIG BIT(1)
> +#define AXI_PWMGEN_RESET BIT(0)
> +
> +struct axi_pwmgen_ddata {
> + struct pwm_chip chip;
> + struct regmap *regmap;
> + unsigned long clk_rate_hz;
> +};
> +
> +static const struct regmap_config axi_pwmgen_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> +};
> +
> +static struct axi_pwmgen_ddata *axi_pwmgen_from_chip(struct pwm_chip *chip)
> +{
> + return container_of(chip, struct axi_pwmgen_ddata, chip);
> +}
> +
> +static int axi_pwmgen_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> + const struct pwm_state *state)
> +{
> + struct axi_pwmgen_ddata *ddata = axi_pwmgen_from_chip(chip);
> + unsigned int ch = pwm->hwpwm;
> + struct regmap *regmap = ddata->regmap;
> + u64 period_cnt, duty_cnt;
> + int ret;
> +
> + if (state->polarity != PWM_POLARITY_NORMAL)
> + return -EINVAL;
> +
> + if (state->enabled) {
> +
no need for extra line in here... at the very least, you should be coherent in
both your code paths...
- Nuno Sá
On Tue, 2024-01-23 at 17:05 -0500, Trevor Gamblin wrote:
> From: Drew Fustini <[email protected]>
>
> Add support for the Analog Devices AXI PWM Generator. This device is an
> FPGA-implemented peripheral used as PWM signal generator and can be
> interfaced with AXI4. The register map of this peripheral makes it
> possible to configure the period and duty cycle of the output signal.
>
> Link: https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen
> Co-developed-by: Sergiu Cuciurean <[email protected]>
> Signed-off-by: Sergiu Cuciurean <[email protected]>
> Co-developed-by: David Lechner <[email protected]>
> Signed-off-by: David Lechner <[email protected]>
> Signed-off-by: Drew Fustini <[email protected]>
> Co-developed-by: Trevor Gamblin <[email protected]>
> Signed-off-by: Trevor Gamblin <[email protected]>
>
> ---
> v2 changes:
> * Address feedback for driver and device tree in v1:
> * Use more reasonable Kconfig approach
> * Use common prefixes for all functions
> * Rename axi_pwmgen struct to axi_pwmgen_ddata
> * Change use of "pwm" to "ddata"
> * Set and check state->polarity
> * Multiply safely with mul_u64_u64_div_u64()
> * Improve handling of max and zero periods
> * Error if clk_rate_hz > NSEC_PER_SEC
> * Add "Limitations" section at top of pwm-axi-pwmgen.c
> * Don't disable outputs by default
> * Remove unnecessary macros for period, duty, offset
> * Fix axi_pwmgen_ddata alignment
> * Don't artificially limit npwm to four
> * Use clk_rate_exclusive_get(), balance with clk_rate_exclusive_put()
> * Cache clk rate in axi_pwmgen_ddata
> * Don't assign pwm->chip.base, do assign pwm->chip.atomic
> * Remove redundant calls to clk_get_rate
> * Test contents of AXI_PWMGEN_REG_CORE_MAGIC instead of
> arbitrary AXI_PWMGEN_TEST_DATA in AXI_PWMGEN_REG_SCRATCHPAD
> * Remove redundant clk struct from axi_pwmgen_ddata
> * Add self as module author
> * Add major version check for IP core
>
> ---
> MAINTAINERS | 1 +
> drivers/pwm/Kconfig | 13 ++
> drivers/pwm/Makefile | 1 +
> drivers/pwm/pwm-axi-pwmgen.c | 246 +++++++++++++++++++++++++++++++++++
> 4 files changed, 261 insertions(+)
> create mode 100644 drivers/pwm/pwm-axi-pwmgen.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8a4ed5545680..2baa7a0a1c8c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3438,6 +3438,7 @@ L: [email protected]
> S: Supported
> W: https://ez.analog.com/linux-software-drivers
> F: Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml
> +F: drivers/pwm/pwm-axi-pwmgen.c
>
> AXXIA I2C CONTROLLER
> M: Krzysztof Adamski <[email protected]>
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index 4b956d661755..d44b0e86adee 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -98,6 +98,19 @@ config PWM_ATMEL_TCB
> To compile this driver as a module, choose M here: the module
> will be called pwm-atmel-tcb.
>
> +config PWM_AXI_PWMGEN
> + tristate "Analog Devices AXI PWM generator"
> + depends on MICROBLAZE || NIOS2 || ARCH_ZYNQ || ARCH_ZYNQMP ||
> ARCH_INTEL_SOCFPGA || COMPILE_TEST
> + select REGMAP_MMIO
> + help
> + This enables support for the Analog Devices AXI PWM generator.
> +
> + This is a configurable PWM generator with variable pulse width and
> + period.
> +
> + To compile this driver as a module, choose M here: the module will
> be
> + called pwm-axi-pwmgen.
> +
> config PWM_BCM_IPROC
> tristate "iProc PWM support"
> depends on ARCH_BCM_IPROC || COMPILE_TEST
> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> index c5ec9e168ee7..8322089954e9 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_PWM_APPLE) += pwm-apple.o
> obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
> obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
> obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
> +obj-$(CONFIG_PWM_AXI_PWMGEN) += pwm-axi-pwmgen.o
> obj-$(CONFIG_PWM_BCM_IPROC) += pwm-bcm-iproc.o
> obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o
> obj-$(CONFIG_PWM_BCM2835) += pwm-bcm2835.o
> diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c
> new file mode 100644
> index 000000000000..39d2c7be0cb4
> --- /dev/null
> +++ b/drivers/pwm/pwm-axi-pwmgen.c
> @@ -0,0 +1,246 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Analog Devices AXI PWM generator
> + *
> + * Copyright 2024 Analog Devices Inc.
> + * Copyright 2024 Baylibre SAS
> + *
> + * Limitations:
> + * - The writes to registers for period and duty are shadowed until
> + * LOAD_CONFIG is written to AXI_PWMGEN_REG_CONFIG at the end of the
> + * current period.
> + * - Writing LOAD_CONFIG also has the effect of re-synchronizing all
> + * enabled channels, which could cause glitching on other channels. It
> + * is therefore expected that channels are assigned harmonic periods
> + * and all have a single user coordinating this.
> + * - Supports normal polarity. Does not support changing polarity.
> + */
> +#include <linux/bits.h>
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/pwm.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +
> +#define AXI_PWMGEN_VERSION_MAJOR(x) (((x) >> 16) & 0xff)
> +#define AXI_PWMGEN_VERSION_MINOR(x) (((x) >> 8) & 0xff)
> +#define AXI_PWMGEN_VERSION_PATCH(x) ((x) & 0xff)
> +
> +#define AXI_PWMGEN_REG_CORE_VERSION 0x00
Hi Trevor,
Just realized now that you should be using the macros already defined in
<linux/fpga/adi-axi-common.h>
- Nuno Sá