Hello Linus,
The OpenRISC work is a bit more interesting this time, adding SMP support and a
few general cleanups. Please consider for pull,
The following changes since commit bb176f67090ca54869fc1262c913aa69d2ede070:
Linux 4.14-rc6 (2017-10-23 06:49:47 -0400)
are available in the git repository at:
git://github.com/openrisc/linux.git tags/for-linus
for you to fetch changes up to 610f01b9a88a9ef8b506709a825c17395c56a62a:
openrisc: fix possible deadlock scenario during timer sync (2017-11-03 14:01:17 +0900)
----------------------------------------------------------------
OpenRISC updates for v4.15
Small Things:
- Move OpenRISC docs into Documentation and clean them up
- Document previously undocumented devicetree bindings
- Update the or1ksim dts to use stdout-path
OpenRISC SMP support details:
- First the "use shadow registers" patch get's the architecture ready for SMP.
- The "add 1 and 2 byte cmpxchg support" and "use qspinlocks and
qrwlocks" add the SMP locking infrastructure as needed. Using the
qspinlocks and qrwlocks as suggested by Peter Z while reviewing the
original spinlocks implementation.
- The "support for ompic" adds a new irqchip device which is used for
IPI communication to support SMP.
- The "initial SMP support" adds smp.c and makes changes to all of the
necessary data-structures to be per-cpu.
- The remaining patches are bug fixes and debug helpers which I wanted
to keep separate from the "initial SMP support" in order to allow them
to be reviewed on their own. This includes:
- add cacheflush support to fix icache aliasing
- fix initial preempt state for secondary cpu tasks
- sleep instead of spin on secondary wait
- support framepointers and STACKTRACE_SUPPORT
- enable LOCKDEP_SUPPORT and irqflags tracing
- timer sync: Add tick timer sync logic
- fix possible deadlock in timer sync, pointed out by mips guys
Note: the irqchip patch was reviewed with Marc and we agreed to push it
together with these patches.
----------------------------------------------------------------
Jan Henrik Weinstock (1):
openrisc: add cacheflush support to fix icache aliasing
Luc Van Oostenryck (1):
openrisc: pass endianness info to sparse
Stafford Horne (15):
openrisc: dts: or1ksim: Add stdout-path
MAINTAINERS: Add OpenRISC pic maintainer
Documentation: Move OpenRISC docs out of arch/
Documentation: openrisc: Updates to README
dt-bindings: openrisc: Add OpenRISC platform SoC
openrisc: add 1 and 2 byte cmpxchg support
openrisc: use qspinlocks and qrwlocks
dt-bindings: add openrisc to vendor prefixes list
irqchip: add initial support for ompic
openrisc: fix initial preempt state for secondary cpu tasks
openrisc: sleep instead of spin on secondary wait
openrisc: support framepointers and STACKTRACE_SUPPORT
openrisc: enable LOCKDEP_SUPPORT and irqflags tracing
openrisc: add tick timer multi-core sync logic
openrisc: fix possible deadlock scenario during timer sync
Stefan Kristiansson (3):
openrisc: use shadow registers to save regs on exception
openrisc: initial SMP support
openrisc: add simple_smp dts and defconfig for simulators
.../interrupt-controller/openrisc,ompic.txt | 22 ++
.../bindings/openrisc/opencores/or1ksim.txt | 39 ++++
.../devicetree/bindings/vendor-prefixes.txt | 1 +
.../openrisc/README | 65 +++---
.../TODO.openrisc => Documentation/openrisc/TODO | 0
MAINTAINERS | 4 +
arch/openrisc/Kconfig | 49 +++-
arch/openrisc/Makefile | 1 +
arch/openrisc/boot/dts/or1ksim.dts | 7 +-
arch/openrisc/boot/dts/simple_smp.dts | 63 +++++
arch/openrisc/configs/simple_smp_defconfig | 66 ++++++
arch/openrisc/include/asm/Kbuild | 5 +-
arch/openrisc/include/asm/cacheflush.h | 96 ++++++++
arch/openrisc/include/asm/cmpxchg.h | 147 +++++++++---
arch/openrisc/include/asm/cpuinfo.h | 7 +-
arch/openrisc/include/asm/mmu_context.h | 2 +-
arch/openrisc/include/asm/pgtable.h | 18 +-
arch/openrisc/include/asm/serial.h | 2 +-
arch/openrisc/include/asm/smp.h | 26 +++
arch/openrisc/include/asm/spinlock.h | 12 +-
arch/openrisc/include/asm/spinlock_types.h | 7 +
arch/openrisc/include/asm/spr_defs.h | 14 ++
arch/openrisc/include/asm/thread_info.h | 2 +-
arch/openrisc/include/asm/time.h | 23 ++
arch/openrisc/include/asm/tlbflush.h | 25 +-
arch/openrisc/include/asm/unwinder.h | 20 ++
arch/openrisc/kernel/Makefile | 4 +-
arch/openrisc/kernel/dma.c | 14 +-
arch/openrisc/kernel/entry.S | 74 +++++-
arch/openrisc/kernel/head.S | 239 ++++++++++++++++---
arch/openrisc/kernel/setup.c | 165 ++++++++-----
arch/openrisc/kernel/smp.c | 259 +++++++++++++++++++++
arch/openrisc/kernel/stacktrace.c | 86 +++++++
arch/openrisc/kernel/sync-timer.c | 120 ++++++++++
arch/openrisc/kernel/time.c | 66 ++++--
arch/openrisc/kernel/traps.c | 54 +----
arch/openrisc/kernel/unwinder.c | 105 +++++++++
arch/openrisc/lib/delay.c | 2 +-
arch/openrisc/mm/Makefile | 2 +-
arch/openrisc/mm/cache.c | 61 +++++
arch/openrisc/mm/fault.c | 4 +-
arch/openrisc/mm/init.c | 2 +-
arch/openrisc/mm/tlb.c | 16 +-
drivers/irqchip/Kconfig | 3 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-ompic.c | 202 ++++++++++++++++
46 files changed, 1940 insertions(+), 262 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
create mode 100644 Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt
rename arch/openrisc/README.openrisc => Documentation/openrisc/README (56%)
rename arch/openrisc/TODO.openrisc => Documentation/openrisc/TODO (100%)
create mode 100644 arch/openrisc/boot/dts/simple_smp.dts
create mode 100644 arch/openrisc/configs/simple_smp_defconfig
create mode 100644 arch/openrisc/include/asm/cacheflush.h
create mode 100644 arch/openrisc/include/asm/smp.h
create mode 100644 arch/openrisc/include/asm/spinlock_types.h
create mode 100644 arch/openrisc/include/asm/time.h
create mode 100644 arch/openrisc/include/asm/unwinder.h
create mode 100644 arch/openrisc/kernel/smp.c
create mode 100644 arch/openrisc/kernel/stacktrace.c
create mode 100644 arch/openrisc/kernel/sync-timer.c
create mode 100644 arch/openrisc/kernel/unwinder.c
create mode 100644 arch/openrisc/mm/cache.c
create mode 100644 drivers/irqchip/irq-ompic.c
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