Add SCMI reset numbers according to the Blaize BLZP1600 SoC
hardware specifications.
Reviewed-by: James Cowgill <[email protected]>
Reviewed-by: Matt Redfearn <[email protected]>
Reviewed-by: Neil Jones <[email protected]>
Signed-off-by: Nikolaos Pasaloukos <[email protected]>
---
.../dt-bindings/reset/blaize,blzp1600-reset.h | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 include/dt-bindings/reset/blaize,blzp1600-reset.h
diff --git a/include/dt-bindings/reset/blaize,blzp1600-reset.h b/include/dt-bindings/reset/blaize,blzp1600-reset.h
new file mode 100644
index 000000000000..c500c2b0690c
--- /dev/null
+++ b/include/dt-bindings/reset/blaize,blzp1600-reset.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) 2023, Blaize, Inc.
+ */
+
+#ifndef DT_BINDING_RESET_BLZP1600_H
+#define DT_BINDING_RESET_BLZP1600_H
+
+/* ARM SCMI resets */
+
+/* BLZP1600 reset numbers as defined in the hardware architecture */
+
+#define BLZP1600_A53_C0_HARD_RST 0
+#define BLZP1600_A53_C0_SOFT_RST 1
+#define BLZP1600_A53_C1_HARD_RST 2
+#define BLZP1600_A53_C1_SOFT_RST 3
+#define BLZP1600_A53_L2_CACHE_RST 4
+#define BLZP1600_A53_DBG_RST 5
+#define BLZP1600_GIC_RST 6
+#define BLZP1600_CRYPTO_RST 7
+/* reset 8 invalid */
+#define BLZP1600_GSP_RST 9
+#define BLZP1600_DRAM_A_SYS_RST 10
+#define BLZP1600_DRAM_A_DDRC_RST 11
+#define BLZP1600_DRAM_A_PRST 12
+#define BLZP1600_DRAM_A_ARST 13
+#define BLZP1600_DRAM_A_PHY_RST 14
+#define BLZP1600_DRAM_A_PWRON_RST 15
+#define BLZP1600_DRAM_A_PHY_PRST 16
+#define BLZP1600_DRAM_B_SYS_RST 17
+#define BLZP1600_DRAM_B_DDRC_RST 18
+#define BLZP1600_DRAM_B_PRST 19
+#define BLZP1600_DRAM_B_ARST 20
+#define BLZP1600_DRAM_B_PHY_RST 21
+#define BLZP1600_DRAM_B_PWRON_RST 22
+#define BLZP1600_DRAM_B_PHY_PRST 23
+#define BLZP1600_USB_RST 24
+#define BLZP1600_USB_PHY_RST 25
+#define BLZP1600_CAN0_RST 26
+#define BLZP1600_CAN1_RST 27
+#define BLZP1600_CAN2_RST 28
+#define BLZP1600_ETH_MAC_RST 29
+#define BLZP1600_SDIO0_RST 30
+#define BLZP1600_SDIO1_RST 31
+#define BLZP1600_SDIO2_RST 32
+/* reset 33 invalid */
+#define BLZP1600_SD_CARD_RST 34
+#define BLZP1600_CSI0_CTRL_RST 35
+#define BLZP1600_CSI0_VDMA_RST 36
+#define BLZP1600_CSI1_CTRL_RST 37
+#define BLZP1600_CSI1_VDMA_RST 38
+#define BLZP1600_CSI2_CTRL_RST 39
+#define BLZP1600_CSI2_VDMA_RST 40
+#define BLZP1600_CSI3_CTRL_RST 41
+#define BLZP1600_CSI3_VDMA_RST 42
+#define BLZP1600_CSID_CTRL_RST 43
+#define BLZP1600_CSID_VDMA_RST 44
+#define BLZP1600_DSI_CTRL_RST 45
+#define BLZP1600_DSI_VDMA_RST 46
+/* resets 47-48 invalid */
+#define BLZP1600_DMA_RST 49
+#define BLZP1600_QSPI_PRST 50
+#define BLZP1600_QSPI_RST 51
+#define BLZP1600_I2S_TX_RST 52
+#define BLZP1600_I2S_RX_RST 53
+#define BLZP1600_I2C0_RST 54
+#define BLZP1600_I2C1_RST 55
+#define BLZP1600_I2C2_RST 56
+#define BLZP1600_I2C3_RST 57
+#define BLZP1600_I2C4_RST 58
+#define BLZP1600_UART0_RST 59
+#define BLZP1600_UART1_RST 60
+#define BLZP1600_SPIS_PRST 61
+#define BLZP1600_SPIS_RST 62
+#define BLZP1600_TIMER_RST 63
+#define BLZP1600_TSENSOR_RST 64
+#define BLZP1600_VIDEO_E_RST 65
+#define BLZP1600_VIDEO_E_REORDER_RST 66
+/* reset 67 invalid */
+#define BLZP1600_VIDEO_D_RST 68
+#define BLZP1600_VIDEO_D_REORDER_RST 69
+#define BLZP1600_VIDEO_D_L2_RST 70
+
+#endif
--
2.34.1
On 24/04/2024 15:32, Niko Pasaloukos wrote:
> Add SCMI reset numbers according to the Blaize BLZP1600 SoC
> hardware specifications.
>
> Reviewed-by: James Cowgill <[email protected]>
> Reviewed-by: Matt Redfearn <[email protected]>
> Reviewed-by: Neil Jones <[email protected]>
> Signed-off-by: Nikolaos Pasaloukos <[email protected]>
> ---
> .../dt-bindings/reset/blaize,blzp1600-reset.h | 84 +++++++++++++++++++
> 1 file changed, 84 insertions(+)
> create mode 100644 include/dt-bindings/reset/blaize,blzp1600-reset.h
This goes with patch adding the binding doc.
>
> diff --git a/include/dt-bindings/reset/blaize,blzp1600-reset.h b/include/dt-bindings/reset/blaize,blzp1600-reset.h
> new file mode 100644
> index 000000000000..c500c2b0690c
> --- /dev/null
> +++ b/include/dt-bindings/reset/blaize,blzp1600-reset.h
> @@ -0,0 +1,84 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> +/*
> + * Copyright (C) 2023, Blaize, Inc.
> + */
> +
> +#ifndef DT_BINDING_RESET_BLZP1600_H
> +#define DT_BINDING_RESET_BLZP1600_H
> +
> +/* ARM SCMI resets */
> +
> +/* BLZP1600 reset numbers as defined in the hardware architecture */
> +
> +#define BLZP1600_A53_C0_HARD_RST 0
> +#define BLZP1600_A53_C0_SOFT_RST 1
> +#define BLZP1600_A53_C1_HARD_RST 2
> +#define BLZP1600_A53_C1_SOFT_RST 3
> +#define BLZP1600_A53_L2_CACHE_RST 4
> +#define BLZP1600_A53_DBG_RST 5
> +#define BLZP1600_GIC_RST 6
> +#define BLZP1600_CRYPTO_RST 7
> +/* reset 8 invalid */
Same concerns.
However another problem is lack of users of it. Your patchset looks
random - this goes to subsustem, but there is no device binding, no
driver, no DTS. Could be result of lack of threading. :/
Best regards,
Krzysztof
On 24/04/2024 16:16, Krzysztof Kozlowski wrote:
>> +
>> +/* BLZP1600 reset numbers as defined in the hardware architecture */
>> +
>> +#define BLZP1600_A53_C0_HARD_RST 0
>> +#define BLZP1600_A53_C0_SOFT_RST 1
>> +#define BLZP1600_A53_C1_HARD_RST 2
>> +#define BLZP1600_A53_C1_SOFT_RST 3
>> +#define BLZP1600_A53_L2_CACHE_RST 4
>> +#define BLZP1600_A53_DBG_RST 5
>> +#define BLZP1600_GIC_RST 6
>> +#define BLZP1600_CRYPTO_RST 7
>> +/* reset 8 invalid */
>
> Same concerns.
>
> However another problem is lack of users of it. Your patchset looks
> random - this goes to subsustem, but there is no device binding, no
> driver, no DTS. Could be result of lack of threading. :/
And now I see my reply at v1 saying that these gaps are unexpected.
Please respond to reviewers comments either acknowledging the comment or
responding with feedback. What are these header constants representing?
Best regards,
Krzysztof