Hi all,
This series fixed various problems I meet when I was trying to
boot kernel on my Loongson-2K PI2 system.
Although most of the series are taged for stable, please apply
it to mips-next tree as it has dependency to commits in next
and I'm not in rush to get them into linus tree. I have some
future works planed based on this series that may get into this
cycle.
Thanks
- Jiaxun
Signed-off-by: Jiaxun Yang <[email protected]>
---
Jiaxun Yang (10):
MIPS: Loongson64: Remove memory node for builtin-dtb
MIPS: dts: loongson: Fix liointc IRQ polarity
MIPS: dts: loongson: Fix ls2k1000-rtc interrupt
MIPS: dts: loongson: Fix GMAC phy node
MIPS: dts: loongson: Add ISA node
MIPS: Loongson64: Test register availability before use
platform: mips: cpu_hwmon: Disable driver on unsupported hardware
MIPS: Loongson64: reset: Prioritise firmware service
MIPS: Loongson64: sleeper: Pass ra and sp as arguments
MIPS: Loongson64: env: Hook up Loongsson-2K
arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi | 65 +++++++++++-----------
arch/mips/include/asm/mach-loongson64/boot_param.h | 2 +
arch/mips/loongson64/env.c | 8 +++
arch/mips/loongson64/reset.c | 38 ++++++-------
arch/mips/loongson64/sleeper.S | 8 ++-
arch/mips/loongson64/smp.c | 23 +++++++-
drivers/platform/mips/cpu_hwmon.c | 3 +
7 files changed, 89 insertions(+), 58 deletions(-)
---
base-commit: 6906a84c482f098d31486df8dc98cead21cce2d0
change-id: 20240613-ls3k-mips-52eb3fb3e917
Best regards,
--
Jiaxun Yang <[email protected]>
ISA node is required by Loongson64 platforms to initialize
PIO support.
Kernel will hang at boot without ISA node.
Cc: [email protected]
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
index b2f66f6bb2fe..cc7747c5f21f 100644
--- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
+++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
@@ -44,6 +44,13 @@ package0: bus@10000000 {
0 0x40000000 0 0x40000000 0 0x40000000
0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
+ isa@18000000 {
+ compatible = "isa";
+ #size-cells = <1>;
+ #address-cells = <2>;
+ ranges = <1 0x0 0x0 0x18000000 0x4000>;
+ };
+
pm: reset-controller@1fe07000 {
compatible = "loongson,ls2k-pm";
reg = <0 0x1fe07000 0 0x422>;
--
2.43.0
Builtin DTBS should never contain memory node as memory is
going to be managed by LEFI interface.
Remove memory node to prevent confliction.
Fixes: b1a792601f26 ("MIPS: Loongson64: DeviceTree for Loongson-2K1000")
Cc: [email protected]
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi | 8 --------
1 file changed, 8 deletions(-)
diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
index b5593f7cc383..f5a74338bf05 100644
--- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
+++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
@@ -23,14 +23,6 @@ cpu0: cpu@0 {
};
};
- memory@200000 {
- compatible = "memory";
- device_type = "memory";
- reg = <0x00000000 0x00200000 0x00000000 0x0ee00000>, /* 238 MB at 2 MB */
- <0x00000000 0x20000000 0x00000000 0x1f000000>, /* 496 MB at 512 MB */
- <0x00000001 0x10000000 0x00000001 0xb0000000>; /* 6912 MB at 4352MB */
- };
-
cpu_clk: cpu_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
--
2.43.0
All internal liointc interrupts are high level triggered.
Fixes: b1a792601f26 ("MIPS: Loongson64: DeviceTree for Loongson-2K1000")
Cc: [email protected]
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi | 42 +++++++++++-----------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
index f5a74338bf05..3f5255584c30 100644
--- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
+++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
@@ -93,7 +93,7 @@ rtc0: rtc@1fe07800 {
compatible = "loongson,ls2k1000-rtc";
reg = <0 0x1fe07800 0 0x78>;
interrupt-parent = <&liointc0>;
- interrupts = <60 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
};
uart0: serial@1fe00000 {
@@ -101,7 +101,7 @@ uart0: serial@1fe00000 {
reg = <0 0x1fe00000 0 0x8>;
clock-frequency = <125000000>;
interrupt-parent = <&liointc0>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
no-loopback-test;
};
@@ -124,8 +124,8 @@ gmac@3,0 {
"pciclass0c03";
reg = <0x1800 0x0 0x0 0x0 0x0>;
- interrupts = <12 IRQ_TYPE_LEVEL_LOW>,
- <13 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
+ <13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&liointc0>;
phy-mode = "rgmii";
@@ -147,8 +147,8 @@ gmac@3,1 {
"loongson, pci-gmac";
reg = <0x1900 0x0 0x0 0x0 0x0>;
- interrupts = <14 IRQ_TYPE_LEVEL_LOW>,
- <15 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&liointc0>;
phy-mode = "rgmii";
@@ -169,7 +169,7 @@ ehci@4,1 {
"pciclass0c03";
reg = <0x2100 0x0 0x0 0x0 0x0>;
- interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc1>;
};
@@ -180,7 +180,7 @@ ohci@4,2 {
"pciclass0c03";
reg = <0x2200 0x0 0x0 0x0 0x0>;
- interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc1>;
};
@@ -191,7 +191,7 @@ sata@8,0 {
"pciclass0106";
reg = <0x4000 0x0 0x0 0x0 0x0>;
- interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc0>;
};
@@ -206,10 +206,10 @@ pcie@9,0 {
#size-cells = <2>;
device_type = "pci";
#interrupt-cells = <1>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_HIGH>;
ranges;
external-facing;
};
@@ -225,10 +225,10 @@ pcie@a,0 {
#size-cells = <2>;
device_type = "pci";
#interrupt-cells = <1>;
- interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_HIGH>;
ranges;
external-facing;
};
@@ -244,10 +244,10 @@ pcie@b,0 {
#size-cells = <2>;
device_type = "pci";
#interrupt-cells = <1>;
- interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_HIGH>;
ranges;
external-facing;
};
@@ -263,10 +263,10 @@ pcie@c,0 {
#size-cells = <2>;
device_type = "pci";
#interrupt-cells = <1>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_HIGH>;
ranges;
external-facing;
};
@@ -282,10 +282,10 @@ pcie@d,0 {
#size-cells = <2>;
device_type = "pci";
#interrupt-cells = <1>;
- interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_HIGH>;
ranges;
external-facing;
};
@@ -301,10 +301,10 @@ pcie@e,0 {
#size-cells = <2>;
device_type = "pci";
#interrupt-cells = <1>;
- interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&liointc1>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_HIGH>;
ranges;
external-facing;
};
--
2.43.0
We should always use firmware's poweroff & reboot service
if it's available as firmware may need to perform more task
than platform's syscon etc.
However _machine_restart & poweroff hooks are registered at
low priority, which means platform reboot driver can override
them.
Register firmware based reboot/poweroff implementation with
register_sys_off_handler with appropriate priority so that
they will be prioritised. Remove _machine_halt hook as it's
deemed to be unnecessary.
Cc: [email protected]
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/loongson64/reset.c | 38 ++++++++++++++++----------------------
1 file changed, 16 insertions(+), 22 deletions(-)
diff --git a/arch/mips/loongson64/reset.c b/arch/mips/loongson64/reset.c
index e01c8d4a805a..3e20ade0503a 100644
--- a/arch/mips/loongson64/reset.c
+++ b/arch/mips/loongson64/reset.c
@@ -11,6 +11,7 @@
#include <linux/init.h>
#include <linux/kexec.h>
#include <linux/pm.h>
+#include <linux/reboot.h>
#include <linux/slab.h>
#include <asm/bootinfo.h>
@@ -21,36 +22,21 @@
#include <loongson.h>
#include <boot_param.h>
-static void loongson_restart(char *command)
+static int firmware_restart(struct sys_off_data *unusedd)
{
void (*fw_restart)(void) = (void *)loongson_sysconf.restart_addr;
fw_restart();
- while (1) {
- if (cpu_wait)
- cpu_wait();
- }
+ return NOTIFY_DONE;
}
-static void loongson_poweroff(void)
+static int firmware_poweroff(struct sys_off_data *unused)
{
void (*fw_poweroff)(void) = (void *)loongson_sysconf.poweroff_addr;
fw_poweroff();
- while (1) {
- if (cpu_wait)
- cpu_wait();
- }
-}
-
-static void loongson_halt(void)
-{
- pr_notice("\n\n** You can safely turn off the power now **\n\n");
- while (1) {
- if (cpu_wait)
- cpu_wait();
- }
+ return NOTIFY_DONE;
}
#ifdef CONFIG_KEXEC_CORE
@@ -154,9 +140,17 @@ static void loongson_crash_shutdown(struct pt_regs *regs)
static int __init mips_reboot_setup(void)
{
- _machine_restart = loongson_restart;
- _machine_halt = loongson_halt;
- pm_power_off = loongson_poweroff;
+ if (loongson_sysconf.restart_addr) {
+ register_sys_off_handler(SYS_OFF_MODE_RESTART,
+ SYS_OFF_PRIO_FIRMWARE,
+ firmware_restart, NULL);
+ }
+
+ if (loongson_sysconf.poweroff_addr) {
+ register_sys_off_handler(SYS_OFF_MODE_POWER_OFF,
+ SYS_OFF_PRIO_FIRMWARE,
+ firmware_poweroff, NULL);
+ }
#ifdef CONFIG_KEXEC_CORE
kexec_argv = kmalloc(KEXEC_ARGV_SIZE, GFP_KERNEL);
--
2.43.0
Somehow those enablement bits were left over when we were
adding initial Loongson-2K support.
Set up basic information and select proper builtin DTB for
Loongson-2K.
Cc: [email protected]
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/include/asm/mach-loongson64/boot_param.h | 2 ++
arch/mips/loongson64/env.c | 8 ++++++++
2 files changed, 10 insertions(+)
diff --git a/arch/mips/include/asm/mach-loongson64/boot_param.h b/arch/mips/include/asm/mach-loongson64/boot_param.h
index e007edd6b60a..9218b3ae3383 100644
--- a/arch/mips/include/asm/mach-loongson64/boot_param.h
+++ b/arch/mips/include/asm/mach-loongson64/boot_param.h
@@ -42,12 +42,14 @@ enum loongson_cpu_type {
Legacy_1B = 0x5,
Legacy_2G = 0x6,
Legacy_2H = 0x7,
+ Legacy_2K = 0x8,
Loongson_1A = 0x100,
Loongson_1B = 0x101,
Loongson_2E = 0x200,
Loongson_2F = 0x201,
Loongson_2G = 0x202,
Loongson_2H = 0x203,
+ Loongson_2K = 0x204,
Loongson_3A = 0x300,
Loongson_3B = 0x301
};
diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c
index ef3750a6ffac..09ff05269861 100644
--- a/arch/mips/loongson64/env.c
+++ b/arch/mips/loongson64/env.c
@@ -88,6 +88,12 @@ void __init prom_lefi_init_env(void)
cpu_clock_freq = ecpu->cpu_clock_freq;
loongson_sysconf.cputype = ecpu->cputype;
switch (ecpu->cputype) {
+ case Legacy_2K:
+ case Loongson_2K:
+ smp_group[0] = 0x900000001fe11000;
+ loongson_sysconf.cores_per_node = 2;
+ loongson_sysconf.cores_per_package = 2;
+ break;
case Legacy_3A:
case Loongson_3A:
loongson_sysconf.cores_per_node = 4;
@@ -221,6 +227,8 @@ void __init prom_lefi_init_env(void)
default:
break;
}
+ } else if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R) {
+ loongson_fdt_blob = __dtb_loongson64_2core_2k1000_begin;
} else if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G) {
if (loongson_sysconf.bridgetype == LS7A)
loongson_fdt_blob = __dtb_loongson64g_4core_ls7a_begin;
--
2.43.0
cpu_hwmon is unsupported on CPUs without loongson_chiptemp
register and csr.
Cc: [email protected]
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/platform/mips/cpu_hwmon.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/platform/mips/cpu_hwmon.c b/drivers/platform/mips/cpu_hwmon.c
index d8c5f9195f85..2ac2f31090f9 100644
--- a/drivers/platform/mips/cpu_hwmon.c
+++ b/drivers/platform/mips/cpu_hwmon.c
@@ -139,6 +139,9 @@ static int __init loongson_hwmon_init(void)
csr_temp_enable = csr_readl(LOONGSON_CSR_FEATURES) &
LOONGSON_CSRF_TEMP;
+ if (!csr_temp_enable && !loongson_chiptemp[0])
+ return -ENODEV;
+
nr_packages = loongson_sysconf.nr_cpus /
loongson_sysconf.cores_per_package;
--
2.43.0
Some firmware implementations require restoring ra and sp to be
passed as arguments.
Passing them as necessary.
Fixes: 68557c59a550 ("MIPS: Loongson64: Implement PM suspend for LEFI firmware")
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/loongson64/sleeper.S | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/mips/loongson64/sleeper.S b/arch/mips/loongson64/sleeper.S
index 04874b9bf430..cf16877409e2 100644
--- a/arch/mips/loongson64/sleeper.S
+++ b/arch/mips/loongson64/sleeper.S
@@ -11,7 +11,11 @@
LEAF(loongson_lefi_sleep)
SUSPEND_SAVE
- jalr a0
- smp_slave_setup
+ move t9, a0
+ PTR_LA a0, wake
+ move a1, sp
+ jalr t9
+wake:
+ smp_slave_setup
RESUME_RESTORE_REGS_RETURN
END(loongson_lefi_sleep)
--
2.43.0
The correct interrupt line for RTC is line 8 on liointc1.
Fixes: e47084e116fc ("MIPS: Loongson64: DTS: Add RTC support to Loongson-2K1000")
Cc: [email protected]
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
index 3f5255584c30..c3a57a0befa7 100644
--- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
+++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
@@ -92,8 +92,8 @@ liointc1: interrupt-controller@1fe11440 {
rtc0: rtc@1fe07800 {
compatible = "loongson,ls2k1000-rtc";
reg = <0 0x1fe07800 0 0x78>;
- interrupt-parent = <&liointc0>;
- interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
};
uart0: serial@1fe00000 {
--
2.43.0
Some global register address variable may be missing on
specific CPU type, test them before use them.
Cc: [email protected]
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/loongson64/smp.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index 5a990cdef91a..66d049cdcf14 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -466,12 +466,25 @@ static void loongson3_smp_finish(void)
static void __init loongson3_smp_setup(void)
{
int i = 0, num = 0; /* i: physical id, num: logical id */
+ int max_cpus = 0;
init_cpu_possible(cpu_none_mask);
+ for (i = 0; i < ARRAY_SIZE(smp_group); i++) {
+ if (!smp_group[i])
+ break;
+ max_cpus += loongson_sysconf.cores_per_node;
+ }
+
+ if (max_cpus < loongson_sysconf.nr_cpus) {
+ pr_err("SMP Groups are less than the number of CPUs\n");
+ loongson_sysconf.nr_cpus = max_cpus ? max_cpus : 1;
+ }
+
/* For unified kernel, NR_CPUS is the maximum possible value,
* loongson_sysconf.nr_cpus is the really present value
*/
+ i = 0;
while (i < loongson_sysconf.nr_cpus) {
if (loongson_sysconf.reserved_cpus_mask & (1<<i)) {
/* Reserved physical CPU cores */
@@ -492,14 +505,14 @@ static void __init loongson3_smp_setup(void)
__cpu_logical_map[num] = -1;
num++;
}
-
csr_ipi_probe();
ipi_set0_regs_init();
ipi_clear0_regs_init();
ipi_status0_regs_init();
ipi_en0_regs_init();
ipi_mailbox_buf_init();
- ipi_write_enable(0);
+ if (smp_group[0])
+ ipi_write_enable(0);
cpu_set_core(&cpu_data[0],
cpu_logical_map(0) % loongson_sysconf.cores_per_package);
@@ -818,6 +831,9 @@ static int loongson3_disable_clock(unsigned int cpu)
uint64_t core_id = cpu_core(&cpu_data[cpu]);
uint64_t package_id = cpu_data[cpu].package;
+ if (!loongson_chipcfg[package_id] || !loongson_freqctrl[package_id])
+ return 0;
+
if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id));
} else {
@@ -832,6 +848,9 @@ static int loongson3_enable_clock(unsigned int cpu)
uint64_t core_id = cpu_core(&cpu_data[cpu]);
uint64_t package_id = cpu_data[cpu].package;
+ if (!loongson_chipcfg[package_id] || !loongson_freqctrl[package_id])
+ return 0;
+
if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id);
} else {
--
2.43.0
phy-mode should be rgmii-id to match hardware configuration.
Also there should be a phy-handle to reference phy node.
Fixes: f8a11425075f ("MIPS: Loongson64: Add GMAC support for Loongson-2K1000")
Cc: [email protected]
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
index c3a57a0befa7..b2f66f6bb2fe 100644
--- a/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
+++ b/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
@@ -128,7 +128,8 @@ gmac@3,0 {
<13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&liointc0>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
@@ -151,7 +152,8 @@ gmac@3,1 {
<15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_lpi";
interrupt-parent = <&liointc0>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
--
2.43.0