This patch corrects CLKVAL_F field value of VIDEO MAIN CONTROLLER 0 REGITSTER.
Frame Rate is 1 / [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1)
} x {(HSPW+1) + (HBPD +1)
+ (HFPD+1) + (HOZVAL + 1) } x { ( CLKVAL+1 ) / ( Frequency of Clock
source ) } ] and VCLK = Video Clock Source / (CLKVAL +1).
therefore CLKVAL_F should be "CLKVAL_F = Frequency of Clock source /
pixel clock * refresh".
for this, I added refresh value in platform data like below.
static struct s3c_fb_pd_win xxx_fb_win0 = {
/* this is to ensure we use win0 */
.win_mode = {
.refresh = 60,
.pixclock = (66+4+2+480)*(15+5+3+800),
.left_margin = 66,
.right_margin = 2,
.upper_margin = 15,
.lower_margin = 3,
.hsync_len = 4,
.vsync_len = 5,
.xres = 480,
.yres = 800,
},
.max_bpp = 32,
.default_bpp = 24,
};
static struct s3c_fb_platdata xxx_lcd_pdata __initdata = {
.win[0] = &xxx_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC
| VIDCON1_INV_VCLK | VIDCON1_INV_VDEN,
.setup_gpio = s5pc1xx_fb_gpio_setup_24bpp,
};
xxx_machine_init()
{
.
.
.
s3c_fb_set_platdata(&xxx_lcd_pdata);
}
platform data defined in machine code should be setting using
s3c_fb_set_platdata().
I have tested this patch on boards based on s3c6410 and s5pc100 and worked fine.
I attached the patch for s3c-fb.c file.
thanks.
signed-by-off : InKi Dae. <[email protected]>