The radeon driver does speed cap detection on the root PCI device for
the maximum speed with which the adapter can communicate. On ppc64
systems, however, the root device belongs to the Hypervisor, so the
current code would case a null pointer dereference.
I propose to look for the outmost bus with a parent node and get speed
caps from it, though I suppose the cleaner way would be to inspect all
devices along the way and choose the smallest speed cap.
Does anyone have suggestions for this?
Thanks
--
---
/home/lucaskt/work/devdrivers/kernel/linux/drivers/gpu/drm/drm_pci.c
2012-09-26 10:06:00.280549928 -0300
+++ drm_pci.c 2012-09-26 15:38:51.121786353 -0300
@@ -466,6 +466,19 @@
}
EXPORT_SYMBOL(drm_pci_exit);
+static struct pci_dev *drm_get_pcie_root_dev(struct pci_dev *dev)
+{
+ // Go up through all possible busses to get the info for the outmost bus
+ while (!pci_is_root_bus(dev->bus))
+ dev = dev->bus->parent->self;
+
+ // In POWER architectures there's no PCI root device, so it should
just read
+ // the caps from the device itself
+ if (dev->bus->self != NULL)
+ return dev->bus->self;
+ else
+ return dev;
+}
+
int drm_pcie_get_speed_cap_mask(struct drm_device *dev, u32 *mask)
{
struct pci_dev *root;
@@ -479,7 +492,7 @@
if (!pci_is_pcie(dev->pdev))
return -EINVAL;
- root = dev->pdev->bus->self;
+ root = drm_get_pcie_root_dev(dev->pdev);
pos = pci_pcie_cap(root);
if (!pos)
--
Lucas Kannebley Tavares
Software Engineer
IBM Linux Technology Center
On 10/19/12 1:43 PM, Lucas Kannebley Tavares wrote:
> The radeon driver does speed cap detection on the root PCI device for
> the maximum speed with which the adapter can communicate. On ppc64
> systems, however, the root device belongs to the Hypervisor, so the
> current code would case a null pointer dereference.
>
> I propose to look for the outmost bus with a parent node and get speed
> caps from it, though I suppose the cleaner way would be to inspect all
> devices along the way and choose the smallest speed cap.
That (walking all parent nodes) is probably the safest thing to do. I'm
not sure whether it's optimal. It would likely depend on whether you
can meaningfully have a bridge that's faster on the downstream side than
on the upstream.
- ajax
> That (walking all parent nodes) is probably the safest thing to do. I'm
> not sure whether it's optimal. It would likely depend on whether you
> can meaningfully have a bridge that's faster on the downstream side than
> on the upstream.
This is architecture goo at heart - would this be better as a helper in
the PCI and arch PCI code ?
Alan
On Mon, Oct 22, 2012 at 9:44 AM, Alan Cox <[email protected]> wrote:
>> That (walking all parent nodes) is probably the safest thing to do. I'm
>> not sure whether it's optimal. It would likely depend on whether you
>> can meaningfully have a bridge that's faster on the downstream side than
>> on the upstream.
>
> This is architecture goo at heart - would this be better as a helper in
> the PCI and arch PCI code ?
Good point.
POWER is not the only architecture where host bridges do not appear as
devices in PCI config space -- ia64 has that, too. So the comment is
too specific.
The link is a point-to-point thing, so this should be a local
negotiation between the radeon device and the upstream bridge. I
don't see the point of walking any farther up the chain.
drm_pcie_get_speed_cap_mask() should also be changed to use
pcie_capability_read_dword() to avoid any issues with v1/v2 PCI
Express Capability structures.
Bjorn